TDC Implementation in Logicbox mainboard

diff --git a/mboasd8/compile.pl b/mboasd8/compile.pl
new file mode 120000 (symlink)
index 0000000..8a19aa6
--- /dev/null
+++ b/mboasd8/compile.pl
@@ -0,0 +1 @@
+../../trb3sc/scripts/compile.pl
\ No newline at end of file

diff --git a/mboasd8/config_compile_frankfurt.pl b/mboasd8/config_compile_frankfurt.pl
new file mode 100644 (file)
index 0000000..5d35420
--- /dev/null
+++ b/mboasd8/config_compile_frankfurt.pl
@@ -0,0 +1,27 @@
+Familyname  => 'MachXO3LF',
+Devicename  => 'LCMXO3LF-2100E',
+Package     => 'WLCSP49',
+Speedgrade  => '5',
+
+TOPNAME                      => "mbo",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.7_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
+# synplify_path                => '/d/jspc29/lattice/synplify/L-2016.03/',
+# synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
+nodelist_file                => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file                  => '', #name of pin-out file, if not equal TOPNAME
+include_TDC                  => 0,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+no_ltxt2ptxt                 => 1,  #if there is no serdes being used
+make_jed                     => 1,

diff --git a/mboasd8/mbo.lpf b/mboasd8/mbo.lpf
new file mode 100644 (file)
index 0000000..461cad7
--- /dev/null
+++ b/mboasd8/mbo.lpf
@@ -0,0 +1,356 @@
+UGROUP "ffarr0groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][0][7]
+  ;
+  
+UGROUP "ffarr0groupB" BBOX 1 2  
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][0][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][0][7]
+  ;   
+          
+UGROUP "ffarr1groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][1][7]
+  ;
+  
+UGROUP "ffarr1groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][1][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][1][7]
+  ;   
+ 
+UGROUP "ffarr2groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][2][7]
+  ;
+  
+UGROUP "ffarr2groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][2][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][2][7]
+  ;   
+ 
+UGROUP "ffarr3groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][3][7]
+  ;
+  
+UGROUP "ffarr3groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][3][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][3][7]
+  ;    
+  
+UGROUP "ffarr4groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][4][7]
+  ;
+  
+UGROUP "ffarr4groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][4][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][4][7]
+  ; 
+ 
+UGROUP "ffarr5groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][5][7]
+  ;
+  
+UGROUP "ffarr5groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][5][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][5][7]
+  ;   
+ 
+UGROUP "ffarr6groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][6][7]
+  ;
+  
+UGROUP "ffarr6groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][6][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][6][7]
+  ;   
+ 
+UGROUP "ffarr7groupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][7][7]
+  ;
+  
+UGROUP "ffarr7groupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][7][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][7][7]
+  ;   
+ 
+UGROUP "ffarrTgroupA" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[0][8][7]
+  ;
+  
+UGROUP "ffarrTgroupB" BBOX 1 2
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][0]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][1]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][2]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][3]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][4]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][5]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][6]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[1][8][7]
+  BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr[2][8][7]
+  ;     
+          
+REGION "FFARR0A" "R2C24" 1 2 DEVSIZE;
+REGION "FFARR0B" "R3C24" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr0groupA"  REGION "FFARR0A";
+LOCATE UGROUP "ffarr0groupB"  REGION "FFARR0B";
+
+REGION "FFARR1A"  "R2C15" 1 2 DEVSIZE;
+REGION "FFARR1B"  "R3C15" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr1groupA"  REGION "FFARR1A";
+LOCATE UGROUP "ffarr1groupB"  REGION "FFARR1B";
+
+REGION "FFARR2A"  "R2C11" 1 2 DEVSIZE;
+REGION "FFARR2B"  "R3C11" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr2groupA"  REGION "FFARR2A";
+LOCATE UGROUP "ffarr2groupB"  REGION "FFARR2B";
+
+REGION "FFARR3A"  "R2C13" 1 2 DEVSIZE;
+REGION "FFARR3B"  "R3C13" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr3groupA"  REGION "FFARR3A";
+LOCATE UGROUP "ffarr3groupB"  REGION "FFARR3B";
+
+REGION "FFARR4A"  "R12C3" 1 2 DEVSIZE;
+REGION "FFARR4B"  "R13C3" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr4groupA"  REGION "FFARR4A";
+LOCATE UGROUP "ffarr4groupB"  REGION "FFARR4B";
+
+REGION "FFARR5A"  "R12C12" 1 2 DEVSIZE;
+REGION "FFARR5B"  "R13C12" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr5groupA"  REGION "FFARR5A";
+LOCATE UGROUP "ffarr5groupB"  REGION "FFARR5B";
+
+REGION "FFARR6A"  "R12C9" 1 2 DEVSIZE;
+REGION "FFARR6B"  "R13C9" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr6groupA"  REGION "FFARR6A";
+LOCATE UGROUP "ffarr6groupB"  REGION "FFARR6B";
+
+REGION "FFARR7A"  "R12C24" 1 2 DEVSIZE;
+REGION "FFARR7B"  "R13C24" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr7groupA"  REGION "FFARR7A";
+LOCATE UGROUP "ffarr7groupB"  REGION "FFARR7B";
+
+REGION "FFARRTA"  "R2C17" 1 2 DEVSIZE;
+REGION "FFARRTB"  "R3C17" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarrTgroupA"  REGION "FFARRTA";
+LOCATE UGROUP "ffarrTgroupB"  REGION "FFARRTB";
+
+
+
+
+USE PRIMARY NET "THE_TDC/CLKa*";
+USE PRIMARY NET "THE_TDC_CLKa*";
+USE PRIMARY NET "THE_TDC/CLKa[0]";
+USE PRIMARY NET "THE_TDC/CLKa[1]";
+USE PRIMARY NET "THE_TDC/CLKa[2]";
+USE PRIMARY NET "THE_TDC/CLKa[3]";
+USE PRIMARY NET "THE_TDC_CLKa[0]";
+USE PRIMARY NET "THE_TDC_CLKa[1]";
+USE PRIMARY NET "THE_TDC_CLKa[2]";
+USE PRIMARY NET "THE_TDC_CLKa[3]";
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

diff --git a/mboasd8/mbo.prj b/mboasd8/mbo.prj
new file mode 100644 (file)
index 0000000..9fd4da9
--- /dev/null
+++ b/mboasd8/mbo.prj
@@ -0,0 +1,79 @@
+#project files
+
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.7_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+
+add_file -vhdl -lib work "../cores/fifo_36x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
+add_file -vhdl -lib work "../cores/pll_4x266.vhd"
+add_file -vhdl -lib work "../code/ffarray.vhd"
+add_file -vhdl -lib work "../code/pwm.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+#add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../code/uart_sctrl.vhd"
+add_file -vhdl -lib work "mbo.vhd"
+
+
+
+#implementation: "LogicBox"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+
+#device options
+set_option -technology MACHXO3LF
+set_option -part LCMXO3LF_2100E
+set_option -package UWG49CTR
+set_option -speed_grade -5
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "mbo"
+
+# mapper_options
+set_option -frequency 100
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/mbo.edf"
+
+#set log file 
+set_option log_file "workdir/mbo.srf" 
+impl -active "workdir"

diff --git a/mboasd8/mbo.vhd b/mboasd8/mbo.vhd
new file mode 100644 (file)
index 0000000..78746b4
--- /dev/null
+++ b/mboasd8/mbo.vhd
@@ -0,0 +1,311 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- library machxo3lf;
+-- use machxo3lf.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity mbo is
+  port(
+    CLK    : in  std_logic;
+  
+    INPUT  : in  std_logic_vector(7 downto 0);
+    
+    PWM    : out std_logic;
+    TRG    : in  std_logic;
+
+    LED    : inout std_logic_vector(3 downto 0);
+    RX_OUT : out std_logic;
+    TX_IN  : in  std_logic;
+    CBUS   : in  std_logic
+    
+    );
+end entity;
+
+architecture arch of mbo is
+
+--   component OSCH
+--     generic (NOM_FREQ: string := "133.00");
+--     port (
+--       STDBY :IN std_logic;
+--       OSC   :OUT std_logic;
+--       SEDSTDBY :OUT std_logic
+--       );
+--   end component; 
+
+  signal clk_i : std_logic;
+
+  signal uart_rx_data : std_logic_vector(31 downto 0);
+  signal uart_tx_data : std_logic_vector(31 downto 0);
+  signal uart_addr    : std_logic_vector(7 downto 0);
+  signal bus_read     : std_logic := '0';
+  signal bus_write    : std_logic := '0';
+  signal bus_ready    : std_logic; 
+  signal uart_busy    : std_logic; 
+
+  signal sed_error : std_logic;
+  signal sed_debug : std_logic_vector(31 downto 0);
+  signal controlsed_i : std_logic_vector(3 downto 0);
+ 
+  signal f_read, f_empty : std_logic;
+  signal last_f_read, last2_f_read : std_logic;
+  signal f_data          : std_logic_vector(31 downto 0);
+
+--   signal reg         : std_logic_vector(31 downto 0);
+  signal config      : std_logic_vector(3 downto 0);
+  signal config_reg  : std_logic_vector(3 downto 0);
+ 
+  signal pwm_data_i : std_logic_vector(15 downto 0);
+  signal pwm_write_i : std_logic;
+  signal pwm_addr_i  : std_logic_vector(4 downto 0);
+ 
+  signal input_hold : std_logic_vector(7 downto 0);
+  signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(7 downto 0);
+ 
+--   signal edge_rising, edge_falling : std_logic_vector(3 downto 0);
+--   signal pulser       : std_logic;
+  signal last_config : std_logic_vector(3 downto 0);
+  signal led_i : std_logic_vector(3 downto 0);
+  signal timer_i : unsigned(31 downto 0) := (others => '0');
+  signal led_highz : std_logic;
+ 
+  type led_timer_t is array(0 to 3) of unsigned(24 downto 0);
+  signal led_timer : led_timer_t;
+  signal led_state : std_logic_vector(3 downto 0);
+ 
+  type counter_arr is array(0 to 7) of unsigned(23 downto 0);
+  signal input_counter    : counter_arr;
+  signal select_i : std_logic_vector(3 downto 0);
+  signal readcounter : unsigned(15 downto 0);
+  signal uart_debug : std_logic_vector(15 downto 0);
+begin
+
+clk_i <= CLK;
+
+timer_i <= timer_i + 1 when rising_edge(clk_i);
+
+---------------------------------------------------------------------------
+-- UART
+---------------------------------------------------------------------------
+THE_UART : entity work.uart_sctrl
+  generic map(
+    CLOCK_SPEED => 125000000,
+    BAUD => 921076
+    )
+  port map(
+    CLK     => clk_i,
+    RESET   => sed_error,
+    UART_RX => TX_IN,
+    UART_TX => RX_OUT,
+    
+    DATA_OUT  => uart_rx_data,
+    DATA_IN   => uart_tx_data,
+    ADDR_OUT  => uart_addr,       
+    WRITE_OUT => bus_write,
+    READ_OUT  => bus_read,
+    READY_IN  => bus_ready,
+    BUSY_OUT  => uart_busy,
+    
+    DEBUG     => uart_debug
+    );
+
+-- RX_OUT <= TX_IN;
+
+PROC_REGS : process begin
+  wait until rising_edge(clk_i);
+  bus_ready <= '0';
+  f_read <= '0';
+  last2_f_read <= last_f_read; last_f_read <= f_read;
+  pwm_write_i <= '0';
+  if bus_read = '1' then
+    bus_ready <= '1';
+    case uart_addr is
+      when x"00" => uart_tx_data <= x"000000" & config & config_reg;
+      when x"01" => uart_tx_data <= x"00000" & "00" & CBUS & TRG & input_reg_2;
+--       when x"10" => uart_tx_data <= reg;
+      when x"d0" => 
+        f_read <= '1';
+        bus_ready <= '0';
+      when x"ee" => uart_tx_data <= sed_debug;
+      when x"ff" => uart_tx_data(15 downto 0) <= std_logic_vector(readcounter);
+                    readcounter <= readcounter + 1;
+    end case;
+    if uart_addr(7 downto 4) = x"2" then
+      uart_tx_data(31 downto 24) <= uart_addr(3 downto 0) & x"0";
+      uart_tx_data(23 downto 0)  <= std_logic_vector(input_counter(to_integer(unsigned(uart_addr(3 downto 0))))); 
+    end if;
+  elsif bus_write = '1' then
+    case uart_addr is
+      when x"00" =>
+        config_reg <= uart_rx_data(3 downto 0);
+      when x"10" => 
+        select_i <= uart_rx_data(3 downto 0);
+      when x"80" =>
+        pwm_write_i <= '1';
+        pwm_data_i <= uart_rx_data(15 downto 0);
+        pwm_addr_i <= uart_rx_data(28 downto 24);
+--       when x"90" =>
+--         temperature_i <= uart_rx_data(11 downto 0);
+--       when x"91" =>
+--         comp_setting <=  uart_rx_data(15 downto 0);
+      when x"ee" => 
+        controlsed_i <= uart_rx_data(3 downto 0);
+    end case;
+  end if;
+  if last2_f_read = '1' then
+    uart_tx_data <= f_data;
+    bus_ready <= '1';
+  end if;          
+  
+  if config_reg(0) = '1' then
+    if f_empty = '0' and uart_busy = '0' and last2_f_read = '0' and last_f_read = '0' and f_read = '0' and  bus_ready = '0' then
+      f_read <= '1';
+    end if;
+  end if;
+  
+  
+end process;
+
+---------------------------------------------------------------------------
+-- Clock
+---------------------------------------------------------------------------
+-- clk_source: OSCH
+--   generic map ( NOM_FREQ => "2.08" )
+--   port map (
+--     STDBY    => '0',
+--     OSC      => clk_osc,
+--     SEDSTDBY => open
+--   );
+
+---------------------------------------------------------------------------
+-- PWM
+---------------------------------------------------------------------------  
+
+THE_PWM_GEN : entity work.pwm_generator
+  generic map(
+    CHANNELS => 1
+    )
+  port map(
+    CLK        => clk_i,
+    DATA_IN    => pwm_data_i,
+    DATA_OUT   => open,
+    COMP_IN    => (others => '0'),
+    WRITE_IN   => pwm_write_i,
+    ADDR_IN    => pwm_addr_i,
+    PWM(0)     => PWM
+    );
+    
+ 
+---------------------------------------------------------------------------
+-- Input Reg
+--------------------------------------------------------------------------- 
+input_reg_0 <= INPUT  when rising_edge(clk_i); --or input_hold
+input_reg_1 <= input_reg_0 when rising_edge(clk_i);
+input_reg_2 <= input_reg_1 when rising_edge(clk_i);
+
+input_hold  <= INPUT or (input_hold and not input_reg_0);
+
+
+
+---------------------------------------------------------------------------
+-- Input Counter
+--------------------------------------------------------------------------- 
+gen_input_counter : for i in 0 to 7 generate
+  proc_cnt : process begin
+    wait until rising_edge(clk_i);
+    if (input_reg_2(i) =  '1') and (input_reg_1(i) = '0') then
+      input_counter(i) <= input_counter(i) + 1;
+    end if;
+  end process;
+end generate;
+
+
+---------------------------------------------------------------------------
+-- TDC
+--------------------------------------------------------------------------- 
+THE_TDC :  entity work.ffarray
+  generic map(
+    CHANNELS => 9
+    )
+  port map(
+    CLK        => clk_i,
+    RESET_IN   => '0',
+    SIGNAL_IN(7 downto 0)  => INPUT(7 downto 0),
+    SIGNAL_IN(8)  => TRG,
+    SELECT_IN  => select_i,
+    DATA_OUT   => f_data,
+    READ_IN    => f_read,
+    EMPTY_OUT  => f_empty
+    );
+
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  PROC_LED : process begin
+    wait until rising_edge(clk_i);
+    if not (config = last_config) and timer_i(27) = '0'  then
+      led_i <= config;  
+    else
+      led_i <= led_state;
+    end if;  
+  end process;
+
+  PROC_LED_STATE : process begin
+    wait until rising_edge(clk_i);
+    for i in 0 to 3 loop
+      if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then
+        led_state(i) <= not led_state(i);
+        led_timer(i) <= 0;
+      elsif led_timer(i)(23) = '1' then
+        led_state(i) <= input_reg_1(i);
+      else
+        led_timer(i) <= led_timer(i) + 1;
+      end if;
+    end loop;
+  end process;  
+  
+---------------------------------------------------------------------------
+-- Read configuration switch
+---------------------------------------------------------------------------
+process begin
+  wait until rising_edge(clk_i);
+  
+
+  if timer_i(27 downto 10) = 0 then
+    led_highz   <= '1';
+    last_config <= config;
+    if timer_i(9 downto 0) = "11"&x"ff" then 
+      config <= not LED;
+    end if;
+  else
+    led_highz <= '0';
+  end if;
+end process;  
+
+LED <= led_i  when led_highz = '0' else 
+       "ZZZZ"; 
+
+
+
+
+-- THE_SED : entity work.sedcheck
+--   port map(
+--     CLK        => clk_i,
+--     ERROR_OUT  => sed_error,
+--     
+--     CONTROL_IN => controlsed_i,
+--     DEBUG      => sed_debug
+--     );
+
+    
+
+end architecture;
+
+       
+       
\ No newline at end of file

diff --git a/mboasd8/par.p2t b/mboasd8/par.p2t
new file mode 100644 (file)
index 0000000..39a0684
--- /dev/null
+++ b/mboasd8/par.p2t
@@ -0,0 +1,21 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 1
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1

diff --git a/pinout/mbo.lpf b/pinout/mbo.lpf
new file mode 100644 (file)
index 0000000..4a1db0e
--- /dev/null
+++ b/pinout/mbo.lpf
@@ -0,0 +1,54 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+SYSCONFIG MCCLK_FREQ=133 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE ;
+# LOCATE COMP "OUTPUT[2]" SITE "A6" ;
+# LOCATE COMP "OUTPUT[3]" SITE "C5" ;
+# LOCATE COMP "OUTPUT[0]" SITE "B4" ;
+# LOCATE COMP "OUTPUT[1]" SITE "B5" ;
+# LOCATE COMP "CONTROLI" SITE "B1" ;
+# LOCATE COMP "CONTROLO" SITE "A1" ;
+LOCATE COMP "LED[0]" SITE "A7" ;
+LOCATE COMP "LED[1]" SITE "E5" ;
+LOCATE COMP "LED[2]" SITE "C1" ;
+LOCATE COMP "LED[3]" SITE "B2" ;
+LOCATE COMP "INPUT[0]" SITE "B1" ;
+LOCATE COMP "INPUT[1]" SITE "B4" ;
+LOCATE COMP "INPUT[2]" SITE "A6" ;
+LOCATE COMP "INPUT[3]" SITE "C5" ;
+LOCATE COMP "INPUT[4]" SITE "F7" ;
+LOCATE COMP "INPUT[5]" SITE "F3" ;
+LOCATE COMP "INPUT[6]" SITE "F4" ;
+LOCATE COMP "INPUT[7]" SITE "G1" ;
+LOCATE COMP "RX_OUT" SITE "F1" ;
+LOCATE COMP "TX_IN" SITE "C4" ;
+LOCATE COMP "CBUS" SITE "C3" ;
+LOCATE COMP "CLK" SITE "G4" ;
+LOCATE COMP "PWM" SITE "G2";
+LOCATE COMP "TRG" SITE "B5";
+# LOCATE COMP "STATUSO" SITE "G2" ;
+# LOCATE COMP "STATUSI" SITE "G1" ;
+IOBUF PORT "INPUT[0]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[1]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[2]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[3]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[4]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[5]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[6]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "INPUT[7]" IO_TYPE=LVTTL33 HYSTERESIS=SMALL DIFFRESISTOR=OFF ;
+IOBUF PORT "LED[0]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[1]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[2]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[3]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "RX_OUT" IO_TYPE=LVTTL33 ;
+IOBUF PORT "TX_IN" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ;
+IOBUF PORT "PWM" IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
+IOBUF PORT "TRG" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CLK" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
+BANK 0 VCCIO 3.3 V;
+BANK 5 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+
+
+FREQUENCY PORT CLK 125 MHz;
+FREQUENCY NET  clk_osc 133 MHz;
\ No newline at end of file