disable unused debug registers

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index a7b1b5aaafb81877e6b6b7a549df7f69cdd61eec..a4df977a6c00a25be6ce4a06c7b1d1fa9ffea99a 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -374,13 +374,16 @@ end generate;
 -- I/O
 ---------------------------------------------------------------------------
 
---   TEST_LINE(8 downto 1)   <= hdr_io(7 downto 0);
+
+--Debug UART
   hdr_io(8)               <= TEST_LINE(1);
   TEST_LINE(2)           <= hdr_io(9);
+
+--   TEST_LINE(8 downto 1)   <= hdr_io(7 downto 0);
 --   TEST_LINE(14 downto 11) <= time_counter(31 downto 28);
 -- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ;
   --& med_stat_debug(18 downto 8);
-link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc);
+-- link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc);
 
 --TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0);
 --TEST_LINE(8 downto 1) <= clk_sys &  med_stat_debug(9) & med_stat_debug(10) &   med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg;
@@ -428,7 +431,7 @@ link_stat_in_reg <= link_stat_in when rising_edge(clk_full_osc);
     generic map (
       CHANNEL_NUMBER => NUM_TDC_CHANNELS,  -- Number of TDC channels per module
       STATUS_REG_NR  => 21,             -- Number of status regs
-      DEBUG          => c_YES,
+      DEBUG          => c_NO,
       SIMULATION     => c_NO)
     port map (
       RESET              => reset_i,