soda-source written into the bus structure of trb3.

Register access is implemented making use of regIO-example  (by Peter Schakel)
controlling LEDs on trb3; i.e. slowcontrol is tested here.
No more errors in Synplify so this should result in a downloadable and working firmware.
First test is access to trb with trbcmd.

ToDo next:
- design/implement/test reply-checker
- make new project for SODA-client or use conditional synthesis ("generate if")

diff --git a/soda_source.ldf b/soda_source.ldf
index 9e2ac236841d4b24f7be10d3d45b36007722d8aa..4f9bd9f47ad9a897c793c24f60e28af7bc62c1c3 100644 (file)
--- a/soda_source.ldf
+++ b/soda_source.ldf
@@ -11,6 +11,9 @@
         <Source name="source/soda_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="source/soda_source.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -284,6 +287,18 @@
         <Source name="source/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
             <Options top_module="trb3_periph_sodasource"/>
         </Source>
+        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>

diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj
index 8b20186e3a2b4990598eeb4a20be3b9a9a2bef69..288ce9522d159e831944f1f273c0c4399cd6b7af 100644 (file)
--- a/soda_source/soda_source_syn.prj
+++ b/soda_source/soda_source_syn.prj
@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version G-2012.09L-1 
 #--  Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj
-#--  Written on Wed May 22 08:53:18 2013
+#--  Written on Thu Aug  8 09:58:23 2013
 
 
 #project files
@@ -103,6 +103,7 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_f
 add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd"
 add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
 add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "/local/lemmens/lattice/soda/soda_source.vhd"
 
 
 #implementation: "soda_source"

diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 6af9fbe057167f18ea7fa257973fb38af839d198..2b63a242a79c7081462092a8f79d3b52f4f3b49a 100644 (file)
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -76,20 +76,26 @@ package soda_components is
                        --Internal Connection
                        SODA_BURST_PULSE_IN     : in    std_logic := '0';       -- 
                        SODA_CMD_STROBE_IN      : in    std_logic := '0';       -- 
-                       SODA_CMD_WORD_IN                : in    std_logic_vector(31 downto 0) := (others : '0');                --REGIO_CTRL_REG in trbnet handler is 32 bit
+                       SODA_CMD_WORD_IN                : in    std_logic_vector(31 downto 0) := (others => '0');               --REGIO_CTRL_REG in trbnet handler is 32 bit
 
                        RX_DLM_WORD_IN                  : in    std_logic_vector(7 downto 0) := (others => '0');
                        RX_DLM_IN                               : in std_logic;
-                       TX_DLM_OUT                              : out   std_logic := '0';       -- 
-                       TX_DLM_WORD_OUT         : out   std_logic_vector(7 downto 0) := (others => '0')
+                       TX_DLM_OUT                              : out   std_logic;
+                       TX_DLM_WORD_OUT         : out   std_logic_vector(7 downto 0) := (others => '0');
 
-                       SODA_DATA_IN                    : in    std_logic_vector(30 downto 0) := (others : '0');
-                       SODA_DATA_OUT                   : in    std_logic_vector(30 downto 0) := (others : '0');
-                       SODA_ADDR                               : in    std_logic_vector(30 downto 0) := (others : '0');
-                       SODA_READ                               : in    std_logic := '0';
-                       SODA_WRITE                              : in    std_logic := '0';
-                       SODA_ACK                                        : in    std_logic := '0'
-               );
+                       SODA_DATA_IN                    : in    std_logic_vector(31 downto 0) := (others => '0');
+                       SODA_DATA_OUT                   : out   std_logic_vector(31 downto 0) := (others => '0');
+                       SODA_ADDR_IN                    : in    std_logic_vector(3 downto 0) := (others => '0');
+                       SODA_READ_IN                    : in    std_logic := '0';
+                       SODA_WRITE_IN                   : in    std_logic := '0';
+                       SODA_ACK_OUT                    : out   std_logic := '0';
+                       LEDS_ACT_OUT          : out  std_logic;
+                       LEDS_OUT           : out  std_logic_vector(3 downto 0);
+                       SPARE_LINE              : in  std_logic_vector(5 downto 0);
+                       TEST_LINE                               : out  std_logic_vector(15 downto 0);
+               -- Status lines
+                       STAT                                            : out  std_logic_vector(31 downto 0) -- DEBUG
+                       );
        end component;\r
        \r
 component spi_flash_and_fpga_reload

diff --git a/source/soda_d8crc8.vhd b/source/soda_d8crc8.vhd
index b49827ef53fa269dc1c05cefa222b818416c8cdb..ff377543c53b0d51cff37da06e0eb835027064e2 100644 (file)
--- a/source/soda_d8crc8.vhd
+++ b/source/soda_d8crc8.vhd
@@ -31,7 +31,14 @@
 library ieee ;
 use ieee.std_logic_1164.all ;
 use ieee.std_logic_arith.all ;
-use ieee.std_logic_unsigned.all ;
+use ieee.std_logic_unsigned.all ;\r
+\r
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; \r
+use work.soda_components.all;
+
 entity soda_d8crc8 is
        port( 
                CLOCK                   : in std_logic; 

diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd
index 687a501bd773116f4c3096914763ab09dc82eb72..ec4f11a849a56863d9b7814fdd7d78bfb2734c5a 100644 (file)
--- a/source/soda_packet_builder.vhd
+++ b/source/soda_packet_builder.vhd
@@ -2,7 +2,11 @@ library ieee;
 use ieee.std_logic_1164.all;\r
 use ieee.numeric_std.all;\r
 \r
-\r
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; \r
+use work.soda_components.all;
 \r
 entity soda_packet_builder is\r
 port(\r
@@ -22,18 +26,18 @@ end soda_packet_builder;
 \r
 architecture Behavioral of soda_packet_builder is\r
 
-component soda_d8crc8
-       port( 
-               clock                   : in std_logic; 
-               reset                   : in std_logic; 
-               soc                     : in std_logic; 
-               data                    : in std_logic_vector(7 downto 0); 
-               data_valid      : in std_logic; 
-               eoc                     : in std_logic; 
-               crc                     : out std_logic_vector(7 downto 0); 
-               crc_valid       : out std_logic 
-       );
-end component;
+--component soda_d8crc8
+--     port( 
+--             clock                   : in std_logic; 
+--             reset                   : in std_logic; 
+--             soc                     : in std_logic; 
+--             data                    : in std_logic_vector(7 downto 0); 
+--             data_valid      : in std_logic; 
+--             eoc                     : in std_logic; 
+--             crc                     : out std_logic_vector(7 downto 0); 
+--             crc_valid       : out std_logic 
+--     );
+--end component;
 
 --     constant        c_K287                                          : std_logic_vector(7 downto 0) := x"FB";\r
 \r

diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd
index 916464c402de5d0913afd9e94a28996e8a2f00bb..17ab0daf66b51df0966e72fe3a77f039debae687 100644 (file)
--- a/source/soda_packet_handler.vhd
+++ b/source/soda_packet_handler.vhd
@@ -2,6 +2,11 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; \r
+use work.soda_components.all;
 
 entity soda_packet_handler is
 port(
@@ -19,18 +24,18 @@ end soda_packet_handler;
 
 architecture Behavioral of soda_packet_handler is
 
-       component soda_d8crc8
-               port( 
-                       clock                   : in std_logic; 
-                       reset                   : in std_logic; 
-                       soc                     : in std_logic; 
-                       data                    : in std_logic_vector(7 downto 0); 
-                       data_valid      : in std_logic; 
-                       eoc                     : in std_logic; 
-                       crc                     : out std_logic_vector(7 downto 0); 
-                       crc_valid       : out std_logic 
-               );
-       end component;
+--     component soda_d8crc8
+--             port( 
+--                     clock                   : in std_logic; 
+--                     reset                   : in std_logic; 
+--                     soc                     : in std_logic; 
+--                     data                    : in std_logic_vector(7 downto 0); 
+--                     data_valid      : in std_logic; 
+--                     eoc                     : in std_logic; 
+--                     crc                     : out std_logic_vector(7 downto 0); 
+--                     crc_valid       : out std_logic 
+--             );
+--     end component;
 
        constant        c_K287                                          : std_logic_vector(7 downto 0) := x"FB";
 

diff --git a/source/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd
index 7cefc6d015a3605cbcf967e3b544cfbf2098e734..5f765298d8859a6e8c8889665879c5eb22ec3d07 100644 (file)
--- a/source/soda_superburst_gen.vhd
+++ b/source/soda_superburst_gen.vhd
@@ -4,6 +4,11 @@ use ieee.numeric_std.all;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use ieee.std_logic_signed.all;
 
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; \r
+use work.soda_components.all;
 
 entity soda_superburst_gen is
        generic(

diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd
index ab3d2ffaed3173884377260d80c2ba82a494745a..d84ed9b91f2ce493cc5340290a4dfa895fd6f26a 100644 (file)
--- a/source/trb3_periph_sodasource.vhd
+++ b/source/trb3_periph_sodasource.vhd
@@ -194,15 +194,16 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal sci2_data_out : std_logic_vector(7 downto 0);
   signal sci2_addr     : std_logic_vector(8 downto 0);  
 
-       --SODA\r
+       --SODA
        signal soda_ack      : std_logic;
        signal soda_nack     : std_logic;
        signal soda_write    : std_logic;
        signal soda_read     : std_logic;
-       signal soda_data_in  : std_logic_vector(7 downto 0);
-       signal soda_data_out : std_logic_vector(7 downto 0);
-       signal soda_addr     : std_logic_vector(8 downto 0);  
-\r
+       signal soda_data_in  : std_logic_vector(31 downto 0);
+       signal soda_data_out : std_logic_vector(31 downto 0);
+       signal soda_addr     : std_logic_vector(3 downto 0);  
+       signal soda_leds     : std_logic_vector(3 downto 0);  
+
        --TDC
   signal hit_in_i : std_logic_vector(63 downto 0);
       
@@ -212,7 +213,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
   signal rx_dlm_i          : std_logic;
   signal tx_dlm_word       : std_logic_vector(7 downto 0);
   signal rx_dlm_word       : std_logic_vector(7 downto 0);
-\r
+
        --SODA
        signal rst_S                                                    : std_logic;
        signal clk_S                                                    : std_logic;
@@ -224,6 +225,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
        signal SOB_S                                                    : std_logic := '0';
        signal dlm_word_S                                               : std_logic_vector(7 downto 0)  := (others => '0');
        signal dlm_valid_S                                      : std_logic;
+       
 begin
 ---------------------------------------------------------------------------
 -- Reset Generation
@@ -406,8 +408,8 @@ THE_HUB : trb_net16_hub_base
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
       PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       others => 0)
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       3 => 4,       others => 0)
       )
     port map(
       CLK   => clk_sys_i,
@@ -450,7 +452,7 @@ THE_HUB : trb_net16_hub_base
       BUS_DATAREADY_IN(1)                 => sci1_ack,
       BUS_WRITE_ACK_IN(1)                 => sci1_ack,
       BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',\r
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
                
       --SCI soda test Media Interface
       BUS_READ_ENABLE_OUT(2)              => sci2_read,
@@ -464,22 +466,21 @@ THE_HUB : trb_net16_hub_base
       BUS_DATAREADY_IN(2)                 => sci2_ack,
       BUS_WRITE_ACK_IN(2)                 => sci2_ack,
       BUS_NO_MORE_DATA_IN(2)              => '0',
-      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,\r
+      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,
                
                      --soda Slow-control Interface
       BUS_READ_ENABLE_OUT(3)              => soda_read,
       BUS_WRITE_ENABLE_OUT(3)             => soda_write,
-      BUS_DATA_OUT(3*32+7 downto 3*32)    => soda_data_in,
-      BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
-      BUS_ADDR_OUT(3*16+8 downto 3*16)    => soda_addr,
-      BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
+      BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
+      BUS_ADDR_OUT(3*16+3 downto 3*16)         => soda_addr,
+      BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
       BUS_TIMEOUT_OUT(3)                  => open,
-      BUS_DATA_IN(3*32+7 downto 3*32)     => soda_data_out,
+      BUS_DATA_IN(3*32+31 downto 3*32)    => soda_data_out,
       BUS_DATAREADY_IN(3)                 => soda_ack,
       BUS_WRITE_ACK_IN(3)                 => soda_ack,
       BUS_NO_MORE_DATA_IN(3)              => '0',
       BUS_UNKNOWN_ADDR_IN(3)              => soda_nack,
-\r
+
                STAT_DEBUG => open
       );
 
@@ -569,48 +570,53 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
 
    
 ---------------------------------------------------------------------------
--- The Soda Source
+-- The Soda Central
 ---------------------------------------------------------------------------         
-  tx_dlm_i <= '0';
-  tx_dlm_word <= x"00";\r
+--  tx_dlm_i <= '0';
+--  tx_dlm_word <= x"00";
         
-       \r
-       superburst_gen :  super_burst_generator
-               generic map(BURST_COUNT         => 16)
-               port map(
-                       SYSCLK                                  =>      clk_sys_i,      --clk_S,
-                       RESET                                           =>      reset_i,                --rst_S,
-                       CLEAR                                           =>      '0',
-                       CLK_EN                                  =>      '0',
-                       --Internal Connection
-                       SODA_BURST_PULSE_IN     =>      SOB_S,
-                       START_OF_SUPERBURST     =>      SOS_S,
-                       SUPER_BURST_NR_OUT      =>      super_burst_nr_S
-               );
-
-       packet_builder : soda_packet_builder
-               port map(
-                       SYSCLK                                  =>      clk_sys_i,      --clk_S,
-                       RESET                                           =>      reset_i,                --rst_S,
-                       CLEAR                                           =>      '0',
-                       CLK_EN                                  => '0',
-                       --Internal Connection
-                       SODA_CMD_STROBE_IN      => soda_cmd_strobe_S,
-                       START_OF_SUPERBURST     => SOS_S,
-                       SUPER_BURST_NR_IN               => super_burst_nr_S,
-                       SODA_CMD_WORD_IN                => soda_cmd_word_S,
-                       TX_DLM_OUT                              => dlm_valid_S,
-                       TX_DLM_WORD_OUT         => dlm_word_S
-               
-                       );
+THE_SODA_SOURCE : soda_source
+       port map(
+               SYSCLK                                  => clk_sys_i,
+               RESET                                           => reset_i,
+               CLEAR                                           => clear_i,
+               CLK_EN                                  => '1',
+               --Internal Connection
+               SODA_BURST_PULSE_IN     => SOB_S,
+               SODA_CMD_STROBE_IN      => soda_cmd_strobe_S,
+               SODA_CMD_WORD_IN                => soda_cmd_word_S,
+
+               RX_DLM_WORD_IN                  => rx_dlm_word,
+               RX_DLM_IN                               => rx_dlm_i,
+               TX_DLM_OUT                              => tx_dlm_i, 
+               TX_DLM_WORD_OUT         => tx_dlm_word,
+
+               SODA_DATA_IN                    => soda_data_in,
+               SODA_DATA_OUT                   => soda_data_out,
+               SODA_ADDR_IN                    => soda_addr,
+               SODA_READ_IN                    => soda_read,
+               SODA_WRITE_IN                   => soda_write,
+               SODA_ACK_OUT                    => soda_ack,\r
+               LEDS_ACT_OUT                    =>      open,\r
+               LEDS_OUT                                        =>      soda_leds,
+               SPARE_LINE                              =>      open,\r
+               TEST_LINE                               =>      open,\r
+               STAT                                            =>      open
+       );
+--end soda_source;
+
    
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
-  LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
-  LED_YELLOW <= '1';
-  LED_GREEN  <= not med_stat_op(9);
-  LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
+--     LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+--     LED_YELLOW <= '1';
+--     LED_GREEN  <= not med_stat_op(9);
+--     LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
+       LED_ORANGE <= soda_leds(0);
+       LED_YELLOW <= soda_leds(1);
+       LED_GREEN  <= soda_leds(2);
+       LED_RED    <= soda_leds(3);
 
 ---------------------------------------------------------------------------
 -- Test Connector
@@ -628,4 +634,4 @@ THE_SYNC_LINK : med_ecp3_sfp_sync
 
 
 
-end trb3_periph_sodasource_arch;
+end trb3_periph_sodasource_arch;
\ No newline at end of file