--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.version.all;
+
+entity mdc_oepb is
+ port(
+ --Clocks
+ CLK : in std_logic;
+ --Reset
+ --Optical link
+ TXP : out std_logic;
+ TXN : out std_logic;
+ RXP : in std_logic;
+ RXN : in std_logic;
+ SD : in std_logic;
+ --LED
+ D : out std_logic_vector(4 downto 1);
+ ONEWIRE : inout std_logic;
+ --Flash FF, Watchdog
+ WATCHDOG : out std_logic;
+ CLK_FF : out std_logic;
+ DATA_FF : out std_logic;
+ --ADC
+ ADC_SCK : out std_logic;
+ ADC_SDI : out std_logic;
+ ADC_SDO : in std_logic;
+ ADC_CONVST : out std_logic;
+ --Debugging
+ TAD : out std_logic_vector(8 downto 0); --TAD 8 downto 0
+ LB : out std_logic_vector(7 downto 0) --REN, DRE, ENB, DRB, ENR, DRA, ADI1, ADI0
+ );
+end entity;
+
+
+architecture mdc_oepb_arch of mdc_oepb is
+
+ component pll_in25_out100 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic
+ );
+ end component;
+
+ component trb_net16_med_ecp_fot is
+ port(
+ CLK : in std_logic;
+ CLK_25 : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+
+ --SFP Connection
+ TXP : out std_logic;
+ TXN : out std_logic;
+ RXP : in std_logic;
+ RXN : in std_logic;
+ SD : in std_logic;
+
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+ end component;
+
+ component adc_ltc2308_readout is
+ generic(
+ CLOCK_FREQUENCY : integer := 100 --MHz
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ ADC_SCK : out std_logic;
+ ADC_SDI : out std_logic;
+ ADC_SDO : in std_logic;
+ ADC_CONVST : out std_logic;
+
+ DAT_ADDR_IN : in std_logic_vector(5 downto 0);
+ DAT_READ_EN_IN : in std_logic;
+ DAT_WRITE_EN_IN : in std_logic;
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ DAT_DATA_IN : in std_logic_vector(31 downto 0);
+ DAT_DATAREADY_OUT : out std_logic;
+ DAT_NO_MORE_DATA_OUT : out std_logic;
+ DAT_WRITE_ACK_OUT : out std_logic;
+ DAT_UNKNOWN_ADDR_OUT : out std_logic;
+ DAT_TIMEOUT_IN : in std_logic;
+
+ STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_endpoint_hades_full is
+ generic (
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ IBUF_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6);
+ IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+ INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_NO);
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_yES,c_yeS,c_NO);
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F100";
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_OUT : out std_logic;
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';
+
+
+ --Data Port
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_OUT: out std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);
+ IPU_DATAREADY_IN : in std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN : in std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT : out std_logic;
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
+ REGIO_IDRAM_WR_IN : in std_logic := '0';
+ REGIO_ONEWIRE_INOUT : inout std_logic;
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
+
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
+ MED_STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_MPLEX : in std_logic_vector (31 downto 0);
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0);
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0)
+ );
+ end component;
+
+ component ram_dp is
+ generic(
+ depth : integer := 3;
+ width : integer := 16
+ );
+ port(
+ CLK : in std_logic;
+ wr1 : in std_logic;
+ a1 : in std_logic_vector(depth-1 downto 0);
+ dout1 : out std_logic_vector(width-1 downto 0);
+ din1 : in std_logic_vector(width-1 downto 0);
+ a2 : in std_logic_vector(depth-1 downto 0);
+ dout2 : out std_logic_vector(width-1 downto 0)
+ );
+ end component;
+
+ signal CLK_100 : std_logic;
+ signal pll_locked : std_logic;
+ signal test_counter : unsigned(25 downto 0);
+ signal reset : std_logic;
+ signal reset_counter : unsigned(23 downto 0) := x"000000";
+
+
+ signal MED_DATA_IN, MED_DATA_OUT : std_logic_vector(16-1 downto 0);
+ signal MED_PACKET_NUM_IN, MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal MED_DATAREADY_IN, MED_DATAREADY_OUT : std_logic;
+ signal MED_READ_IN, MED_READ_OUT : std_logic;
+ signal MED_STAT_OP : std_logic_vector(16-1 downto 0);
+ signal MED_CTRL_OP : std_logic_vector(16-1 downto 0);
+ signal MED_STAT_DEBUG : std_logic_vector(63 downto 0);
+ signal MED_CTRL_DEBUG : std_logic_vector(15 downto 0);
+
+ signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
+ signal LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal LVL1_TRG_RELEASE_IN : std_logic;
+
+ signal IPU_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal IPU_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal IPU_START_READOUT_OUT : std_logic;
+ signal IPU_DATA_IN : std_logic_vector(31 downto 0);
+ signal IPU_DATAREADY_IN : std_logic;
+ signal IPU_READOUT_FINISHED_IN : std_logic;
+ signal IPU_READ_OUT : std_logic;
+ signal IPU_LENGTH_IN : std_logic_vector(15 downto 0);
+ signal IPU_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal ipu_counter : unsigned(15 downto 0);
+
+ signal REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal REGIO_REGISTERS_IN : std_logic_vector(32*2**(3)-1 downto 0);
+ signal REGIO_REGISTERS_OUT : std_logic_vector(32*2**(3)-1 downto 0);
+ signal REGIO_ADDR_OUT : std_logic_vector(15 downto 0);
+ signal REGIO_READ_ENABLE_OUT : std_logic;
+ signal REGIO_WRITE_ENABLE_OUT : std_logic;
+ signal REGIO_DATA_OUT : std_logic_vector(31 downto 0);
+ signal REGIO_DATA_IN : std_logic_vector(31 downto 0);
+ signal REGIO_DATAREADY_IN : std_logic;
+ signal REGIO_NO_MORE_DATA_IN : std_logic;
+ signal REGIO_WRITE_ACK_IN : std_logic;
+ signal REGIO_UNKNOWN_ADDR_IN : std_logic;
+ signal REGIO_TIMEOUT_OUT : std_logic;
+ signal REGIO_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
+ signal REGIO_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
+ signal REGIO_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
+ signal REGIO_IDRAM_WR_IN : std_logic;
+
+ signal adc_addr : std_logic_vector(5 downto 0);
+ signal adc_read : std_logic;
+ signal adc_write : std_logic;
+ signal adc_data_out : std_logic_vector(31 downto 0);
+ signal adc_data_in : std_logic_vector(31 downto 0);
+ signal adc_dataready : std_logic;
+ signal adc_no_more_data : std_logic;
+ signal adc_write_ack : std_logic;
+ signal adc_unknown_addr : std_logic;
+ signal adc_timeout : std_logic;
+ signal adc_stat : std_logic_vector(31 downto 0);
+
+ signal reg_REGIO_ADDR : std_logic_vector(15 downto 0);
+ signal reg_REGIO_READ : std_logic;
+ signal last_reg_REGIO_READ : std_logic;
+ signal reg_REGIO_WRITE : std_logic;
+
+ signal thresh_mem_data : std_logic_vector(7 downto 0);
+ signal thresh_mem_data_out : std_logic_vector(7 downto 0);
+ signal thresh_mem_write: std_logic;
+ signal thresh_mem_read : std_logic;
+ signal thresh_mem_addr : std_logic_vector(6 downto 0);
+
+
+begin
+---------------------------------------------------------------------
+-- PLL: 100 MHz
+---------------------------------------------------------------------
+ PLL100 : pll_in25_out100
+ port map(
+ CLK => CLK,
+ CLKOP => CLK_100,
+ LOCK => pll_locked
+ );
+
+
+
+-- reset <= c_reset or not pll25_lock;
+---------------------------------------------------------------------
+-- Reset process
+---------------------------------------------------------------------
+ THE_RESET_COUNTER_PROC: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ reset_counter <= reset_counter + "1";
+ reset <= '1';
+ if( reset_counter = x"FFFFEF" ) then
+ reset <= '0';
+ reset_counter <= x"FFFFEF";
+ end if;
+ end if;
+ end process;
+
+
+---------------------------------------------------------------------
+-- Flash FF
+---------------------------------------------------------------------
+
+ CLK_FF <= '0';
+ DATA_FF <= '0';
+
+
+
+---------------------------------------------------------------------
+-- trbnet endpoint
+---------------------------------------------------------------------
+ API: trb_net16_endpoint_hades_full
+ generic map(
+ REGIO_NUM_STAT_REGS => 3,
+ REGIO_NUM_CTRL_REGS => 3,
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS => (others => '0'),
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS => (others => '1'),
+ REGIO_USED_CTRL_BITMASK => (others => '1'),
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
+ )
+ port map(
+ CLK => CLK_100,
+ RESET => reset,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_STAT_OP_IN => MED_STAT_OP,
+ MED_CTRL_OP_OUT => MED_CTRL_OP,
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT,
+ LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+
+ --Data Port
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN,
+ REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT,
+ REGIO_REGISTERS_IN => REGIO_REGISTERS_IN,
+ REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT,
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => REGIO_IDRAM_DATA_IN,
+ REGIO_IDRAM_DATA_OUT => REGIO_IDRAM_DATA_OUT,
+ REGIO_IDRAM_ADDR_IN => REGIO_IDRAM_ADDR_IN,
+ REGIO_IDRAM_WR_IN => REGIO_IDRAM_WR_IN,
+ REGIO_ONEWIRE_INOUT => ONEWIRE,
+ REGIO_ONEWIRE_MONITOR_IN => '0',
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open
+ );
+
+---------------------------------------------------------------------
+-- LVL1 handler
+---------------------------------------------------------------------
+ LVL1_ERROR_PATTERN_IN <= (others => '0');
+ LVL1_TRG_RELEASE_IN <= '1';
+
+---------------------------------------------------------------------
+-- IPU Data channel handler
+---------------------------------------------------------------------
+
+ IPU_LENGTH_IN <= x"0005";
+ IPU_ERROR_PATTERN_IN <= (others => '0');
+
+ process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ IPU_READOUT_FINISHED_IN <= '0';
+ ipu_counter <= ipu_counter;
+ IPU_DATAREADY_IN <= '0';
+ if IPU_START_READOUT_OUT = '1' then
+ IPU_DATAREADY_IN <= IPU_DATAREADY_IN;
+ if IPU_DATAREADY_IN = '0' and IPU_READOUT_FINISHED_IN = '0' then
+ ipu_counter <= ipu_counter + 1;
+ IPU_DATAREADY_IN <= '1';
+ elsif IPU_DATAREADY_IN = '1' and IPU_READ_OUT = '1' then
+ IPU_DATAREADY_IN <= '0';
+ end if;
+ if ipu_counter = x"5" or IPU_READOUT_FINISHED_IN = '1' then
+ ipu_counter <= (others => '0');
+ IPU_DATAREADY_IN <= '0';
+ IPU_READOUT_FINISHED_IN <= '1';
+ end if;
+ else
+ ipu_counter <= (others => '0');
+ end if;
+ end if;
+ end process;
+ IPU_DATA_IN(15 downto 0) <= std_logic_vector(ipu_counter);
+ IPU_DATA_IN(31 downto 16) <= std_logic_vector(0 - unsigned(ipu_counter));
+
+
+
+---------------------------------------------------------------------
+-- SlowControl Handler
+---------------------------------------------------------------------
+
+
+ REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 0) <= (others => '0');
+
+--These are your registers:
+ REGIO_REGISTERS_IN <= (others => '0');
+ --REGIO_REGISTERS_OUT;
+
+ REGIO_IDRAM_DATA_IN <= (others => '0');
+ REGIO_IDRAM_ADDR_IN <= (others => '0');
+ REGIO_IDRAM_WR_IN <= '0';
+
+-- Memory map:
+-- full range: 8000 - FFFF
+-- 8000 - 80FF ADC (17)
+-- 9000 - 9FFF SPI
+-- A000 - A7FF Threshold Bytes (16)
+-- F000 - F00F Test readout addresses (15-0)
+
+
+
+THE_REG_DAT_ADDR : process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ if REGIO_READ_ENABLE_OUT = '1' or REGIO_WRITE_ENABLE_OUT = '1' then
+ reg_REGIO_ADDR <= REGIO_ADDR_OUT;
+ end if;
+ reg_REGIO_READ <= REGIO_READ_ENABLE_OUT;
+ reg_REGIO_WRITE <= REGIO_WRITE_ENABLE_OUT;
+ last_reg_REGIO_READ <= reg_REGIO_READ;
+ end if;
+ end process;
+
+
+THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
+ begin
+ if rising_edge(CLK_100) then
+ REGIO_WRITE_ACK_IN <= '0';
+ REGIO_NO_MORE_DATA_IN <= '0';
+ REGIO_DATAREADY_IN <= '0';
+ REGIO_DATA_IN <= (others => '0');
+ REGIO_UNKNOWN_ADDR_IN <= '0';
+
+ adc_read <= '0';
+ adc_write <= '0';
+ adc_data_in <= REGIO_DATA_OUT;
+ adc_addr <= REGIO_ADDR_OUT(5 downto 0);
+ adc_timeout <= REGIO_TIMEOUT_OUT;
+
+ thresh_mem_data <= REGIO_DATA_OUT(7 downto 0);
+ thresh_mem_addr <= REGIO_ADDR_OUT(6 downto 0);
+ thresh_mem_write <= '0';
+ thresh_mem_read <= '0';
+
+ if reg_REGIO_ADDR(15 downto 7) = x"A0"&'0' then
+ thresh_mem_write <= reg_REGIO_WRITE;
+ thresh_mem_read <= reg_REGIO_READ;
+ REGIO_DATA_IN(7 downto 0) <= thresh_mem_data_out;
+ REGIO_DATA_IN(31 downto 8) <= (others => '0');
+ REGIO_UNKNOWN_ADDR_IN <= '0';
+ REGIO_NO_MORE_DATA_IN <= '0';
+ REGIO_WRITE_ACK_IN <= reg_REGIO_WRITE;
+ REGIO_DATAREADY_IN <= last_reg_REGIO_READ;
+
+ elsif reg_REGIO_ADDR(15 downto 8) = x"80" then
+ REGIO_DATA_IN <= adc_data_out;
+ REGIO_DATAREADY_IN <= adc_dataready;
+ REGIO_NO_MORE_DATA_IN <= adc_no_more_data;
+ REGIO_WRITE_ACK_IN <= adc_write_ack;
+ REGIO_UNKNOWN_ADDR_IN <= adc_unknown_addr;
+ adc_write <= reg_REGIO_WRITE;
+ adc_read <= reg_REGIO_READ;
+
+ else
+ REGIO_UNKNOWN_ADDR_IN <= reg_REGIO_READ or reg_REGIO_WRITE;
+ end if;
+ end if;
+ end process;
+
+---------------------------------------------------------------------
+-- Threshold memory
+---------------------------------------------------------------------
+ THE_THRESH_MEM : ram_dp
+ generic map(
+ depth => 7,
+ width => 8
+ )
+ port map(
+ CLK => CLK_100,
+ wr1 => thresh_mem_write,
+ a1 => thresh_mem_addr,
+ dout1 => thresh_mem_data_out,
+ din1 => thresh_mem_data,
+ a2 => (others => '0'),
+ dout2 => open
+ );
+
+---------------------------------------------------------------------
+-- ADC
+---------------------------------------------------------------------
+ THE_ADC : adc_ltc2308_readout
+ port map(
+ CLK => CLK_100,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ ADC_SCK => ADC_SCK,
+ ADC_SDI => ADC_SDI,
+ ADC_SDO => ADC_SDO,
+ ADC_CONVST => ADC_CONVST,
+
+ DAT_ADDR_IN => adc_addr,
+ DAT_READ_EN_IN => adc_read,
+ DAT_WRITE_EN_IN => adc_write,
+ DAT_DATA_OUT => adc_data_out,
+ DAT_DATA_IN => adc_data_in,
+ DAT_DATAREADY_OUT => adc_dataready,
+ DAT_NO_MORE_DATA_OUT => adc_no_more_data,
+ DAT_WRITE_ACK_OUT => adc_write_ack,
+ DAT_UNKNOWN_ADDR_OUT => adc_unknown_addr,
+ DAT_TIMEOUT_IN => adc_timeout,
+
+ STAT_VOLTAGES_OUT => adc_stat
+ );
+
+
+---------------------------------------------------------------------
+-- Optical Uplink
+---------------------------------------------------------------------
+ THE_MED_INTERFACE : trb_net16_med_ecp_fot
+ port map(
+ CLK => CLK_100,
+ CLK_25 => CLK,
+ CLK_EN => '1',
+ RESET => RESET,
+
+ --Internal Connection
+ MED_DATA_IN => MED_DATA_OUT,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT,
+ MED_DATAREADY_IN => MED_DATAREADY_OUT,
+ MED_READ_OUT => MED_READ_IN,
+ MED_DATA_OUT => MED_DATA_IN,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN,
+ MED_DATAREADY_OUT => MED_DATAREADY_IN,
+ MED_READ_IN => MED_READ_OUT,
+
+ --SFP Connection
+ TXP => TXP,
+ TXN => TXN,
+ RXP => RXP,
+ RXN => RXN,
+ SD => SD,
+
+ -- Status and control port
+ STAT_OP => MED_STAT_OP,
+ CTRL_OP => MED_CTRL_OP,
+ STAT_DEBUG => MED_STAT_DEBUG,
+ CTRL_DEBUG => MED_CTRL_DEBUG
+ );
+
+---------------------------------------------------------------------
+-- Outputs to Logic Analyzer
+---------------------------------------------------------------------
+-- TAD(7 downto 0) <= med_dataready_in & MED_PACKET_NUM_IN & med_data_in(3 downto 0);
+ TAD(7 downto 0) <= MED_STAT_DEBUG(48 downto 41);
+ TAD(8) <= CLK;
+ LB(7 downto 0) <= MED_STAT_DEBUG(40) & MED_STAT_DEBUG(38 downto 32);
+
+
+
+---------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------
+ D(1) <= not MED_STAT_DEBUG(1);
+ D(2) <= not MED_STAT_OP(9);
+ D(3) <= not MED_STAT_DEBUG(7);
+ D(4) <= not MED_STAT_DEBUG(8);
+
+
+
+---------------------------------------------------------------------
+-- List of debugging signals
+---------------------------------------------------------------------
+--
+-- STAT_OP(2 downto 0) <= med_error;
+-- STAT_OP(8 downto 3) <= (others => '0');
+-- STAT_OP(9) <= link_led;
+-- STAT_OP(10) <= rx_led;
+-- STAT_OP(11) <= tx_led;
+-- STAT_OP(12) <= '0';
+-- STAT_OP(13) <= buf_RESET_TRBNET_OUT;
+-- STAT_OP(14) <= reset_me; -- reset out
+-- STAT_OP(15) <= buf_RESET_TRBNET_OUT;
+
+-- STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
+-- stat_debug(3 downto 0) <= state_bits;
+-- stat_debug(4) <= align_me;
+-- stat_debug(5) <= buf_swap_bytes;
+-- stat_debug(6) <= resync;
+-- stat_debug(7) <= sfp_missing_in;
+-- stat_debug(8) <= sfp_los_in;
+-- stat_debug(31 downto 9) <= (others => '0');
+-- STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0);
+-- STAT_DEBUG(40) <= rx_fifo_write_en;
+-- STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout;
+-- STAT_DEBUG(63 downto 49) <= (others => '0');
+
+
+end architecture;
+
jspc29 / mdcoep.git / commitdiff