64 word ring buffer option

diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd
index ac166dd986f24c7e78ebb97d1a332826eb4e34ee..0af6275890c6b9517df8846c70ed82a868ba983b 100644 (file)
--- a/32PinAddOn/config.vhd
+++ b/32PinAddOn/config.vhd
@@ -28,7 +28,7 @@ package config is
   constant PHYSICAL_INPUTS : integer := 32;
 
 --Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
-    constant USE_64_FIFO : integer := c_YES;
+    constant USE_64_FIFO : integer := c_NO;
 
 --Run wih 125 MHz instead of 100 MHz
     constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!

diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd
index 5987129b0d23bc277aff3a9917321fed1176c3de..f0fcb5dfdeffc2027bb504a3d03dc55703312583 100644 (file)
--- a/ADA_Addon/config.vhd
+++ b/ADA_Addon/config.vhd
@@ -20,7 +20,10 @@ package config is
 
 --Add logic to generate configurable trigger signal from input signals.
     constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;
-    
+
+--Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
+    constant USE_64_FIFO : integer := c_NO;
+
 --Run wih 125 MHz instead of 100 MHz
     constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!
     

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 518e87ddb0f5263cd9dec534e16e237bb0928412..12b300be69b6ed87f5713ffb66bbbfa9a8db71f8 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -450,6 +450,21 @@ package trb3_components is
       AlmostFull : out std_logic);
   end component FIFO_DC_36x128_OutReg;
 
+  component FIFO_DC_36x64_OutReg is
+    port (
+      Data       : in  std_logic_vector(35 downto 0);
+      WrClock    : in  std_logic;
+      RdClock    : in  std_logic;
+      WrEn       : in  std_logic;
+      RdEn       : in  std_logic;
+      Reset      : in  std_logic;
+      RPReset    : in  std_logic;
+      Q          : out std_logic_vector(35 downto 0);
+      Empty      : out std_logic;
+      Full       : out std_logic;
+      AlmostFull : out std_logic);
+  end component FIFO_DC_36x64_OutReg;
+
   component FIFO_36x128_OutReg_Counter is
     port (
       Data    : in  std_logic_vector(35 downto 0);

diff --git a/cbmtof/config.vhd b/cbmtof/config.vhd
index a2d3212e91690e6bfd9be2ccb62ff8ae1f5a87a7..606270f6a0429f0312f35a367cfe63846e5d8cdc 100644 (file)
--- a/cbmtof/config.vhd
+++ b/cbmtof/config.vhd
@@ -23,11 +23,14 @@ package config is
   constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;  --not compatible with cbmtof!
 
 --Do histos of all inputs
-  constant INCLUDE_STATISTICS : integer := c_NO;
+  constant INCLUDE_STATISTICS : integer := c_YES;
 
 --number of real inputs to the FPGA
   constant PHYSICAL_INPUTS : integer := 32;
 
+--Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
+  constant USE_64_FIFO : integer := c_NO;
+
 --Run wih 125 MHz instead of 100 MHz
   constant USE_125_MHZ : integer := c_NO;  --not implemented yet!
 

diff --git a/hadesstart/config.vhd b/hadesstart/config.vhd
index 597ad076db5a03191180452dd561587c48e27484..e5681dd5cb83d2bfd6955f6ac27794126751441d 100644 (file)
--- a/hadesstart/config.vhd
+++ b/hadesstart/config.vhd
@@ -1,5 +1,5 @@
 library ieee;
-USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.trb_net_std.all;
 
@@ -11,36 +11,38 @@ package config is
 ------------------------------------------------------------------------------
 
 --TDC settings
-    constant NUM_TDC_CHANNELS       : integer range 1 to 65 := 17;  
-    constant NUM_TDC_CHANNELS_POWER2: integer range 0 to 6  := 4;  --the nearest power of two, for convenience reasons 
-    constant USE_DOUBLE_EDGE        : integer := c_YES;
-    
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 33;
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
+  constant USE_DOUBLE_EDGE         : integer               := c_YES;
+
 --use only every fourth input as in HPTDC high precision mode    
-    constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES;
-    
+  constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES;
+
 --Include SPI on AddOn connector    
-    constant INCLUDE_SPI            : integer := c_YES;
+  constant INCLUDE_SPI : integer := c_YES;
 
 --Add logic to generate configurable trigger signal from input signals.
-    constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;    
+  constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+
 --Do histos of all inputs
-    constant INCLUDE_STATISTICS     : integer := c_YES;    
+  constant INCLUDE_STATISTICS : integer := c_YES;
+
 --number of real inputs to the FPGA    
-    constant PHYSICAL_INPUTS        : integer := 16;
+  constant PHYSICAL_INPUTS : integer := 16;
+
+--Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
+  constant USE_64_FIFO : integer := c_NO;
 
-    
-    
 --Run wih 125 MHz instead of 100 MHz     
-    constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!  
-    
+  constant USE_125_MHZ : integer := c_NO;  --not implemented yet!  
+
 --Use sync mode, RX clock for all parts of the FPGA
-    constant USE_RXCLOCK            : integer := c_NO;  --not implemented yet!
-    
-   
+  constant USE_RXCLOCK : integer := c_NO;  --not implemented yet!
+
 --Address settings   
-    constant INIT_ADDRESS           : std_logic_vector := x"F305";
-    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4e";
-   
+  constant INIT_ADDRESS           : std_logic_vector := x"F305";
+  constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4e";
+
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
@@ -49,31 +51,31 @@ package config is
 ------------------------------------------------------------------------------
 --Select settings by configuration 
 ------------------------------------------------------------------------------
-    type intlist_t is array(0 to 7) of integer;
-    type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
-    constant HW_INFO_BASE            : unsigned(31 downto 0) := x"91000000";
-    constant HW_INFO_SPI             : hw_info_t := (x"00000000",x"00000400", others => x"00000000");
-    constant HW_INFO_DOUBLE_EDGE     : hw_info_t := (x"00000000",x"00000800", others => x"00000000");
-    constant HW_INFO_NUM_CHANS       : hw_info_t := (x"00000000",x"00000010",x"00000020",x"00000030",
-                                                     x"00000040",x"00000050",x"00000060",x"00000070", others => x"00000000");
-    
-    constant CLOCK_FREQUENCY_ARR  : intlist_t := (100,125, others => 0);
-    constant MEDIA_FREQUENCY_ARR  : intlist_t := (200,125, others => 0);
-                          
+  type intlist_t is array(0 to 7) of integer;
+  type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+  constant HW_INFO_BASE        : unsigned(31 downto 0) := x"91000000";
+  constant HW_INFO_SPI         : hw_info_t             := (x"00000000", x"00000400", others => x"00000000");
+  constant HW_INFO_DOUBLE_EDGE : hw_info_t             := (x"00000000", x"00000800", others => x"00000000");
+  constant HW_INFO_NUM_CHANS   : hw_info_t             := (x"00000000", x"00000010", x"00000020", x"00000030",
+                                                           x"00000040", x"00000050", x"00000060", x"00000070",
+                                                           others => x"00000000");
+  constant CLOCK_FREQUENCY_ARR : intlist_t := (100, 125, others => 0);
+  constant MEDIA_FREQUENCY_ARR : intlist_t := (200, 125, others => 0);
+
   --declare constants, filled in body                          
-    constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
-    constant CLOCK_FREQUENCY      : integer;
-    constant MEDIA_FREQUENCY      : integer;
+  constant HARDWARE_INFO   : std_logic_vector(31 downto 0);
+  constant CLOCK_FREQUENCY : integer;
+  constant MEDIA_FREQUENCY : integer;
 
 end;
 
 package body config is
 --compute correct configuration mode
   
-  constant HARDWARE_INFO        : std_logic_vector(31 downto 0) := std_logic_vector(
-                                      HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) +
-                                      HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2));
-  constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
-  constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+  constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+    HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) +
+    HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2));
+  constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
+  constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
   
-end package body;
\ No newline at end of file
+end package body;

diff --git a/wasa/config.vhd b/wasa/config.vhd
index f6783958b57d2fbc4ae418bbcc29339a9c0ce778..a4ecd21bafbe1be95d39db681871644199e577c2 100644 (file)
--- a/wasa/config.vhd
+++ b/wasa/config.vhd
@@ -30,6 +30,8 @@ package config is
 --number of real inputs to the FPGA
   constant PHYSICAL_INPUTS : integer := 16;
 
+--Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
+  constant USE_64_FIFO : integer := c_NO;
 
 --Run wih 125 MHz instead of 100 MHz
   constant USE_125_MHZ : integer := c_NO;  --not implemented yet!