added information about Padiwa Flash

diff --git a/.gitignore b/.gitignore
index 8bf3846591c4a801b91e7c78c9e7195cf1e190fa..e09ce2691abbfb63b3f7ec04c6e7e448bf9b9c5f 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -8,4 +8,5 @@
 *.blg
 *.prv_auto
 *.fdb_latexmk
-/trb3/main.pdf
\ No newline at end of file
+/trb3/main.pdf
+.kateproject.d

diff --git a/.kateproject b/.kateproject
new file mode 100644 (file)
index 0000000..5795034
--- /dev/null
+++ b/.kateproject
@@ -0,0 +1,4 @@
+{
+  "name": "DaqDocu"
+, "files": [ { "git": 1 } ]
+}

diff --git a/trb3/MvdAddOn.tex b/trb3/MvdAddOn.tex
index 86d561cacada18037739e22b6aca1ab1b37f5b6a..ab4c829339304df93c47221429c835c8c7f250e8 100644 (file)
--- a/trb3/MvdAddOn.tex
+++ b/trb3/MvdAddOn.tex
@@ -1,5 +1,5 @@
 
-\begin{itemize}
+\begin{itemize*}
  \item Schematics %\url{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/MvdAddon1_alles.pdf}
  \item Pin-out file for the FPGA %\url{:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_mvd.lpf}
-\end{itemize}
+\end{itemize*}

diff --git a/trb3/SfpAddOn.tex b/trb3/SfpAddOn.tex
index 1e76760ca25155487190da5af9b355d5fe256553..7fd1a4b2849754c77862172dafddcda5907a3f70 100644 (file)
--- a/trb3/SfpAddOn.tex
+++ b/trb3/SfpAddOn.tex
@@ -1,6 +1,6 @@
 
 
-\begin{itemize}
+\begin{itemize*}
  \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/SFP-Addon1_alles.pdf}{SFP-Addon1\_alles.pdf}
  \item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_sfp.lpf}{cvsroot/trb3/base/trb3\_periph\_sfp.lpf}
-\end{itemize}
+\end{itemize*}

diff --git a/trb3/TdcAddOn.tex b/trb3/TdcAddOn.tex
index dff82af90b6e9d5bfe2ff4ed540987ddccfe04bd..d72fdc3ccb4daa3f8ee8e8b73c93534732cc2a76 100644 (file)
--- a/trb3/TdcAddOn.tex
+++ b/trb3/TdcAddOn.tex
@@ -1,6 +1,6 @@
 
-\begin{itemize}
+\begin{itemize*}
  \item Schematics \href{http://hades-wiki.gsi.de/pub/DaqSlowControl/TDCReadoutBoardV3/ADDON1ADA1_alles.pdf}{ADDON1ADA1\_alles.pdf}
  \item Pin-out file for the FPGA \href{cvs://:ext:hadaq@lxi001.gsi.de:/misc/hadesprojects/daq/cvsroot/trb3/base/trb3_periph_ada.lpf}{cvsroot/trb3/base/trb3\_periph\_ada.lpf}
-\end{itemize}
+\end{itemize*}
 

diff --git a/trb3/WasaFrontend.tex b/trb3/WasaFrontend.tex
index 3d5aedabf8f8dcee56a50396995fabefc58bc0ad..c6abf74ab716fe283fb4232c93ad3184379fbffc 100644 (file)
--- a/trb3/WasaFrontend.tex
+++ b/trb3/WasaFrontend.tex
@@ -39,17 +39,32 @@ Note that up to 16 commands can be sent to a board with one trbnet access: Load
 0x10 & UId / Temperature & read unique id. 64 Bit Id is divided in 4 16 Bit words, in registers 0 - 3. Temperature is available in register 4. (r/o)\\
 0x20 & I/O & Register 0 contains one bit per input. 0: enable (default), 1: disable.\newline Register 1 shows the current status of the pin.\newline Register 2 Write: Override LED status. Bit 0-3: LED in alphabetical order. Bit 4: enable override. Read: LED status.\newline Register 3: 4 Bit to select one input to be routed to test output (SPARE\_LINE 5\&6) \\
 0x40 & Memory & Read/Write to/from RAM. 16 registers with 8 Bit each.\\
-0x50 & Flash & Execute Flash command. Bit 14-12: Command (0:read, 2:write, 4:enable flash, 5:disable flash, 7:erase, Bit 11-0: Flash page\\
+0x50 & Flash & Execute Flash command.\\
 0x51 & Flash & Load RAM content to PWM settings. Channel Bit 0 selects upper or lower half of PWM channels. No data payload\\
-0x52 & Flash $\dagger$& Load RAM content from Flash. No data payload\\
  \end{tabularx} 
 \caption{SPI component selection}
 \label{tab:spiselect}
 \end{table}
 
-% the table above makes some ugly formatting :/
-% the typical LaTeX problem: too little text, too many floats :)
-\clearpage
+\subsubsection{Flash ROM}
+The Flash of the Padiwa FPGA contains two parts, the configuration ROM and the user ROM. Both can be erased individually and are organized in pages with 16 Byte each. Both are mapped to the same page address space:
+
+\begin{itemize*}
+\item Pages 0 - 5758 (0x0000 - 0x167E) Configuration ROM
+\item Pages 7168 - 7936 (0x1C00 - 0x1EFF) User space
+\end{itemize*}
+
+A flash command consists of a three Bit operation (Bit 15-13 in SPI register 0x50) and a 13 Bit page address (Bit 12 - 0). The address must be supplied for every command to affect the correct part of the Flash ROM.
+\begin{description*}
+\item[0x0 read]Read a page from Flash and store it in internal RAM.
+\item[0x4 write] Write a page of the Flash from the internal RAM.
+\item[0x8 enable] Enable Flash ROM. Has to be issued before any read/write operation. No address required.
+\item[0xA disable] Disable Flash ROM. Should be done after finishing all operations. No address required.
+\item[0xE erase] Erase either user or configuration Flash, depending on page address.
+\end{description*}
+
+
+
 \subsubsection{Some Hints for Beginners}
 
 Just some quick notes from a first user perspectives.