my $lattice_path = '/d/sugar/lattice/diamond/1.1';
#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/';
+#my $synplify_path = '/d/sugar/lattice/synplify/fpga_e201009sp2/';
use FileHandle;
signal time_waiting : unsigned(31 downto 0);
signal force_reinit : std_logic;
+ signal doing_calib : std_logic;
begin
when WAIT_FOR_FINISHED_STORING =>
if storing_data_is_finished = '1' then
- current_state <= RELEASE_LVL1;
- lvl1_release_i <= '1';
+ if doing_calib = '0' then
+ current_state <= RELEASE_LVL1;
+ lvl1_release_i <= '1';
+ else
+ current_state <= TIMING_TRIGGER;
+ timer_clear <= '1';
+ start_trigger_i <= '1';
+ end if;
end if;
when RELEASE_LVL1 =>
end if;
end process;
+ proc_doing_calib : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if start_calib_i = '1' then
+ doing_calib <= '1';
+ elsif storing_data_is_finished = '1' then
+ doing_calib <= '0';
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
-- I/O