change trb3_tools for new SPI features

diff --git a/base/code/trb3_tools.vhd b/base/code/trb3_tools.vhd
index 1de5be592e0430dd7c4a304bcc80db96650acdfb..ef8cc38f31ca3ca9981ffdc32ff4f15d5b0e2ce9 100644 (file)
--- a/base/code/trb3_tools.vhd
+++ b/base/code/trb3_tools.vhd
@@ -65,7 +65,7 @@ architecture trb3_tools_arch of trb3_tools is
 signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX;
 signal bus_debug_tx_in,  bus_flash_tx_in,  busflash_tx, busspi_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX;
 
-signal spi_sdi, spi_sdo, spi_sck : std_logic;
+signal spi_sdi, spi_sdo, spi_sck : std_logic_vector(15 downto 0);
 signal spi_cs, spi_clr           : std_logic_vector(15 downto 0);
 signal uart_rx, uart_tx          : std_logic;
 
@@ -228,10 +228,10 @@ end generate;
         SPI_CLR_OUT            => spi_clr
         );
     SPI_CS_OUT   <= spi_cs;
-    SPI_CLK_OUT  <= (others => spi_sck);
-    SPI_MOSI_OUT <= (others => spi_sdo);
+    SPI_CLK_OUT  <= spi_sck;
+    SPI_MOSI_OUT <= spi_sdo;
     SPI_CLR_OUT  <= spi_clr;
-    spi_sdi      <= or_all(SPI_MISO_IN and not spi_cs);
+    spi_sdi      <= SPI_MISO_IN;
     busspi_tx.unknown <= '0';
   end generate;
   gen_noSPI_LOGIC : if INCLUDE_SPI = 0 generate
@@ -347,4 +347,4 @@ end generate;
 DEBUG_OUT <= debug_status;
 
       
-end architecture;
\ No newline at end of file
+end architecture;