signal num_pakets : unsigned(3 downto 0) := (others => '0');
signal use_crc : std_logic := '0';
+--signal next_use_crc : std_logic := '0';
signal load_use_crc : std_logic := '0';
+--signal last_load_use_crc : std_logic := '0';
signal disable_crc : std_logic := '0';
signal num_crc : unsigned(3 downto 0) := (others => '0');
last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100);
last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100);
+--last_load_use_crc <= load_use_crc when rising_edge(CLK_100);
+--use_crc <= next_use_crc when rising_edge(CLK_100);
process begin
wait until rising_edge(CLK_100);
-
- if pulse_good_100 = '1' then
- got_pulse_good <= '1';
- good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
- else
- if buf_rx_write_out = '1' and use_crc = '0' then
- --fake pointer increase
+
+ if ct_fifo_empty = '1' then
+ got_pulse_bad <= '0';
+ got_pulse_good <= '0';
+ if load_use_crc = '1' then
+ use_crc <= '1';
+ else
+ use_crc <= '0';
+ end if;
+ end if;
+
+ if use_crc = '0' then --check disabled, just dummy counter
+ if buf_rx_write_out = '1' then
good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+1);
end if;
- if ct_fifo_empty = '1' then
- got_pulse_good <= '0';
- if load_use_crc = '1' then
- use_crc <= '1';
- else
- use_crc <= '0';
- end if;
- end if;
+ elsif pulse_good_100 = '1' then
+ got_pulse_good <= '1';
+ good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
end if;
+
if pulse_bad_100 = '1' then
got_pulse_bad <= '1';
- got_pulse_good <= '0';
- elsif ct_fifo_empty = '1' then
- got_pulse_bad <= '0';
end if;
if RX_ALLOW_IN = '0' then
elsif buf_rx_write_out = '1' then
if rx_packet_num = "100" then
rx_packet_num <= "000";
- --if use_crc = '0' then
- --good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
- --end if;
else
rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1);
end if;
end if;
end process;
-last_good_pos_counter <= good_pos_counter when rising_edge(CLK_100) and resub_mode = '1';
+last_good_pos_counter <= good_pos_counter when rising_edge(CLK_100) ; -- and waiting_for_retr = '1';
+-- and resub_mode = '1';
last_send_link_reset_i <= send_link_reset_i when rising_edge(CLK_100);
----------------------------------------------------------------------
if (use_crc = '0') then
-- first time
load_use_crc <= '1';
- pulse_good <= '1';
+ --pulse_good <= '1';
+ disable_crc <= '0';
else
if ((crc_q = reg_rx_data_in and waiting_for_retr = '0') --- and num_pakets = 5)
and force_crc_error = '0') or disable_crc = '1' then -- CRC match
ram_read_addr <= (others => '0');
--ram_read_addr2 <= (others => '0');
elsif load_read_pointer_i = '1' then
+ ram_read_addr1 <= ram_read_addr;
ram_read_addr <= unsigned(restart_position_i);
ram_read_addr2 <= unsigned(restart_position_i);
- ram_read_addr1 <= ram_read_addr;
elsif ram_read = '1' then
ram_read_addr <= ram_read_addr + to_unsigned(1,1);
- end if;
+ end if;
end if;
end process;