add pause function to injection generator

diff --git a/mupix/Mupix8/sources/MupixBoardDAC.vhd b/mupix/Mupix8/sources/MupixBoardDAC.vhd
index 3f78be956c49ef68a48c19228f01d76c5547cd3e..ba48fffcb5bc2ce5608c416d8477114b86e3da58 100644 (file)
--- a/mupix/Mupix8/sources/MupixBoardDAC.vhd
+++ b/mupix/Mupix8/sources/MupixBoardDAC.vhd
@@ -76,6 +76,7 @@ architecture RTL of MupixBoardDAC is
                rst                  : in  std_logic;
        clk                  : in  std_logic;
        pulse_length         : in  std_logic_vector(15 downto 0); 
+       pulse_pause          : in  std_logic_vector(15 downto 0);
        pulse_start          : in  std_logic;
        pulse_o              : out std_logic 
        );
@@ -102,7 +103,7 @@ architecture RTL of MupixBoardDAC is
        signal spi_clk_adc : std_logic;
        
        signal pulse_start_i : std_logic := '0';
-       signal pulse_length_i  : std_logic_vector(15 downto 0) := (others => '0');
+       signal pulse_length_i, pulse_pause_i  : std_logic_vector(15 downto 0) := (others => '0');
        
 begin
        
@@ -168,6 +169,7 @@ begin
                        rst                  => reset,
                clk                  => clk,
                pulse_length         => pulse_length_i,
+               pulse_pause          => pulse_pause_i,
                pulse_start          => pulse_start_i,
                pulse_o              => injection_pulse
                );      
@@ -182,7 +184,7 @@ begin
        --0x0096: start write threshold and injection dacs bit
        --0x0097: write config adc
        --0x0098: read adc data
-       --0x0099: injection length
+       --0x0099: injection length (31:16) and pause (15:0) 
        -----------------------------------------------------------------------------
        SLV_BUS_HANDLER : process(clk)
        begin                               -- process SLV_BUS_HANDLER
@@ -223,6 +225,7 @@ begin
                                                SLV_DATA_OUT              <= spi_data_out_adc;
                                                SLV_ACK_OUT               <= '1';
                                        when x"0099" =>
+                                               SLV_DATA_OUT(31 downto 16) <= pulse_length_i;
                                                SLV_DATA_OUT(15 downto 0)  <= pulse_length_i;
                                                SLV_ACK_OUT                <= '1';
                                        when others =>
@@ -250,7 +253,8 @@ begin
                                                SLV_ACK_OUT           <= '1';
                                        when x"0099" =>
                                                pulse_start_i  <= '1';
-                                               pulse_length_i <= SLV_DATA_IN(15 downto 0);
+                                               pulse_length_i <= SLV_DATA_IN(31 downto 16);
+                                               pulse_pause_i  <= SLV_DATA_IN(15 downto 0);
                                                SLV_ACK_OUT    <= '1';
                                        when others =>
                                                SLV_UNKNOWN_ADDR_OUT <= '1';

diff --git a/mupix/Mupix8/sources/TestpulseGenerator.vhd b/mupix/Mupix8/sources/TestpulseGenerator.vhd
index 6c5bce7c1b5c727caa4379209540e3e5c6fd1a21..2a7c288d8fc69a054324f70c86b0e9e42df44c5d 100644 (file)
--- a/mupix/Mupix8/sources/TestpulseGenerator.vhd
+++ b/mupix/Mupix8/sources/TestpulseGenerator.vhd
@@ -12,6 +12,7 @@ entity injection_generator is
     rst                  : in  std_logic;--! reset input
     clk                  : in  std_logic;--! clock input
     pulse_length         : in  std_logic_vector(15 downto 0); --! length of injection pulse
+    pulse_pause          : in  std_logic_vector(15 downto 0); --! pause between pulses
     pulse_start          : in  std_logic;--! start generation of pulse
     pulse_o              : out std_logic --! output signal to mupix board
     );
@@ -20,41 +21,55 @@ end injection_generator;
 
 architecture rtl of injection_generator is
 
-       type injection_generator_type is (idle, gen);
+       type injection_generator_type is (idle, gen, pause);
        signal injection_generator_fsm : injection_generator_type := idle;  
-       signal counter : unsigned(15 downto 0) := (others => '0');
+       signal length_counter, pause_counter : unsigned(15 downto 0) := (others => '0');
        
 begin
 
        injection_gen : process(clk) is
-       begin
-               if rising_edge(clk) then
-                       if rst = '1' then
-                               counter <= (others => '0');
-                               injection_generator_fsm <= idle;
-                               pulse_o <= '0';
-                       else
-                               case injection_generator_fsm is  
-                                       when idle =>
-                                               pulse_o <= '0';
-                                               counter <= (others => '0');
-                                               if pulse_start = '1' then
-                                                       injection_generator_fsm <= gen;
-                                               else
-                                                       injection_generator_fsm <= idle;
-                                               end if;
-                                       when gen =>
-                                               pulse_o <= '1';
-                                               counter <= counter + 1;
-                                               if counter = unsigned(pulse_length) then
-                                                       injection_generator_fsm <= idle;
-                                               else
-                                                       injection_generator_fsm <= gen;
-                                               end if;
-                               end case; 
-                       end if;
-               end if;
-       end process injection_gen;
+       begin
+               if rising_edge(clk) then
+                       if rst = '1' then
+                               length_counter          <= (others => '0');
+                               pause_counter           <= (others => '0');
+                               injection_generator_fsm <= idle;
+                               pulse_o                 <= '0';
+                       else
+                               case injection_generator_fsm is
+                                       when idle =>
+                                               pulse_o        <= '0';
+                                               length_counter <= (others => '0');
+                                               if pulse_start = '1' then
+                                                       injection_generator_fsm <= gen;
+                                               else
+                                                       injection_generator_fsm <= idle;
+                                               end if;
+                                       when gen =>
+                                               pulse_o        <= '1';
+                                               length_counter <= length_counter + 1;
+                                               if length_counter = unsigned(pulse_length) then
+                                                       injection_generator_fsm <= pause;
+                                                       pause_counter           <= (others => '0');
+                                               else
+                                                       injection_generator_fsm <= gen;
+                                               end if;
+                                       when pause =>
+                                               pulse_o        <= '0';
+                                               if pulse_pause /= x"0000" then
+                                                       if std_logic_vector(pause_counter) = pulse_pause then
+                                                               injection_generator_fsm <= gen;
+                                                               length_counter <= (others => '0');
+                                                       else
+                                                               pause_counter <= pause_counter + 1;
+                                                       end if;
+                                               else
+                                                       injection_generator_fsm <= idle;
+                                               end if;
+                               end case;
+                       end if;
+               end if;
+       end process injection_gen;
        
   
 end rtl;