--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+USE IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.version.all;\r
+\r
+\r
+\r
+entity trb3_central is\r
+ generic (\r
+ USE_ETHERNET : integer range 0 to 1 := 1\r
+ );\r
+ port(\r
+ --Clocks\r
+ CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45\r
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 2/9, 200 MHz <-- MAIN CLOCK\r
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 1/9, 125 MHz <-- for GbE\r
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz \r
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz \r
+\r
+ --Trigger\r
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out\r
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out\r
+ TRIGGER_EXT : in std_logic_vector(4 downto 2); --additional trigger from RJ45\r
+ TRIGGER_OUT : out std_logic; --trigger to second input of fan-out\r
+ \r
+ --Serdes\r
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems\r
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible\r
+ \r
+ --SFP\r
+ SFP_RX_P : in std_logic_vector(16 downto 1); \r
+ SFP_RX_N : in std_logic_vector(16 downto 1); \r
+ SFP_TX_P : out std_logic_vector(16 downto 1); \r
+ SFP_TX_N : out std_logic_vector(16 downto 1); \r
+ SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken\r
+ SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP\r
+ SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal\r
+ SFP_MOD0 : in std_logic_vector(8 downto 1); --SFP present\r
+ SFP_MOD1 : in std_logic_vector(8 downto 1); --I2C interface\r
+ SFP_MOD2 : in std_logic_vector(8 downto 1); --I2C interface\r
+ SFP_TXDIS : out std_logic_vector(8 downto 1); --disable TX\r
+ \r
+ --Clock and Trigger Control\r
+ TRIGGER_SELECT : out std_logic; --trigger select for fan-out. 0: external, 1: signal from FPGA5\r
+ CLOCK_SELECT : out std_logic; --clock select for fan-out. 0: 200MHz, 1: external from RJ45\r
+ CLK_MNGR1_USER : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1\r
+ CLK_MNGR2_USER : inout std_logic_vector(3 downto 0); --I/O lines to clock manager 1\r
+ \r
+ --Inter-FPGA Communication\r
+ FPGA1_COMM : inout std_logic_vector(11 downto 0);\r
+ FPGA2_COMM : inout std_logic_vector(11 downto 0);\r
+ FPGA3_COMM : inout std_logic_vector(11 downto 0);\r
+ FPGA4_COMM : inout std_logic_vector(11 downto 0); \r
+ -- on all FPGAn_COMM: --Bit 0/1 output, serial link TX active\r
+ --Bit 2/3 input, serial link RX active\r
+ --others yet undefined\r
+ FPGA1_TTL : inout std_logic_vector(3 downto 0);\r
+ FPGA2_TTL : inout std_logic_vector(3 downto 0);\r
+ FPGA3_TTL : inout std_logic_vector(3 downto 0);\r
+ FPGA4_TTL : inout std_logic_vector(3 downto 0);\r
+ --only for not timing-sensitive signals\r
+\r
+ --Communication to small addons\r
+ FPGA1_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP3/4\r
+ FPGA2_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 2-3: LED for SFP7/8\r
+ FPGA3_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP5/6 \r
+ FPGA4_CONNECTOR : inout std_logic_vector(7 downto 0); --Bit 0-1: LED for SFP1/2\r
+ --Bit 0-3 connected to LED by default, two on each side\r
+ \r
+ --Big AddOn connector\r
+ ADDON_RESET : out std_logic; --reset signal to AddOn\r
+ ADDON_TO_TRB_CLK : in std_logic; --Clock from AddOn, connected to PCLK input\r
+ TRB_TO_ADDON_CLK : out std_logic; --Clock sent to AddOn\r
+ ADO_LV : inout std_logic_vector(61 downto 0);\r
+ ADO_TTL : inout std_logic_vector(46 downto 0);\r
+ FS_PE : inout std_logic_vector(17 downto 0);\r
+ \r
+ --Flash ROM & Reboot\r
+ FLASH_CLK : out std_logic;\r
+ FLASH_CS : out std_logic;\r
+ FLASH_CIN : out std_logic;\r
+ FLASH_DOUT : in std_logic;\r
+ PROGRAMN : out std_logic := '1'; --reboot FPGA\r
+ \r
+ --Misc\r
+ ENPIRION_CLOCK : out std_logic; --Clock for power supply, not necessary, floating\r
+ TEMPSENS : inout std_logic; --Temperature Sensor\r
+ LED_CLOCK_GREEN : out std_logic;\r
+ LED_CLOCK_RED : out std_logic;\r
+ LED_GREEN : out std_logic;\r
+ LED_ORANGE : out std_logic; \r
+ LED_RED : out std_logic;\r
+ LED_TRIGGER_GREEN : out std_logic;\r
+ LED_TRIGGER_RED : out std_logic; \r
+ LED_YELLOW : out std_logic;\r
+\r
+ --Test Connectors\r
+ TEST_LINE : out std_logic_vector(31 downto 0)\r
+ );\r
+ \r
+ attribute syn_useioff : boolean;\r
+ --no IO-FF for LEDs relaxes timing constraints\r
+ attribute syn_useioff of LED_CLOCK_GREEN : signal is false;\r
+ attribute syn_useioff of LED_CLOCK_RED : signal is false;\r
+ attribute syn_useioff of LED_GREEN : signal is false;\r
+ attribute syn_useioff of LED_ORANGE : signal is false;\r
+ attribute syn_useioff of LED_RED : signal is false;\r
+ attribute syn_useioff of LED_TRIGGER_GREEN : signal is false;\r
+ attribute syn_useioff of LED_TRIGGER_RED : signal is false;\r
+ attribute syn_useioff of LED_YELLOW : signal is false;\r
+ attribute syn_useioff of FPGA1_TTL : signal is false;\r
+ attribute syn_useioff of FPGA2_TTL : signal is false;\r
+ attribute syn_useioff of FPGA3_TTL : signal is false;\r
+ attribute syn_useioff of FPGA4_TTL : signal is false;\r
+ attribute syn_useioff of SFP_TXDIS : signal is false;\r
+ \r
+ --important signals _with_ IO-FF\r
+ attribute syn_useioff of FLASH_CLK : signal is true;\r
+ attribute syn_useioff of FLASH_CS : signal is true;\r
+ attribute syn_useioff of FLASH_CIN : signal is true;\r
+ attribute syn_useioff of FLASH_DOUT : signal is true;\r
+ attribute syn_useioff of FPGA1_COMM : signal is true;\r
+ attribute syn_useioff of FPGA2_COMM : signal is true;\r
+ attribute syn_useioff of FPGA3_COMM : signal is true;\r
+ attribute syn_useioff of FPGA4_COMM : signal is true;\r
+\r
+\r
+end entity;\r
+\r
+architecture trb3_central_arch of trb3_central is\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+ \r
+ component pll_in200_out100 is\r
+port (\r
+ CLK: in std_logic;\r
+ CLKOP: out std_logic;\r
+ CLKOK: out std_logic;\r
+ LOCK: out std_logic\r
+ );\r
+end component;\r
+\r
+\r
+component serdes is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes.txt");\r
+ port (\r
+------------------\r
+-- CH0 --\r
+ hdinp_ch0, hdinn_ch0 : in std_logic;\r
+ hdoutp_ch0, hdoutn_ch0 : out std_logic;\r
+ rxiclk_ch0 : in std_logic;\r
+ txiclk_ch0 : in std_logic;\r
+ rx_full_clk_ch0 : out std_logic;\r
+ rx_half_clk_ch0 : out std_logic;\r
+ tx_full_clk_ch0 : out std_logic;\r
+ tx_half_clk_ch0 : out std_logic;\r
+ fpga_rxrefclk_ch0 : in std_logic;\r
+ txdata_ch0 : in std_logic_vector (7 downto 0);\r
+ tx_k_ch0 : in std_logic;\r
+ xmit_ch0 : in std_logic;\r
+ tx_disp_correct_ch0 : in std_logic;\r
+ rxdata_ch0 : out std_logic_vector (7 downto 0);\r
+ rx_k_ch0 : out std_logic;\r
+ rx_disp_err_ch0 : out std_logic;\r
+ rx_cv_err_ch0 : out std_logic;\r
+ rx_serdes_rst_ch0_c : in std_logic;\r
+ sb_felb_ch0_c : in std_logic;\r
+ sb_felb_rst_ch0_c : in std_logic;\r
+ tx_pcs_rst_ch0_c : in std_logic;\r
+ tx_pwrup_ch0_c : in std_logic;\r
+ rx_pcs_rst_ch0_c : in std_logic;\r
+ rx_pwrup_ch0_c : in std_logic;\r
+ rx_los_low_ch0_s : out std_logic;\r
+ lsm_status_ch0_s : out std_logic;\r
+ rx_cdr_lol_ch0_s : out std_logic;\r
+-- CH1 --\r
+ hdinp_ch1, hdinn_ch1 : in std_logic;\r
+ hdoutp_ch1, hdoutn_ch1 : out std_logic;\r
+ rxiclk_ch1 : in std_logic;\r
+ txiclk_ch1 : in std_logic;\r
+ rx_full_clk_ch1 : out std_logic;\r
+ rx_half_clk_ch1 : out std_logic;\r
+ tx_full_clk_ch1 : out std_logic;\r
+ tx_half_clk_ch1 : out std_logic;\r
+ fpga_rxrefclk_ch1 : in std_logic;\r
+ txdata_ch1 : in std_logic_vector (7 downto 0);\r
+ tx_k_ch1 : in std_logic;\r
+ xmit_ch1 : in std_logic;\r
+ tx_disp_correct_ch1 : in std_logic;\r
+ rxdata_ch1 : out std_logic_vector (7 downto 0);\r
+ rx_k_ch1 : out std_logic;\r
+ rx_disp_err_ch1 : out std_logic;\r
+ rx_cv_err_ch1 : out std_logic;\r
+ rx_serdes_rst_ch1_c : in std_logic;\r
+ sb_felb_ch1_c : in std_logic;\r
+ sb_felb_rst_ch1_c : in std_logic;\r
+ tx_pcs_rst_ch1_c : in std_logic;\r
+ tx_pwrup_ch1_c : in std_logic;\r
+ rx_pcs_rst_ch1_c : in std_logic;\r
+ rx_pwrup_ch1_c : in std_logic;\r
+ rx_los_low_ch1_s : out std_logic;\r
+ lsm_status_ch1_s : out std_logic;\r
+ rx_cdr_lol_ch1_s : out std_logic;\r
+-- CH2 --\r
+-- CH3 --\r
+---- Miscillaneous ports\r
+ fpga_txrefclk : in std_logic;\r
+ tx_serdes_rst_c : in std_logic;\r
+ tx_pll_lol_qd_s : out std_logic;\r
+ tx_sync_qd_c : in std_logic;\r
+ rst_qd_c : in std_logic;\r
+ serdes_rst_qd_c : in std_logic);\r
+\r
+end component;\r
+\r
+component sgmii33 port (\r
+ rst_n : in std_logic;\r
+ signal_detect : in std_logic;\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ --force_isolate : in std_logic;\r
+ --force_loopback : in std_logic;\r
+ --force_unidir : in std_logic;\r
+ operational_rate : in std_logic_vector(1 downto 0);\r
+ debug_link_timer_short : in std_logic;\r
+ rx_compensation_err : out std_logic;\r
+ --ctc_drop_flag : out std_logic;\r
+ --ctc_add_flag : out std_logic;\r
+ --an_link_ok : out std_logic;\r
+ tx_clk_125 : in std_logic; \r
+ tx_clock_enable_source : out std_logic;\r
+ tx_clock_enable_sink : in std_logic; \r
+ tx_d : in std_logic_vector(7 downto 0); \r
+ tx_en : in std_logic; \r
+ tx_er : in std_logic; \r
+ rx_clk_125 : in std_logic; \r
+ rx_clock_enable_source : out std_logic;\r
+ rx_clock_enable_sink : in std_logic; \r
+ rx_d : out std_logic_vector(7 downto 0); \r
+ rx_dv : out std_logic; \r
+ rx_er : out std_logic; \r
+ col : out std_logic; \r
+ crs : out std_logic; \r
+ tx_data : out std_logic_vector(7 downto 0); \r
+ tx_kcntl : out std_logic; \r
+ tx_disparity_cntl : out std_logic; \r
+ --xmit_autoneg : out std_logic; \r
+ serdes_recovered_clk : in std_logic; \r
+ rx_data : in std_logic_vector(7 downto 0); \r
+ rx_even : in std_logic; \r
+ rx_kcntl : in std_logic; \r
+ rx_disp_err : in std_logic; \r
+ rx_cv_err : in std_logic; \r
+ rx_err_decode_mode : in std_logic; \r
+ mr_an_complete : out std_logic; \r
+ mr_page_rx : out std_logic; \r
+ mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
+ mr_main_reset : in std_logic; \r
+ mr_an_enable : in std_logic; \r
+ mr_restart_an : in std_logic; \r
+ mr_adv_ability : in std_logic_vector(15 downto 0)\r
+ );\r
+end component;\r
+\r
+component pll is\r
+ port (\r
+ CLK: in std_logic; \r
+ CLKOP: out std_logic; \r
+ LOCK: out std_logic);\r
+end component;\r
+\r
+\r
+component reset_controller_pcs port (\r
+ rst_n : in std_logic;\r
+ clk : in std_logic;\r
+ tx_plol : in std_logic; \r
+ rx_cdr_lol : in std_logic; \r
+ quad_rst_out : out std_logic; \r
+ tx_pcs_rst_out : out std_logic; \r
+ rx_pcs_rst_out : out std_logic\r
+ );\r
+end component;\r
+component reset_controller_cdr port (\r
+ rst_n : in std_logic;\r
+ clk : in std_logic;\r
+ cdr_lol : in std_logic; \r
+ cdr_rst_out : out std_logic\r
+ );\r
+end component;\r
+\r
+component rate_resolution port (\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ an_enable : in std_logic; \r
+ advertised_rate : in std_logic_vector(1 downto 0);\r
+ link_partner_rate : in std_logic_vector(1 downto 0);\r
+ non_an_rate : in std_logic_vector(1 downto 0);\r
+ operational_rate : out std_logic_vector(1 downto 0) \r
+ );\r
+end component;\r
+\r
+component register_interface_hb port (\r
+ rst_n : in std_logic;\r
+ hclk : in std_logic;\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ hcs_n : in std_logic;\r
+ hwrite_n : in std_logic;\r
+ haddr : in std_logic_vector(3 downto 0);\r
+ hdatain : in std_logic_vector(7 downto 0);\r
+ hdataout : out std_logic_vector(7 downto 0); \r
+ hready_n : out std_logic;\r
+ mr_an_complete : in std_logic; \r
+ mr_page_rx : in std_logic; \r
+ mr_lp_adv_ability : in std_logic_vector(15 downto 0); \r
+ mr_main_reset : out std_logic; \r
+ mr_an_enable : out std_logic; \r
+ mr_restart_an : out std_logic; \r
+ mr_adv_ability : out std_logic_vector(15 downto 0) \r
+ );\r
+end component;\r
+\r
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL\r
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.\r
+ signal clear_i : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal GSR_N : std_logic;\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+ \r
+ --FPGA Test\r
+ signal time_counter : unsigned(31 downto 0);\r
+ \r
+ --Media Interface\r
+ signal med_stat_op : std_logic_vector (5*16-1 downto 0);\r
+ signal med_ctrl_op : std_logic_vector (5*16-1 downto 0);\r
+ signal med_stat_debug : std_logic_vector (5*64-1 downto 0);\r
+ signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0);\r
+ signal med_data_out : std_logic_vector (5*16-1 downto 0);\r
+ signal med_packet_num_out : std_logic_vector (5*3-1 downto 0);\r
+ signal med_dataready_out : std_logic_vector (5*1-1 downto 0);\r
+ signal med_read_out : std_logic_vector (5*1-1 downto 0);\r
+ signal med_data_in : std_logic_vector (5*16-1 downto 0);\r
+ signal med_packet_num_in : std_logic_vector (5*3-1 downto 0);\r
+ signal med_dataready_in : std_logic_vector (5*1-1 downto 0);\r
+ signal med_read_in : std_logic_vector (5*1-1 downto 0);\r
+ \r
+ --Hub\r
+ --signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0);\r
+ --signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0);\r
+ signal my_address : std_logic_vector (16-1 downto 0);\r
+ signal regio_addr_out : std_logic_vector (16-1 downto 0);\r
+ signal regio_read_enable_out : std_logic;\r
+ signal regio_write_enable_out : std_logic;\r
+ signal regio_data_out : std_logic_vector (32-1 downto 0);\r
+ signal regio_data_in : std_logic_vector (32-1 downto 0);\r
+ signal regio_dataready_in : std_logic;\r
+ signal regio_no_more_data_in : std_logic;\r
+ signal regio_write_ack_in : std_logic;\r
+ signal regio_unknown_addr_in : std_logic;\r
+ signal regio_timeout_out : std_logic;\r
+ \r
+ signal spictrl_read_en : std_logic;\r
+ signal spictrl_write_en : std_logic;\r
+ signal spictrl_data_in : std_logic_vector(31 downto 0);\r
+ signal spictrl_addr : std_logic;\r
+ signal spictrl_data_out : std_logic_vector(31 downto 0);\r
+ signal spictrl_ack : std_logic;\r
+ signal spictrl_busy : std_logic;\r
+ signal spimem_read_en : std_logic;\r
+ signal spimem_write_en : std_logic;\r
+ signal spimem_data_in : std_logic_vector(31 downto 0);\r
+ signal spimem_addr : std_logic_vector(5 downto 0);\r
+ signal spimem_data_out : std_logic_vector(31 downto 0);\r
+ signal spimem_ack : std_logic;\r
+\r
+ signal spi_bram_addr : std_logic_vector(7 downto 0);\r
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
+ signal spi_bram_we : std_logic;\r
+\r
+ signal cts_number : std_logic_vector(15 downto 0);\r
+ signal cts_code : std_logic_vector(7 downto 0);\r
+ signal cts_information : std_logic_vector(7 downto 0);\r
+ signal cts_start_readout : std_logic;\r
+ signal cts_readout_type : std_logic_vector(3 downto 0);\r
+ signal cts_data : std_logic_vector(31 downto 0);\r
+ signal cts_dataready : std_logic;\r
+ signal cts_readout_finished : std_logic;\r
+ signal cts_read : std_logic;\r
+ signal cts_length : std_logic_vector(15 downto 0);\r
+ signal cts_status_bits : std_logic_vector(31 downto 0);\r
+ signal fee_data : std_logic_vector(15 downto 0);\r
+ signal fee_dataready : std_logic;\r
+ signal fee_read : std_logic;\r
+ signal fee_status_bits : std_logic_vector(31 downto 0);\r
+ signal fee_busy : std_logic;\r
+\r
+signal stage_stat_regs : std_logic_vector (31 downto 0);\r
+signal stage_ctrl_regs : std_logic_vector (31 downto 0);\r
+\r
+signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0);\r
+signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0);\r
+signal mb_stat_reg_read : std_logic;\r
+signal mb_stat_reg_write : std_logic;\r
+signal mb_stat_reg_ack : std_logic;\r
+\r
+signal ip_cfg_mem_clk : std_logic;\r
+signal ip_cfg_mem_addr : std_logic_vector(7 downto 0);\r
+signal ip_cfg_mem_data : std_logic_vector(31 downto 0);\r
+\r
+signal rx_full_clk, tx_k, rx_k, signal_detected, los : std_logic;\r
+signal txd, rxd : std_logic_vector(7 downto 0);\r
+\r
+signal tx_clk_en, rx_clk_en, an_link_ok, an_complete, sd_tx_kcntl, sd_tx_disp_cntl, sd_rx_kcntl, sd_rx_cv, sd_rx_disp_er, restart_an, restart_an_lock : std_logic; \r
+signal pcs_tx_en, pcs_tx_er, pcs_rx_dv, pcs_rx_er : std_logic;\r
+signal sd_rxd, sd_txd, pcs_rxd, pcs_txd : std_logic_vector(7 downto 0);\r
+signal counter : std_logic_vector(31 downto 0);\r
+signal rst_n, tx_pll_lol, rx_pcs_rst, quad_rst, rx_cdr_lol, rx_serdes_rst, lane_rst, user_rst : std_logic;\r
+signal tx_pcs_rst : std_logic;\r
+signal clk_125_i, xmit, tx_full_clk : std_logic;\r
+signal pcs_col, pcs_crs, mac_rx_dv : std_logic;\r
+signal mac_rxd : std_logic_vector(7 downto 0);\r
+\r
+signal mr_an_enable, mr_restart_an, mr_main_reset, mr_page_rx : std_logic;\r
+signal mr_lp_adv_ability, mr_adv_ability : std_logic_vector(15 downto 0);\r
+signal operational_rate : std_logic_vector(1 downto 0);\r
+\r
+signal hdinp0a, hdinn0a, hdoutp0a, hdoutn0a, pcs_rx_dva, pcs_rx_era, tx_clk_ena, rx_clk_ena, rx_full_clka, tx_pll_lola, sd_tx_kcntla, sd_tx_disp_cntla, sd_rx_kcntla, sd_rx_disp_era, sd_rx_cva, losa, signal_detecteda, rx_cdr_lola, tx_pcs_rsta, rx_pcs_rsta, quad_rsta, rx_serdes_rsta : std_logic;\r
+signal sd_txda, sd_rxda, pcs_rxda : std_logic_vector(7 downto 0);\r
+\r
+signal powerup, compensation_err : std_logic;\r
+\r
+ attribute syn_keep of compensation_err : signal is true;\r
+ attribute syn_preserve of compensation_err : signal is true;\r
+\r
+ attribute syn_keep of signal_detected : signal is true;\r
+ attribute syn_preserve of signal_detected : signal is true;\r
+ \r
+ attribute syn_keep of los : signal is true;\r
+ attribute syn_preserve of los : signal is true;\r
+\r
+ attribute syn_keep of an_link_ok : signal is true;\r
+ attribute syn_preserve of an_link_ok : signal is true;\r
+\r
+ attribute syn_keep of an_complete : signal is true;\r
+ attribute syn_preserve of an_complete : signal is true;\r
+\r
+ attribute syn_keep of restart_an : signal is true;\r
+ attribute syn_preserve of restart_an : signal is true;\r
+\r
+signal hdinp0, hdinn0, hdoutp0, hdoutn0 : std_logic;\r
+\r
+attribute NOPAD : boolean;\r
+attribute NOPAD of hdinp0 : signal is true;\r
+attribute NOPAD of hdinn0 : signal is true;\r
+attribute NOPAD of hdoutp0 : signal is true;\r
+attribute NOPAD of hdoutn0 : signal is true;\r
+attribute NOPAD of hdinp0a : signal is true;\r
+attribute NOPAD of hdinn0a : signal is true;\r
+attribute NOPAD of hdoutp0a : signal is true;\r
+attribute NOPAD of hdoutn0a : signal is true;\r
+\r
+\r
+ \r
+begin\r
+\r
+\r
+hdinp0 <= SFP_RX_P(6);\r
+hdinn0 <= SFP_RX_N(6);\r
+SFP_TX_P(6) <= hdoutp0;\r
+SFP_TX_N(6) <= hdoutn0;\r
+\r
+hdinp0a <= SFP_RX_P(5);\r
+hdinn0a <= SFP_RX_N(5);\r
+SFP_TX_P(5) <= hdoutp0a;\r
+SFP_TX_N(5) <= hdoutn0a;\r
+\r
+\r
+\r
+SERDES_INST : serdes\r
+ port map(\r
+------------------\r
+-- CH0 --\r
+ hdinp_ch0 => hdinp0a,\r
+ hdinn_ch0 => hdinn0a,\r
+ hdoutp_ch0 => hdoutp0a,\r
+ hdoutn_ch0 => hdoutn0a,\r
+\r
+ rxiclk_ch0 => rx_full_clka,\r
+ txiclk_ch0 => clk_125_i,\r
+ rx_full_clk_ch0 => rx_full_clka,\r
+ rx_half_clk_ch0 => open,\r
+ tx_full_clk_ch0 => open,\r
+ tx_half_clk_ch0 => open,\r
+ fpga_rxrefclk_ch0 => clk_125_i,\r
+\r
+ txdata_ch0 => sd_txda,\r
+ tx_k_ch0 => sd_tx_kcntla,\r
+ xmit_ch0 => '0', --xmit,\r
+ tx_disp_correct_ch0 => sd_tx_disp_cntla,\r
+\r
+ rxdata_ch0 => sd_rxda,\r
+ rx_k_ch0 => sd_rx_kcntla,\r
+ rx_disp_err_ch0 => sd_rx_disp_era,\r
+ rx_cv_err_ch0 => sd_rx_cva,\r
+\r
+ sb_felb_ch0_c => '0',\r
+ sb_felb_rst_ch0_c => '0',\r
+\r
+ tx_pwrup_ch0_c => '1',\r
+ rx_pwrup_ch0_c => '1',\r
+\r
+ rx_los_low_ch0_s => losa,\r
+ lsm_status_ch0_s => signal_detecteda,\r
+ rx_cdr_lol_ch0_s => rx_cdr_lola,\r
+\r
+ tx_pcs_rst_ch0_c => tx_pcs_rsta,\r
+ rx_pcs_rst_ch0_c => rx_pcs_rsta,\r
+ --rst_qd_c => quad_rsta,\r
+ rx_serdes_rst_ch0_c => rx_serdes_rsta,\r
+-- CH1 --\r
+ hdinp_ch1 => hdinp0,\r
+ hdinn_ch1 => hdinn0,\r
+ hdoutp_ch1 => hdoutp0,\r
+ hdoutn_ch1 => hdoutn0,\r
+\r
+ rxiclk_ch1 => rx_full_clk,\r
+ txiclk_ch1 => clk_125_i,\r
+ rx_full_clk_ch1 => rx_full_clk,\r
+ rx_half_clk_ch1 => open,\r
+ tx_full_clk_ch1 => tx_full_clk,\r
+ tx_half_clk_ch1 => open,\r
+ fpga_rxrefclk_ch1 => clk_125_i,\r
+\r
+ txdata_ch1 => sd_txd,\r
+ tx_k_ch1 => sd_tx_kcntl,\r
+ xmit_ch1 => '0', --xmit,\r
+ tx_disp_correct_ch1 => sd_tx_disp_cntl,\r
+\r
+ rxdata_ch1 => sd_rxd,\r
+ rx_k_ch1 => sd_rx_kcntl,\r
+ rx_disp_err_ch1 => sd_rx_disp_er,\r
+ rx_cv_err_ch1 => sd_rx_cv,\r
+\r
+ sb_felb_ch1_c => '0',\r
+ sb_felb_rst_ch1_c => '0',\r
+\r
+ tx_pwrup_ch1_c => '1',\r
+ rx_pwrup_ch1_c => '1',\r
+\r
+ rx_los_low_ch1_s => los,\r
+ lsm_status_ch1_s => signal_detected,\r
+ rx_cdr_lol_ch1_s => rx_cdr_lol,\r
+\r
+ tx_pcs_rst_ch1_c => tx_pcs_rst,\r
+ rx_pcs_rst_ch1_c => rx_pcs_rst,\r
+ rx_serdes_rst_ch1_c => rx_serdes_rst,\r
+-- CH2 --\r
+-- CH3 --\r
+---- Miscillaneous ports\r
+ fpga_txrefclk => clk_125_i,\r
+ tx_serdes_rst_c => '0',\r
+ tx_pll_lol_qd_s => tx_pll_lol,\r
+ tx_sync_qd_c => '0',\r
+ rst_qd_c => quad_rst,\r
+ serdes_rst_qd_c => '0');\r
+\r
+SGMII2_INST : sgmii33 port map (\r
+ rst_n => GSR_N,\r
+ signal_detect => signal_detecteda,\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ operational_rate => operational_rate,\r
+ debug_link_timer_short => '0',\r
+ rx_compensation_err => open,\r
+ tx_clk_125 => clk_125_i,\r
+ tx_clock_enable_source => tx_clk_ena,\r
+ tx_clock_enable_sink => tx_clk_ena,\r
+ tx_d => pcs_rxda,\r
+ tx_en => pcs_rx_dva, \r
+ tx_er => pcs_rx_era, \r
+ rx_clk_125 => clk_125_i,\r
+ rx_clock_enable_source => rx_clk_ena,\r
+ rx_clock_enable_sink => rx_clk_ena, \r
+ rx_d => pcs_rxda,\r
+ rx_dv => pcs_rx_dva,\r
+ rx_er => pcs_rx_era, \r
+ col => open,\r
+ crs => open,\r
+ tx_data => sd_txda,\r
+ tx_kcntl => sd_tx_kcntla,\r
+ tx_disparity_cntl => sd_tx_disp_cntla,\r
+ serdes_recovered_clk => rx_full_clka,\r
+ rx_data => sd_rxda,\r
+ rx_even => '0',\r
+ rx_kcntl => sd_rx_kcntla,\r
+ rx_disp_err => sd_rx_disp_era,\r
+ rx_cv_err => sd_rx_cva,\r
+ rx_err_decode_mode => '0',\r
+ mr_an_complete => open,\r
+ mr_page_rx => open,\r
+ mr_lp_adv_ability => open,\r
+ mr_main_reset => mr_main_reset, --reset_i,\r
+ mr_an_enable => '1', --'1',\r
+ mr_restart_an => mr_restart_an,\r
+ mr_adv_ability => mr_adv_ability --x"0020"\r
+ );\r
+\r
+SGMII_INST : sgmii33 port map (\r
+ rst_n => GSR_N,\r
+ signal_detect => signal_detected,\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ operational_rate => operational_rate,\r
+ debug_link_timer_short => '0',\r
+ rx_compensation_err => compensation_err,\r
+ tx_clk_125 => clk_125_i,\r
+ tx_clock_enable_source => tx_clk_en,\r
+ tx_clock_enable_sink => tx_clk_en,\r
+ tx_d => pcs_rxd, --pcs_txd,\r
+ tx_en => pcs_rx_dv, --pcs_tx_en, \r
+ tx_er => pcs_rx_er, --pcs_tx_er, \r
+ rx_clk_125 => clk_125_i,\r
+ rx_clock_enable_source => rx_clk_en,\r
+ rx_clock_enable_sink => rx_clk_en, \r
+ rx_d => pcs_rxd,\r
+ rx_dv => pcs_rx_dv,\r
+ rx_er => pcs_rx_er, \r
+ col => pcs_col,\r
+ crs => pcs_crs,\r
+ tx_data => sd_txd,\r
+ tx_kcntl => sd_tx_kcntl,\r
+ tx_disparity_cntl => sd_tx_disp_cntl,\r
+ serdes_recovered_clk => rx_full_clk,\r
+ rx_data => sd_rxd,\r
+ rx_even => '0',\r
+ rx_kcntl => sd_rx_kcntl,\r
+ rx_disp_err => sd_rx_disp_er,\r
+ rx_cv_err => sd_rx_cv,\r
+ rx_err_decode_mode => '0',\r
+ mr_an_complete => an_complete,\r
+ mr_page_rx => mr_page_rx,\r
+ mr_lp_adv_ability => mr_lp_adv_ability,\r
+ mr_main_reset => mr_main_reset, --reset_i,\r
+ mr_an_enable => '1', --'1',\r
+ mr_restart_an => mr_restart_an,\r
+ mr_adv_ability => mr_adv_ability --x"0020"\r
+ );\r
+\r
+\r
+rst_n <= not reset_i;\r
+\r
+u0_reset_controller_pcs : reset_controller_pcs port map(\r
+ rst_n => rst_n,\r
+ clk => clk_125_i,\r
+ tx_plol => tx_pll_lol,\r
+ rx_cdr_lol => rx_cdr_lol,\r
+ quad_rst_out => quad_rst,\r
+ tx_pcs_rst_out => tx_pcs_rst,\r
+ rx_pcs_rst_out => rx_pcs_rst\r
+);\r
+\r
+u0_reset_controller_cdr : reset_controller_cdr port map(\r
+ rst_n => rst_n,\r
+ clk => clk_125_i,\r
+ cdr_lol => rx_cdr_lol,\r
+ cdr_rst_out => rx_serdes_rst\r
+);\r
+\r
+u0_rate_resolution : rate_resolution port map(\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ an_enable => '1',\r
+ advertised_rate => mr_adv_ability(11 downto 10),\r
+ link_partner_rate => mr_lp_adv_ability(11 downto 10),\r
+ non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled\r
+ \r
+ operational_rate => operational_rate\r
+);\r
+\r
+u0_ri : register_interface_hb port map(\r
+ -- Control Signals\r
+ rst_n => rst_n,\r
+ hclk => clk_125_i,\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ \r
+ -- Host Bus\r
+ hcs_n => '1',\r
+ hwrite_n => '1',\r
+ haddr => (others => '0'),\r
+ hdatain => (others => '0'),\r
+ \r
+ hdataout => open,\r
+ hready_n => open,\r
+\r
+ -- Register Outputs\r
+ mr_an_enable => mr_an_enable,\r
+ mr_restart_an => mr_restart_an,\r
+ mr_main_reset => mr_main_reset,\r
+ mr_adv_ability => mr_adv_ability,\r
+\r
+ -- Register Inputs\r
+ mr_an_complete => an_complete,\r
+ mr_page_rx => mr_page_rx,\r
+ mr_lp_adv_ability => mr_lp_adv_ability\r
+ );\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Reset Generation\r
+---------------------------------------------------------------------------\r
+\r
+GSR_N <= pll_lock;\r
+ \r
+THE_RESET_HANDLER : trb_net_reset_handler\r
+ generic map(\r
+ RESET_DELAY => x"FEEE"\r
+ )\r
+ port map(\r
+ CLEAR_IN => '0', -- reset input (high active, async)\r
+ CLEAR_N_IN => '1', -- reset input (low active, async)\r
+ CLK_IN => clk_125_i, --clk_200_i, -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN => clk_125_i, --clk_100_i, -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)\r
+ RESET_IN => '0', -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN => '0', --med_stat_op(4*16+13), -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!\r
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT => open\r
+ ); \r
+\r
+---------------------------------------------------------------------------\r
+-- Clock Handling\r
+---------------------------------------------------------------------------\r
+-- THE_MAIN_PLL : pll_in200_out100\r
+-- port map(\r
+-- CLK => CLK_GPLL_LEFT,\r
+-- CLKOP => clk_100_i,\r
+-- CLKOK => clk_200_i,\r
+-- LOCK => pll_lock\r
+-- );\r
+\r
+PLL_INST : pll\r
+ port map(\r
+ CLK => CLK_GPLL_RIGHT,\r
+ CLKOP => clk_125_i,\r
+ LOCK => pll_lock\r
+);\r
+\r
+\r
+SFP_TXDIS(4 downto 1) <= (others => '1');\r
+SFP_TXDIS(8 downto 7) <= (others => '1');\r
+SFP_TXDIS(6) <= '0';\r
+SFP_TXDIS(5) <= '0';\r
+\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- Clock and Trigger Configuration\r
+---------------------------------------------------------------------------\r
+ TRIGGER_SELECT <= '0'; --always external trigger source\r
+ CLOCK_SELECT <= '0'; --use on-board oscillator\r
+ CLK_MNGR1_USER <= (others => '0');\r
+ CLK_MNGR2_USER <= (others => '0'); \r
+\r
+ TRIGGER_OUT <= '0';\r
+\r
+---------------------------------------------------------------------------\r
+-- FPGA communication\r
+---------------------------------------------------------------------------\r
+-- FPGA1_COMM <= (others => 'Z');\r
+-- FPGA2_COMM <= (others => 'Z');\r
+-- FPGA3_COMM <= (others => 'Z');\r
+-- FPGA4_COMM <= (others => 'Z');\r
+\r
+ FPGA1_TTL <= (others => 'Z');\r
+ FPGA2_TTL <= (others => 'Z');\r
+ FPGA3_TTL <= (others => 'Z');\r
+ FPGA4_TTL <= (others => 'Z');\r
+\r
+ FPGA1_CONNECTOR <= (others => 'Z');\r
+ FPGA2_CONNECTOR <= (others => 'Z');\r
+ FPGA3_CONNECTOR <= (others => 'Z');\r
+ FPGA4_CONNECTOR <= (others => 'Z');\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Big AddOn Connector\r
+---------------------------------------------------------------------------\r
+ ADDON_RESET <= '1';\r
+ TRB_TO_ADDON_CLK <= '0';\r
+ ADO_LV <= (others => 'Z');\r
+ ADO_TTL <= (others => 'Z');\r
+ FS_PE <= (others => 'Z');\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+ --LED_CLOCK_GREEN <= '0';\r
+ --LED_CLOCK_RED <= '1';\r
+ --LED_GREEN <= not med_stat_op(9);\r
+ --LED_YELLOW <= not med_stat_op(10);\r
+ --LED_ORANGE <= not med_stat_op(11); \r
+ --LED_RED <= '1';\r
+ --LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);\r
+ --LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));\r
+\r
+ LED_GREEN <= compensation_err;\r
+ LED_ORANGE <= not an_complete;\r
+ LED_RED <= not restart_an;\r
+ LED_YELLOW <= signal_detected;\r
+---------------------------------------------------------------------------\r
+-- Test Connector\r
+--------------------------------------------------------------------------- \r
+\r
+ TEST_LINE(7 downto 0) <= med_data_in(7 downto 0);\r
+ TEST_LINE(8) <= med_dataready_in(0);\r
+ TEST_LINE(9) <= med_dataready_out(0);\r
+\r
+ \r
+ TEST_LINE(31 downto 10) <= (others => '0');\r
+\r
+end architecture;
\ No newline at end of file
jspc29 / trb3.git / commitdiff