SEND_RESET_WORDS_OUT : out std_logic;
MAKE_TRBNET_RESET_OUT : out std_logic;
-- Status signals
- LINK_BROKEN_OUT : out std_logic;
- CLEAR_STATUS_IN : in std_logic;
+ PACKET_TIMEOUT_OUT : out std_logic;
-- Debug signals
BSM_OUT : out std_logic_vector(3 downto 0);
DBG_OUT : out std_logic_vector(15 downto 0)
signal send_reset_q : std_logic_vector(3 downto 0);
signal reset_word_cnt : std_logic_vector(19 downto 0);
signal send_reset_words : std_logic_vector(3 downto 0);
-signal send_reset_words_q : std_logic_vector(3 downto 0);
signal make_trbnet_reset : std_logic_vector(3 downto 0);
-signal make_trbnet_reset_q : std_logic_vector(3 downto 0);
+
+signal packet_timeout : std_logic_vector(3 downto 0);
+signal rx_bsm : std_logic_vector(15 downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
port map(
core_txrefclk => CLK_25,
core_rxrefclk => CLK_25,
-
+
hdinp0 => RXP(0),
hdinn0 => RXN(0),
hdoutp0 => TXP(0),
ffs_rxfbfifo_error_ch0 => link_error(0)(6),
ffs_rlol_ch0 => link_error(0)(7),
oob_out_ch0 => open,
-
+
hdinp1 => rxp(1),
hdinn1 => rxn(1),
hdoutp1 => txp(1),
ffs_rxfbfifo_error_ch1 => link_error(1)(6),
ffs_rlol_ch1 => link_error(1)(7),
oob_out_ch1 => open,
-
+
hdinp2 => rxp(2),
hdinn2 => rxn(2),
hdoutp2 => txp(2),
ffs_rxfbfifo_error_ch2 => link_error(2)(6),
ffs_rlol_ch2 => link_error(2)(7),
oob_out_ch2 => open,
-
+
hdinp3 => rxp(3),
hdinn3 => rxn(3),
hdoutp3 => txp(3),
ffs_rxfbfifo_error_ch3 => link_error(3)(6),
ffs_rlol_ch3 => link_error(3)(7),
oob_out_ch3 => open,
-
+
ffc_macro_rst => '0',
ffc_quad_rst => quad_rst(0),
ffc_trst => '0',
port map(
core_txrefclk => CLK_25,
core_rxrefclk => CLK_25,
-
+
hdinp0 => RXP(0),
hdinn0 => RXN(0),
hdoutp0 => TXP(0),
ffs_rxfbfifo_error_ch0 => link_error(3)(6),
ffs_rlol_ch0 => link_error(3)(7),
oob_out_ch0 => open,
-
+
hdinp1 => rxp(1),
hdinn1 => rxn(1),
hdoutp1 => txp(1),
ffs_rxfbfifo_error_ch1 => link_error(2)(6),
ffs_rlol_ch1 => link_error(2)(7),
oob_out_ch1 => open,
-
+
hdinp2 => rxp(2),
hdinn2 => rxn(2),
hdoutp2 => txp(2),
ffs_rxfbfifo_error_ch2 => link_error(1)(6),
ffs_rlol_ch2 => link_error(1)(7),
oob_out_ch2 => open,
-
+
hdinp3 => rxp(3),
hdinn3 => rxn(3),
hdoutp3 => txp(3),
ffs_rxfbfifo_error_ch3 => link_error(0)(6),
ffs_rlol_ch3 => link_error(0)(7),
oob_out_ch3 => open,
-
+
ffc_macro_rst => '0',
ffc_quad_rst => quad_rst(0),
ffc_trst => '0',
fifo_reset(i) <= reset or quad_rst(0) or not rx_allow(i); --(sync with SYSCLK)
- --RX Control (25)
+ --RX Control
---------------------
- THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport
- generic map(
- USE_STATUS_FLAGS => c_NO
- )
- port map(
- read_clock_in => clk,
- write_clock_in => CLK_25,
- read_enable_in => rx_fifo_read_en(i),
- write_enable_in => rx_fifo_write_en(i),
- fifo_gsr_in => fifo_reset(i),
- write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8),
- read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8),
- full_out => rx_fifo_full(i),
- empty_out => rx_fifo_empty(i)
- );
-
- THE_WRITE_RX_FIFO_PROC: process( CLK_25 )
- begin
- if( rising_edge(CLK_25) ) then
- buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8);
- buf_rx_k(i) <= rx_k(i);
- if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then
- rx_fifo_write_en(i) <= '0';
- is_idle_word(i) <= '1';
- rx_starting(i) <= '1';
- else
- rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8);
- if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
- rx_fifo_write_en(i) <= '1';
- else
- rx_fifo_write_en(i) <= '0';
- end if;
- if ( buf_rx_k(i) = '1' ) then
- is_idle_word(i) <= '1';
- rx_starting(i) <= '0';
- elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then
- is_idle_word(i) <= '0';
- end if;
- end if;
- end if;
- end process THE_WRITE_RX_FIFO_PROC;
-
- THE_CNT_RESET_PROC : process( CLK_25 )
- begin
- if( rising_edge(CLK_25) ) then
- if( reset = '1' ) then
- send_reset_words(i) <= '0';
- make_trbnet_reset(i) <= '0';
- reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
- else
- send_reset_words(i) <= '0';
- make_trbnet_reset(i) <= '0';
- if( (buf_rx_data(i*8+7 downto i*8) = x"FE") and (buf_rx_k(i) = '1') ) then
- if( reset_word_cnt(i*5+4) = '0' ) then
- reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1;
- else
- send_reset_words(i) <= '1';
- end if;
- else
- reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
- make_trbnet_reset(i) <= reset_word_cnt(i*5+4);
- end if;
- end if;
- end if;
- end process;
+ THE_RX_CONTROL : trb_net16_rx_packets
+ port map(
+ -- Resets
+ RESET_IN => fifo_reset(i),
+ QUAD_RST_IN => quad_rst(0),
+ -- data stream from SerDes
+ CLK_IN => CLK_25,
+ RX_ALLOW_IN => rx_allow(i),
+ RX_DATA_IN => rx_data(8*i+7 downto 8*i),
+ RX_K_IN => rx_k(i),
+ -- media interface
+ SYSCLK_IN => CLK,
+ MED_DATA_OUT => MED_DATA_OUT(i*16+15 downto i*16),
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT(i),
+ MED_READ_IN => MED_READ_IN(i),
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(i*3+2 downto i*3),
+ -- reset handling
+ SEND_RESET_WORDS_OUT => send_reset_words(i),
+ MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i),
+ -- Status signals
+ PACKET_TIMEOUT_OUT => packet_timeout(i),
+ -- Debug signals
+ BSM_OUT => rx_bsm(i*4+3 downto i*4),
+ DBG_OUT => open
+ );
--TX Control (100)
---------------------
tx_fifo_data_in(i*16+15 downto i*16) <= med_data_in(i*16+15 downto i*16);
med_read_out(i) <= buf_med_read_out(i);
- --RX Control (100)
- ---------------------
- THE_RX_CTRL_PROC: process( clk )
- begin
- if( rising_edge(clk) ) then
- if( reset = '1' ) then
- buf_med_dataready_out(i) <= '0';
- byte_select(i) <= '0';
- last_rx_fifo_read_en(i) <= '0';
- else
- last_rx_fifo_read_en(i) <= rx_fifo_read_en(i);
- last_rx_fifo_empty(i) <= rx_fifo_empty(i);
- last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i);
- last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i);
- last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8);
- buf_med_dataready_out(i) <= '0';
- if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then
- if( byte_select(i) = '1' ) then
- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8)
- & buf_MED_DATA_OUT(i*16+7 downto i*16);
- buf_MED_DATAREADY_OUT(i) <= '1';
- else
- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8);
- end if;
- byte_select(i) <= not byte_select(i);
- end if;
- end if;
- end if;
- end process THE_RX_CTRL_PROC;
-
- rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i);
- MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16);
- MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i);
- MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
-
- --rx packet counter
- ---------------------
- THE_RX_PACKETS_PROC: process( clk )
- begin
- if( rising_edge(clk) ) then
- if( (reset = '1') or (rx_allow(i) = '0') ) then
- rx_counter(i*3+2 downto i*3) <= c_H0;
- else
- if( buf_med_dataready_out(i) = '1' ) then
- if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then
- rx_counter(i*3+2 downto i*3) <= (others => '0');
- else
- rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1;
- end if;
- end if;
- end if;
- end if;
- end process THE_RX_PACKETS_PROC;
--Link State machine
---------------------
D_OUT(2) => rx_allow_del(i)
);
- SYNC_RESET_DETECT_1 : signal_sync
- generic map( DEPTH => 2, WIDTH => 4 )
- port map(
- RESET => reset,
- D_IN => send_reset_words,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT => send_reset_words_q
- );
-
- SYNC_RESET_DETECT_2 : signal_sync
- generic map( DEPTH => 2, WIDTH => 4 )
- port map(
- RESET => reset,
- D_IN => make_trbnet_reset,
- CLK0 => CLK,
- CLK1 => CLK,
- D_OUT => make_trbnet_reset_q
- );
THE_SFP_STATUS_SYNC: signal_sync
generic map( DEPTH => 2, WIDTH => 1 )
STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0);
STAT_OP(i*16+10) <= rx_led(i);
STAT_OP(i*16+11) <= tx_led(i);
- STAT_OP(i*16+12) <= FSM_STAT_OP(i*16+12);
- STAT_OP(i*16+13) <= make_trbnet_reset_q(i);
+ STAT_OP(i*16+12) <= packet_timeout(i); --FSM_STAT_OP(i*16+12);
+ STAT_OP(i*16+13) <= make_trbnet_reset(i);
STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14);
- STAT_OP(i*16+15) <= send_reset_words_q(i);
+ STAT_OP(i*16+15) <= send_reset_words(i);
STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
STAT_DEBUG(i*64+39 downto i*64+32) <= buf_rx_data_reg(i*8+7 downto i*8);
SFP_LOS <= not sd_q;
FSM_CTRL_OP <= CTRL_OP;
-end architecture;
\ No newline at end of file
+end architecture;
+
+
+
+
+-- THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport
+-- generic map(
+-- USE_STATUS_FLAGS => c_NO
+-- )
+-- port map(
+-- read_clock_in => clk,
+-- write_clock_in => CLK_25,
+-- read_enable_in => rx_fifo_read_en(i),
+-- write_enable_in => rx_fifo_write_en(i),
+-- fifo_gsr_in => fifo_reset(i),
+-- write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8),
+-- read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8),
+-- full_out => rx_fifo_full(i),
+-- empty_out => rx_fifo_empty(i)
+-- );
+
+-- THE_WRITE_RX_FIFO_PROC: process( CLK_25 )
+-- begin
+-- if( rising_edge(CLK_25) ) then
+-- buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8);
+-- buf_rx_k(i) <= rx_k(i);
+-- if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then
+-- rx_fifo_write_en(i) <= '0';
+-- is_idle_word(i) <= '1';
+-- rx_starting(i) <= '1';
+-- else
+-- rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8);
+-- if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
+-- rx_fifo_write_en(i) <= '1';
+-- else
+-- rx_fifo_write_en(i) <= '0';
+-- end if;
+-- if ( buf_rx_k(i) = '1' ) then
+-- is_idle_word(i) <= '1';
+-- rx_starting(i) <= '0';
+-- elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then
+-- is_idle_word(i) <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end process THE_WRITE_RX_FIFO_PROC;
+
+-- THE_CNT_RESET_PROC : process( CLK_25 )
+-- begin
+-- if( rising_edge(CLK_25) ) then
+-- if( reset = '1' ) then
+-- send_reset_words(i) <= '0';
+-- make_trbnet_reset(i) <= '0';
+-- reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
+-- else
+-- send_reset_words(i) <= '0';
+-- make_trbnet_reset(i) <= '0';
+-- if( (buf_rx_data(i*8+7 downto i*8) = x"FE") and (buf_rx_k(i) = '1') ) then
+-- if( reset_word_cnt(i*5+4) = '0' ) then
+-- reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1;
+-- else
+-- send_reset_words(i) <= '1';
+-- end if;
+-- else
+-- reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
+-- make_trbnet_reset(i) <= reset_word_cnt(i*5+4);
+-- end if;
+-- end if;
+-- end if;
+-- end process;
+ --RX Control (100)
+ ---------------------
+-- THE_RX_CTRL_PROC: process( clk )
+-- begin
+-- if( rising_edge(clk) ) then
+-- if( reset = '1' ) then
+-- buf_med_dataready_out(i) <= '0';
+-- byte_select(i) <= '0';
+-- last_rx_fifo_read_en(i) <= '0';
+-- else
+-- last_rx_fifo_read_en(i) <= rx_fifo_read_en(i);
+-- last_rx_fifo_empty(i) <= rx_fifo_empty(i);
+-- last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i);
+-- last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i);
+-- last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8);
+-- buf_med_dataready_out(i) <= '0';
+-- if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then
+-- if( byte_select(i) = '1' ) then
+-- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8)
+-- & buf_MED_DATA_OUT(i*16+7 downto i*16);
+-- buf_MED_DATAREADY_OUT(i) <= '1';
+-- else
+-- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8);
+-- end if;
+-- byte_select(i) <= not byte_select(i);
+-- end if;
+-- end if;
+-- end if;
+-- end process THE_RX_CTRL_PROC;
+
+-- rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i);
+-- MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16);
+-- MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i);
+-- MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
+
+-- --rx packet counter
+-- ---------------------
+-- THE_RX_PACKETS_PROC: process( clk )
+-- begin
+-- if( rising_edge(clk) ) then
+-- if( (reset = '1') or (rx_allow(i) = '0') ) then
+-- rx_counter(i*3+2 downto i*3) <= c_H0;
+-- else
+-- if( buf_med_dataready_out(i) = '1' ) then
+-- if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then
+-- rx_counter(i*3+2 downto i*3) <= (others => '0');
+-- else
+-- rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1;
+-- end if;
+-- end if;
+-- end if;
+-- end if;
+-- end process THE_RX_PACKETS_PROC;
#####################################################################
# Test connector
#####################################################################
- LOCATE COMP "TEST_LINE_0" SITE "J26";
- LOCATE COMP "TEST_LINE_1" SITE "H26";
- LOCATE COMP "TEST_LINE_2" SITE "H27";
- LOCATE COMP "TEST_LINE_3" SITE "G26";
- LOCATE COMP "TEST_LINE_4" SITE "H23";
- LOCATE COMP "TEST_LINE_5" SITE "H24";
- LOCATE COMP "TEST_LINE_6" SITE "D28";
- LOCATE COMP "TEST_LINE_7" SITE "E28";
- LOCATE COMP "TEST_LINE_8" SITE "G24";
- LOCATE COMP "TEST_LINE_9" SITE "H25";
- LOCATE COMP "TEST_LINE_10" SITE "D27";
- LOCATE COMP "TEST_LINE_11" SITE "E27";
- LOCATE COMP "TEST_LINE_12" SITE "F26";
- LOCATE COMP "TEST_LINE_13" SITE "G25";
- LOCATE COMP "TEST_LINE_14" SITE "F24";
- LOCATE COMP "TEST_LINE_15" SITE "F25";
-
- DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
- IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
+# LOCATE COMP "TEST_LINE_0" SITE "J26";
+# LOCATE COMP "TEST_LINE_1" SITE "H26";
+# LOCATE COMP "TEST_LINE_2" SITE "H27";
+# LOCATE COMP "TEST_LINE_3" SITE "G26";
+# LOCATE COMP "TEST_LINE_4" SITE "H23";
+# LOCATE COMP "TEST_LINE_5" SITE "H24";
+# LOCATE COMP "TEST_LINE_6" SITE "D28";
+# LOCATE COMP "TEST_LINE_7" SITE "E28";
+# LOCATE COMP "TEST_LINE_8" SITE "G24";
+# LOCATE COMP "TEST_LINE_9" SITE "H25";
+# LOCATE COMP "TEST_LINE_10" SITE "D27";
+# LOCATE COMP "TEST_LINE_11" SITE "E27";
+# LOCATE COMP "TEST_LINE_12" SITE "F26";
+# LOCATE COMP "TEST_LINE_13" SITE "G25";
+# LOCATE COMP "TEST_LINE_14" SITE "F24";
+# LOCATE COMP "TEST_LINE_15" SITE "F25";
+#
+# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ;
#####################################################################
# Onewire
#####################################################################
# SFP
#####################################################################
-#Exchanged GBE and TrbNet for testing!
LOCATE COMP "GBE_LOS" SITE "AG8";
LOCATE COMP "GBE_MOD_0" SITE "AF8";
LOCATE COMP "GBE_MOD_1" SITE "AE15";
entity adc_ltc2308_readout is
generic(
CLOCK_FREQUENCY : integer := 100; --MHz
- PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"C10_A28" ; --5V/2 - 2.4-3.1
- PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A00_940" ; --5V/2 - 2.4-2.6
- PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"F00_D50" ; --3.5 - 3.4-3.8
- PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D80_C80" ; --3.3 - 3.2-3.4
- PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"770_510" ; --1.4 - 1.3-1.9
- PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"4E0_480" ; --1.2 - 1.15-1.25
- PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"C10_B50" ; --3.0 - 2.9-3.1
- PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"C10_B50" --3.0 - 2.9-3.1
+ PRESET_RANGES_CH0 : std_logic_vector(23 downto 0) := x"B6D_A28" ; --5V/2 - 2.4-3.1
+ PRESET_RANGES_CH1 : std_logic_vector(23 downto 0) := x"A00_960" ; --5V/2 - 2.4-2.6
+ PRESET_RANGES_CH2 : std_logic_vector(23 downto 0) := x"E70_DAC" ; --3.5 - 3.4-3.8
+ PRESET_RANGES_CH3 : std_logic_vector(23 downto 0) := x"D80_CB0" ; --3.3 - 3.2-3.4
+ PRESET_RANGES_CH4 : std_logic_vector(23 downto 0) := x"6A0_5B0" ; --1.4 - 1.3-1.9
+ PRESET_RANGES_CH5 : std_logic_vector(23 downto 0) := x"500_480" ; --1.2 - 1.15-1.25
+ PRESET_RANGES_CH6 : std_logic_vector(23 downto 0) := x"BF0_B55" ; --3.0 - 2.9-3.1
+ PRESET_RANGES_CH7 : std_logic_vector(23 downto 0) := x"C18_B50" --3.0 - 2.9-3.1
);
port(
CLK : in std_logic;
MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
-- LVL1 trigger APL
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received
LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received
REGIO_TIMEOUT_OUT : out std_logic;
REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
TIMER_TICKS_OUT : out std_logic_vector(1 downto 0);
-
+ HUB_LED_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
signal HUB_ADDRESS : std_logic_vector (15 downto 0);
signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0);
signal HUB_ERROR_BITS : std_logic_vector (16*4*32-1 downto 0);
- signal buf_HUB_ALL_ERROR_BITS : std_logic_vector ((16*2**(c_MUX_WIDTH-1))*32-1 downto 0);
+ signal buf_HUB_ALL_ERROR_BITS : std_logic_vector ((16*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0);
- signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0);
- signal network_reset_counter: std_logic_vector(11 downto 0);
+ signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0);
+ signal local_reset_med : std_logic_vector(MII_NUMBER-1 downto 0);
+ signal network_reset_counter : std_logic_vector(11 downto 0);
- signal stream_port_connected : std_logic;
+ signal stream_port_connected : std_logic;
signal stat_packets_addr : std_logic_vector(4 downto 0);
signal stat_packets_read : std_logic;
signal iobuf_stat_init_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
signal iobuf_stat_reply_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal led_counter : unsigned(9 downto 0);
+ signal hub_led_i : std_logic_vector(MII_NUMBER-1 downto 0);
+ signal hub_show_port : std_logic_vector(MII_NUMBER-1 downto 0);
+
+ signal lsm_addr : std_logic_vector(3 downto 0);
+ signal lsm_read : std_logic;
+ signal lsm_write : std_logic;
+ signal lsm_data : std_logic_vector(31 downto 0);
+ signal last_lsm_read : std_logic;
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_preserve of m_DATA_IN : signal is true;
proc_SYNC_CTRL_OP : process(CLK)
begin
if rising_edge(CLK) then
- MED_CTRL_OP(13+i*16 downto i*16) <= (others => '0');
+ MED_CTRL_OP(12+i*16 downto i*16) <= (others => '0');
+ MED_CTRL_OP(13+i*16) <= local_reset_med(i);
MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i);
if MII_IS_UPLINK(i) = 0 then
MED_CTRL_OP(15+i*16) <= combined_resync or local_network_reset(i);
gen_local_network_reset : process(CLK)
begin
if rising_edge(CLK) then
- if CTRL_REG_STROBE(8) = '1' then
- local_network_reset <= HUB_CTRL_LOCAL_NETWORK_RESET;
+ if CTRL_REG_STROBE(6) = '1' then
+ local_network_reset <= HUB_CTRL_LOCAL_NETWORK_RESET;
+ local_reset_med <= (others => '0');
network_reset_counter <= x"001";
end if;
- if network_reset_counter /= 0 then
- network_reset_counter <= network_reset_counter + 1;
- end if;
if network_reset_counter(10) = '1' then
network_reset_counter <= (others => '0');
- local_network_reset <= (others => '0');
+ local_network_reset <= (others => '0');
+ local_reset_med <= (others => '0');
+ elsif and_all(network_reset_counter(9 downto 0)) = '1' then
+ local_reset_med <= local_network_reset;
+ elsif network_reset_counter /= 0 then
+ network_reset_counter <= network_reset_counter + 1;
+ else
+ local_network_reset <= (others => '0');
+ local_reset_med <= (others => '0');
end if;
end if;
end process;
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", others => x"0000"),
- PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, others => 0)
+ PORT_NUMBER => 7,
+ PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, others => 0)
)
port map(
CLK => CLK,
BUS_NO_MORE_DATA_IN(5) => '0',
BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
+ BUS_ADDR_OUT(99 downto 96) => lsm_addr,
+ BUS_ADDR_OUT(111 downto 100) => open,
+ BUS_DATA_OUT(223 downto 192) => open,
+ BUS_READ_ENABLE_OUT(6) => lsm_read,
+ BUS_WRITE_ENABLE_OUT(6) => lsm_write,
+ BUS_TIMEOUT_OUT(6) => open,
+ BUS_DATA_IN(223 downto 192) => lsm_data,
+ BUS_DATAREADY_IN(5) => last_lsm_read,
+ BUS_WRITE_ACK_IN(5) => '0',
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => lsm_write,
+
STAT_DEBUG => open
);
begin
if rising_edge(CLK) then
reg_STROBES <= STAT_REG_STROBE;
+--Timeouts
if reg_STROBES(8) = '1' then
buf_HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0');
else
buf_HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or buf_HC_STAT_REGS(11*32+31 downto 11*32);
end if;
+--Error on slowcontrol
if reg_STROBES(36) = '1' then
HC_STAT_REGS(36*32+31 downto 36*32) <= (others => '0');
else
buf_HUB_ALL_ERROR_BITS(i*32+48*32+6);
end loop;
end if;
+
+--Track boards A5
+ if reg_STROBES(37) = '1' then
+ HC_STAT_REGS(37*32+31 downto 37*32) <= (others => '0');
+ else
+ for i in 0 to MII_NUMBER-1 loop
+ HC_STAT_REGS(37*32+i) <= HC_STAT_REGS(37*32+i)
+ or (buf_HUB_ALL_ERROR_BITS(i*32+48*32+0) and buf_HUB_ALL_ERROR_BITS(i*32+48*32+4));
+ end loop;
+ end if;
+
+--LSM packet timeout A6
+ if reg_STROBES(38) = '1' then
+ HC_STAT_REGS(38*32+31 downto 38*32) <= (others => '0');
+ else
+ for i in 0 to MII_NUMBER-1 loop
+ HC_STAT_REGS(38*32+i) <= HC_STAT_REGS(38*32+i) or (MED_STAT_OP(i*16+12));
+ end loop;
+ end if;
+
end if;
end process;
if rising_edge(CLK) then
HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0);
HC_STAT_REGS(36*32-1 downto 12*32) <= buf_HC_STAT_REGS(36*32-1 downto 12*32);
- HC_STAT_REGS(48*32-1 downto 37*32) <= buf_HC_STAT_REGS(48*32-1 downto 37*32);
+ HC_STAT_REGS(48*32-1 downto 39*32) <= buf_HC_STAT_REGS(48*32-1 downto 39*32);
HC_STAT_REGS(64*32-1 downto 48*32) <= buf_HC_STAT_REGS(64*32-1 downto 48*32);
end if;
end process;
end if;
end process;
+------------------------------------
+--LSM status
+------------------------------------
+ PROC_LSM_STAT : process(CLK, lsm_addr)
+ variable tmp : integer range 0 to 15;
+ begin
+ tmp := to_integer(unsigned(lsm_addr));
+ if rising_edge(CLK) then
+ last_lsm_read <= lsm_read;
+ lsm_data(7 downto 0) <= MED_STAT_OP(tmp*16+7 downto tmp*16+0);
+ lsm_data(31 downto 8) <= (others => '0');
+ end if;
+ end process;
+
------------------------------------
--STAT busy counters
------------------------------------
--Control Registers
------------------------------------
HUB_CTRL_media_interfaces_off <= HC_CTRL_REGS(2**2*32+31 downto 2**2*32);
- HUB_CTRL_LOCAL_NETWORK_RESET <= HC_CTRL_REGS(7*32+MII_NUMBER-1 downto 7*32);
+ HUB_CTRL_LOCAL_NETWORK_RESET <= HC_CTRL_REGS(6*32+MII_NUMBER-1 downto 6*32);
PROC_active_points : process (CLK)
begin
end if;
end process;
+ PROC_timeout_settings : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if CTRL_REG_STROBE(5) = '1' then
+ HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32);
+ end if;
+ end if;
+ end process;
+
+
gen_ack_waiting : for i in 0 to MII_NUMBER-1 generate
HC_STAT_ack_waiting(i) <= iobuf_stat_init_obuf_debug_i((i*4+0)*32+20);
HC_STAT_ack_waiting(32+i) <= iobuf_stat_init_obuf_debug_i((i*4+1)*32+20);
iobuf_ctrl_stat(48) <= iobuf_reset_sctrl_counter;
iobuf_ctrl_stat(63 downto 49) <= (others => '0');
+---------------------------------------------------------------------
+--LED signals
+---------------------------------------------------------------------
+ proc_led_count: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if timer_ms_tick = '1' then
+ led_counter <= led_counter + to_unsigned(1,1);
+ end if;
+ end if;
+ end process;
+
+ proc_led : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ for i in 0 to MII_NUMBER-1 loop
+ hub_led_i(i) <= '0';
+ if hub_show_port(i) = '1' then
+ if led_counter(6 downto 0) < to_unsigned(32,7) then
+ hub_led_i(i) <= '1';
+ end if;
+ elsif HC_STAT_REGS(8*32+i) = '1' or HC_STAT_REGS(9*32+i) = '1' or HC_STAT_REGS(10*32+i) = '1' or HC_STAT_REGS(11*32+i) = '1' then
+ if led_counter(8 downto 0) < to_unsigned(128,10) then
+ hub_led_i(i) <= '1';
+ end if;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ hub_show_port <= HC_CTRL_REGS(7*32+MII_NUMBER-1 downto 7*32);
+ HUB_LED_OUT <= hub_led_i;
+
---------------------------------------------------------------------
--Debugging Signals
---------------------------------------------------------------------
MY_ADDRESS_OUT <= HUB_ADDRESS;
STAT_REGS <= HC_STAT_REGS(16*32-1 downto 0);
STAT_CTRL_REGS <= HC_CTRL_REGS(255 downto 0);
- HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32);
HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
STAT_DEBUG <= buf_STAT_DEBUG;
HUB_STAT_GEN <= (others => '0');
COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs
COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+ HUB_LED_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1'))) = '1' then
connection_timed_out(i) <= '1';
- elsif timer_ms_tick = '1' then
+ elsif timer_ms_tick = '1' and got_trm(i) = '0' then
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
end if;
end if;
SEND_RESET_WORDS_OUT : out std_logic;\r
MAKE_TRBNET_RESET_OUT : out std_logic;\r
-- Status signals\r
- LINK_BROKEN_OUT : out std_logic;\r
+ PACKET_TIMEOUT_OUT : out std_logic;\r
-- Debug signals\r
BSM_OUT : out std_logic_vector(3 downto 0);\r
DBG_OUT : out std_logic_vector(15 downto 0)\r
-- RD4 : third word output reg, fourth word prefetch, wait state for handshake of third data word\r
-- RD5 : fourth word output reg, fifth word prefetch, wait state for handshake of forth data word\r
-- => decision: continous data stream or stalling as FIFO runs empty!\r
--- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission \r
+-- RDO : fifth word output reg, wait state for handshake of fifth data word, can also resume transmission\r
-- if new data is available in FIFO\r
--- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word, \r
+-- RDW : fifth word output reg, first word prefetch, wait state for handshake of fifth data word,\r
-- continue data stream or stall if for complete packet\r
\r
-- state declarations\r
case CURRENT_STATE is\r
when IDLE => if( fifo_rcnt > 0 ) then\r
-- we have at least one data word in FIFO, so we prefetch it\r
- NEXT_STATE <= RD1; \r
+ NEXT_STATE <= RD1;\r
fifo_rd_en_x <= '1';\r
ce_toc_x <= '1';\r
else\r
NEXT_STATE <= IDLE;\r
end if;\r
when RD1 => if ( fifo_rcnt > 1 ) then -- was 0\r
- -- second data word is available in FIFO, so we prefetch it and \r
+ -- second data word is available in FIFO, so we prefetch it and\r
-- forward the first word to the output register\r
NEXT_STATE <= RD2;\r
fifo_rd_en_x <= '1';\r
NEXT_STATE <= RD4;\r
end if;\r
when RD5 => med_dataready_x <= '1';\r
- -- DANGER. This is the key state for decisions here. \r
+ -- DANGER. This is the key state for decisions here.\r
-- There are many ways to do it the wrong way, depending on the FIFO fill level.\r
if ( (MED_READ_IN = '1') and (fifo_rcnt < 3) ) then -- was 2, changed due to RCNT latency\r
-- fourth word of packet has been transfered, and FIFO has not seen any new packet word.\r
update_x <= '1';\r
else\r
NEXT_STATE <= RDW;\r
- med_dataready_x <= '1'; \r
+ med_dataready_x <= '1';\r
end if;\r
when TOC => NEXT_STATE <= CLEAN;\r
fifo_rst_x <= '1';\r
when CLEAN => NEXT_STATE <= IDLE;\r
- \r
+\r
when others => NEXT_STATE <= IDLE;\r
end case;\r
end process STATE_TRANSFORM;\r
----------------------------------------------------------------------\r
SEND_RESET_WORDS_OUT <= send_reset_words;\r
MAKE_TRBNET_RESET_OUT <= make_trbnet_reset;\r
-LINK_BROKEN_OUT <= fifo_rst;\r
+PACKET_TIMEOUT_OUT <= fifo_rst;\r
\r
MED_DATAREADY_OUT <= med_dataready;\r
MED_DATA_OUT <= med_data;\r
jspc29 / trbnet.git / commitdiff