<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_in200_out100" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2012 12 14 18:35:50.458" version="5.3" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="pll_in200_out100" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 12 13:37:14.642" version="5.6" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_in200_out100.lpc" type="lpc" modified="2012 12 14 18:35:48.000"/>
- <File name="pll_in200_out100.vhd" type="top_level_vhdl" modified="2012 12 14 18:35:48.000"/>
- <File name="pll_in200_out100_tmpl.vhd" type="template_vhdl" modified="2012 12 14 18:35:48.000"/>
+ <File name="pll_in200_out100.lpc" type="lpc" modified="2014 08 12 13:36:33.000"/>
+ <File name="pll_in200_out100.vhd" type="top_level_vhdl" modified="2014 08 12 13:36:34.000"/>
+ <File name="pll_in200_out100_tmpl.vhd" type="template_vhdl" modified="2014 08 12 13:36:34.000"/>
</Package>
</DiamondModule>
[Device]
Family=latticeecp3
PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN1156C
+PartName=LFE3-150EA-8FN672C
SpeedGrade=8
-Package=FPBGA1156
+Package=FPBGA672
OperatingCondition=COM
Status=P
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.3
+CoreRevision=5.6
ModuleName=pll_in200_out100
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=12/14/2012
-Time=18:35:48
+Date=08/12/2014
+Time=13:36:33
[Parameters]
Verilog=0
EnCLKOK=1
ClkOKBp=1
enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/d/jspc29/lattice/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw -e
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module Version: 5.6
+--/opt/lattice/diamond/3.2_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw
--- Fri Dec 14 18:35:48 2012
+-- Tue Aug 12 13:36:34 2014
library IEEE;
use IEEE.std_logic_1164.all;
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements