library ieee;\r
use ieee.std_logic_1164.all;\r
-USE IEEE.numeric_std.ALL;\r
-USE IEEE.std_logic_UNSIGNED.ALL;\r
+use IEEE.numeric_std.all;\r
+use IEEE.std_logic_UNSIGNED.all;\r
library work;\r
use work.trb_net_std.all;\r
\r
\r
\r
\r
-component trb_net16_med_scm_sfp_gbe is\r
-generic(\r
-SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE\r
-EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE\r
-USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE\r
-);\r
-port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component trb_net16_med_scm_sfp_gbe;\r
-\r
-\r
-\r
-\r
-\r
-component adc_ltc2308_readout is\r
- generic(\r
- CLOCK_FREQUENCY : integer := 100 --MHz\r
- );\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- ADC_SCK : out std_logic;\r
- ADC_SDI : out std_logic;\r
- ADC_SDO : in std_logic;\r
- ADC_CONVST : out std_logic;\r
-\r
- DAT_ADDR_IN : in std_logic_vector(5 downto 0);\r
- DAT_READ_EN_IN : in std_logic;\r
- DAT_WRITE_EN_IN : in std_logic;\r
- DAT_DATA_OUT : out std_logic_vector(31 downto 0);\r
- DAT_DATA_IN : in std_logic_vector(31 downto 0);\r
- DAT_DATAREADY_OUT : out std_logic;\r
- DAT_NO_MORE_DATA_OUT : out std_logic;\r
- DAT_WRITE_ACK_OUT : out std_logic;\r
- DAT_UNKNOWN_ADDR_OUT : out std_logic;\r
- DAT_TIMEOUT_IN : in std_logic;\r
-\r
- STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_addresses is\r
- generic(\r
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"\r
- );\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- API_DATAREADY_IN : in std_logic;\r
- API_READ_OUT : out std_logic;\r
- RAM_DATA_IN : in std_logic_vector(15 downto 0);\r
- RAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
- RAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
- RAM_WR_IN : in std_logic;\r
- API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- API_DATAREADY_OUT : out std_logic;\r
- API_READ_IN : in std_logic;\r
- ADDRESS_REJECTED : out std_logic;\r
- DONT_UNDERSTAND_OUT : out std_logic;\r
- API_SEND_OUT : out std_logic;\r
- ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
- STAT_DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_api_base is\r
- generic (\r
- API_TYPE : integer range 0 to 1 := c_API_PASSIVE;\r
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;\r
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;\r
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;\r
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;\r
- APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- -- APL Transmitter port\r
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- APL_DATAREADY_IN : in std_logic;\r
- APL_READ_OUT : out std_logic;\r
- APL_SHORT_TRANSFER_IN : in std_logic;\r
- APL_DTYPE_IN : in std_logic_vector (3 downto 0);\r
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
- APL_SEND_IN : in std_logic;\r
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)\r
- -- Receiver port\r
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- APL_TYP_OUT : out std_logic_vector (2 downto 0);\r
- APL_DATAREADY_OUT : out std_logic;\r
- APL_READ_IN : in std_logic;\r
- -- APL Control port\r
- APL_RUN_OUT : out std_logic;\r
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);\r
- APL_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0);\r
- -- Internal direction port\r
- -- the ports with master or slave in their name are to be mapped by the active api\r
- -- to the init respectivly the reply path and vice versa in the passive api.\r
- -- lets define: the "master" path is the path that I send data on.\r
- -- master_data_out and slave_data_in are only used in active API for termination\r
- INT_MASTER_DATAREADY_OUT : out std_logic;\r
- INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_MASTER_READ_IN : in std_logic;\r
- INT_MASTER_DATAREADY_IN : in std_logic;\r
- INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_MASTER_READ_OUT : out std_logic;\r
- INT_SLAVE_DATAREADY_OUT : out std_logic;\r
- INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_SLAVE_READ_IN : in std_logic;\r
- INT_SLAVE_DATAREADY_IN : in std_logic;\r
- INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_SLAVE_READ_OUT : out std_logic;\r
- -- Status and control port\r
- CTRL_SEQNR_RESET : in std_logic;\r
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);\r
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_api_ipu_streaming is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- -- Internal direction port\r
-\r
- FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- FEE_INIT_DATAREADY_OUT : out std_logic;\r
- FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- FEE_INIT_READ_IN : in std_logic;\r
-\r
- FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- FEE_REPLY_DATAREADY_IN : in std_logic;\r
- FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- FEE_REPLY_READ_OUT : out std_logic;\r
-\r
- CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- CTS_INIT_DATAREADY_IN : in std_logic;\r
- CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- CTS_INIT_READ_OUT : out std_logic;\r
-\r
- CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- CTS_REPLY_DATAREADY_OUT : out std_logic;\r
- CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- CTS_REPLY_READ_IN : in std_logic;\r
-\r
- --Event information coming from CTS\r
- CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- CTS_CODE_OUT : out std_logic_vector (7 downto 0);\r
- CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- CTS_START_READOUT_OUT : out std_logic;\r
-\r
- --Information sent to CTS\r
- --status data, equipped with DHDR\r
- CTS_DATA_IN : in std_logic_vector (31 downto 0);\r
- CTS_DATAREADY_IN : in std_logic;\r
- CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM\r
- CTS_READ_OUT : out std_logic;\r
- CTS_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
-\r
- -- Data from Frontends\r
- FEE_DATA_OUT : out std_logic_vector (15 downto 0);\r
- FEE_DATAREADY_OUT : out std_logic;\r
- FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready\r
- FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
- FEE_BUSY_OUT : out std_logic;\r
-\r
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
- CTRL_SEQNR_RESET : in std_logic\r
-\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_api_ipu_streaming_internal is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- -- Internal direction port\r
-\r
- FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- FEE_INIT_DATAREADY_OUT : out std_logic;\r
- FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- FEE_INIT_READ_IN : in std_logic;\r
-\r
- FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- FEE_REPLY_DATAREADY_IN : in std_logic;\r
- FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- FEE_REPLY_READ_OUT : out std_logic;\r
-\r
- --Event information coming from CTS\r
- CTS_SEND_IN : in std_logic;\r
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --valid while start_readout is high\r
- CTS_CODE_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --valid while start_readout is high\r
- \r
- CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
- CTS_BUSY_OUT : out std_logic; --goes high after CTS_SEND_IN, goes low after GBE_READOUT_FINISHED_IN\r
-\r
- --connection to GbE\r
- GBE_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high\r
- GBE_CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
- GBE_CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
- GBE_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high\r
- GBE_CTS_START_READOUT_OUT : out std_logic;\r
-\r
- GBE_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle\r
- GBE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high\r
-\r
- GBE_FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE\r
- GBE_FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid\r
- GBE_FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready\r
- GBE_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again\r
- GBE_FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE\r
- --has been read.\r
-\r
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
- CTRL_SEQNR_RESET : in std_logic\r
-\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_bridge_pcie_apl is\r
- generic(\r
- USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES)\r
- );\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- --TrbNet connect\r
- APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0);\r
- APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0);\r
- APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0);\r
- APL_READ_IN : in std_logic_vector (3-1 downto 0);\r
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0);\r
- APL_DTYPE_OUT : out std_logic_vector (3*4-1 downto 0);\r
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0);\r
- APL_SEND_OUT : out std_logic_vector (3-1 downto 0);\r
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0);\r
- APL_DATA_IN : in std_logic_vector (16*3-1 downto 0);\r
- APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0);\r
- APL_TYP_IN : in std_logic_vector (3*3-1 downto 0);\r
- APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0);\r
- APL_READ_OUT : out std_logic_vector (3-1 downto 0);\r
- APL_RUN_IN : in std_logic_vector (3-1 downto 0);\r
- APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0);\r
- APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0);\r
-\r
- --Internal Data Bus\r
- BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
- BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
- BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
- BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
- BUS_WE_IN : in std_logic;\r
- BUS_CYC_IN : in std_logic;\r
- BUS_STB_IN : in std_logic;\r
- BUS_LOCK_IN : in std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
-\r
- EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
- SEND_RESET_OUT : out std_logic;\r
- --DMA interface\r
-\r
- --Debug\r
- STAT : out std_logic_vector (31 downto 0);\r
- CTRL : in std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_bridge_pcie_endpoint is\r
- generic(\r
- USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES)\r
- );\r
- port(\r
- RESET : in std_logic;\r
- CLK: in std_logic;\r
-\r
- BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
- BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
- BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
- BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
- BUS_WE_IN : in std_logic;\r
- BUS_CYC_IN : in std_logic;\r
- BUS_STB_IN : in std_logic;\r
- BUS_LOCK_IN : in std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
-\r
- MED_DATAREADY_IN : in STD_LOGIC;\r
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out STD_LOGIC;\r
-\r
- MED_DATAREADY_OUT : out STD_LOGIC;\r
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in STD_LOGIC;\r
-\r
- MED_ERROR_IN : in std_logic_vector(2 downto 0);\r
- SEND_RESET_OUT : out std_logic;\r
- STAT : out std_logic_vector(31 downto 0);\r
- STAT_ENDP : out std_logic_vector(31 downto 0);\r
- STAT_API1 : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_bridge_pcie_endpoint_hub is\r
-generic(\r
- NUM_LINKS : integer range 1 to 4 := 2;\r
- COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')\r
- );\r
-port(\r
- RESET : in std_logic;\r
- RESET_TRBNET : in std_logic;\r
- CLK : in std_logic;\r
- CLK_125_IN : in std_logic;\r
-\r
- BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
- BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
- BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
- BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
- BUS_WE_IN : in std_logic;\r
- BUS_CYC_IN : in std_logic;\r
- BUS_STB_IN : in std_logic;\r
- BUS_LOCK_IN : in std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
-\r
- SPI_CLK_OUT : out std_logic;\r
- SPI_D_OUT : out std_logic;\r
- SPI_D_IN : in std_logic;\r
- SPI_CE_OUT : out std_logic;\r
-\r
- MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
- MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);\r
- MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
-\r
- MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
- MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);\r
- MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
-\r
- MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
-\r
- REQUESTOR_ID_IN : in std_logic_vector(15 downto 0);\r
- TX_ST_OUT : out std_logic; --tx first word\r
- TX_END_OUT : out std_logic; --tx last word\r
- TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit\r
- TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out\r
- TX_REQ_OUT : out std_logic; --tx request out\r
- TX_RDY_IN : in std_logic; --tx arbiter can read\r
- TX_VAL_IN : in std_logic; --tx data is valid\r
- TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write\r
- TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words\r
- TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read\r
-\r
- RX_CR_CPLH_OUT : out std_logic;\r
- RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0);\r
- UNEXP_CMPL_OUT : out std_logic;\r
- RX_ST_IN : in std_logic;\r
- RX_END_IN : in std_logic;\r
- RX_DWEN_IN : in std_logic;\r
- RX_DATA_IN : in std_logic_vector(63 downto 0);\r
-\r
- PROGRMN_OUT : out std_logic;\r
- SEND_RESET_OUT : out std_logic;\r
- MAKE_RESET_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-component trb_net_CRC is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- DATA_IN : in std_logic_vector(15 downto 0);\r
- CRC_OUT : out std_logic_vector(15 downto 0);\r
- CRC_match : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_CRC8 is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- DATA_IN : in std_logic_vector(7 downto 0);\r
- CRC_OUT : out std_logic_vector(7 downto 0);\r
- CRC_match : out std_logic\r
- );\r
-end component;\r
-\r
-component ddr_off is\r
- port (\r
- Clk: in std_logic;\r
- Data: in std_logic_vector(1 downto 0);\r
- Q: out std_logic_vector(0 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component dll_in100_out100 is\r
- port (\r
- clk: in std_logic;\r
- aluhold: in std_logic;\r
- clkop: out std_logic;\r
- clkos: out std_logic;\r
- lock: out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component dll_in200_out100 is\r
- port (\r
- clk: in std_logic;\r
- aluhold: in std_logic;\r
- clkop: out std_logic;\r
- clkos: out std_logic;\r
- lock: out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_dummy_fifo is\r
- port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
- WRITE_ENABLE_IN : in std_logic;\r
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
- READ_ENABLE_IN : in std_logic;\r
- FULL_OUT : out std_logic;\r
- EMPTY_OUT : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_endpoint_hades_full is\r
- generic (\r
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
- IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);\r
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- --standard values for output registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
- --set to 0 for unused ctrl registers to save resources\r
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
- --set to 0 for each unused bit in a register\r
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic := '1';\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- -- LVL1 trigger APL\r
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received\r
-\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
- LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
- LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
- LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
-\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
-\r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
- LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT : out std_logic;\r
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
- TRG_SPURIOUS_TRG_OUT : out std_logic;\r
- TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
- TRG_SPIKE_DETECTED_OUT : out std_logic;\r
- TRG_LONG_TRG_OUT : out std_logic; \r
- --Data Port\r
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- --start strobe\r
- IPU_START_READOUT_OUT : out std_logic;\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_IN : in std_logic;\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN : in std_logic;\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT : out std_logic;\r
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
-\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --following ports only used when using internal data port\r
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- REGIO_READ_ENABLE_OUT : out std_logic;\r
- REGIO_WRITE_ENABLE_OUT : out std_logic;\r
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- REGIO_DATAREADY_IN : in std_logic := '0';\r
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
- REGIO_WRITE_ACK_IN : in std_logic := '0';\r
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- REGIO_TIMEOUT_OUT : out std_logic;\r
- --IDRAM is used if no 1-wire interface, onewire used otherwise\r
- REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
- REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
- REGIO_IDRAM_WR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
- REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
-\r
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
- --Debugging & Status information\r
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
- MED_STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
- STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0); \r
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_endpoint_hades_full_handler is\r
- generic (\r
- IBUF_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;\r
- --Configure data handler\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8\r
- );\r
-\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic := '1';\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- --Timing trigger in\r
- TRG_TIMING_TRG_RECEIVED_IN : in std_logic;\r
- --LVL1 trigger to FEE\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received\r
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received\r
- LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
-\r
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
-\r
- --Response from FEE\r
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT : out std_logic;\r
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
- TRG_SPURIOUS_TRG_OUT : out std_logic;\r
- TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
- TRG_SPIKE_DETECTED_OUT : out std_logic;\r
-\r
- --Slow Control Port\r
- --common registers\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- --user defined registers\r
- REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');\r
- REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
- REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --internal data port\r
- BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- BUS_READ_ENABLE_OUT : out std_logic;\r
- BUS_WRITE_ENABLE_OUT : out std_logic;\r
- BUS_TIMEOUT_OUT : out std_logic;\r
- BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- BUS_DATAREADY_IN : in std_logic := '0';\r
- BUS_WRITE_ACK_IN : in std_logic := '0';\r
- BUS_NO_MORE_DATA_IN : in std_logic := '0';\r
- BUS_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- --Onewire\r
- ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
- ONEWIRE_MONITOR_IN : in std_logic := '0';\r
- ONEWIRE_MONITOR_OUT : out std_logic;\r
- --Config endpoint id, if not statically assigned\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');\r
-\r
- --Timing registers\r
- TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds\r
- TIME_LOCAL_OUT : out std_logic_vector ( 7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger\r
- TIME_TICKS_OUT : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick\r
-\r
- --Debugging & Status information\r
- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
- STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
- STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
- STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0); \r
- DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-component trb_net16_endpoint_hades_cts is\r
- generic(\r
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
- IBUF_DEPTH : channel_config_t := (1,6,6,6);\r
- FIFO_TO_INT_DEPTH : channel_config_t := (1,1,6,6);\r
- FIFO_TO_APL_DEPTH : channel_config_t := (1,6,6,6);\r
- INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);\r
- REPLY_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_YES);\r
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES,c_YES,c_NO,c_NO);\r
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);\r
- APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);\r
- ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
- BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers\r
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- --standard values for output registers\r
- REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
- --set to 0 for unused ctrl registers to save resources\r
- REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";\r
- --set to 0 for each unused bit in a register\r
- REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
- REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";\r
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";\r
- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";\r
- REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR\r
- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
- CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
- );\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- -- Media direction port\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in std_logic;\r
-\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
-\r
- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
-\r
- --LVL1 trigger\r
- TRG_SEND_IN : in std_logic;\r
- TRG_TYPE_IN : in std_logic_vector (3 downto 0);\r
- TRG_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);\r
- TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
- TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
- TRG_BUSY_OUT : out std_logic;\r
-\r
- --IPU Channel\r
- IPU_SEND_IN : in std_logic;\r
- IPU_TYPE_IN : in std_logic_vector (3 downto 0);\r
- IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
- -- Receiver port\r
- IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_OUT : out std_logic;\r
- IPU_READ_IN : in std_logic;\r
- IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
- IPU_BUSY_OUT : out std_logic;\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
- REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
- COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
- CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
- --following ports only used when using internal data port\r
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
- REGIO_READ_ENABLE_OUT : out std_logic;\r
- REGIO_WRITE_ENABLE_OUT : out std_logic;\r
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
- REGIO_DATAREADY_IN : in std_logic := '0';\r
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
- REGIO_WRITE_ACK_IN : in std_logic := '0';\r
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
- REGIO_TIMEOUT_OUT : out std_logic;\r
- REGIO_ONEWIRE_INOUT : inout std_logic;\r
- REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
- REGIO_ONEWIRE_MONITOR_IN : in std_logic;\r
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
- TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received\r
- GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
- LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
- STAT_DEBUG_1 : out std_logic_vector(31 downto 0);\r
- STAT_DEBUG_2 : out std_logic_vector(31 downto 0)\r
- );\r
-\r
-end component;\r
-\r
-\r
-\r
-\r
-component etrax_interface is\r
- generic(\r
- STATUS_REGISTERS : integer := 4;\r
- CONTROL_REGISTERS : integer := 4\r
- );\r
- port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- --Connection to Etrax\r
- ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);\r
- ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);\r
- ETRAX_BUS_BUSY : out std_logic;\r
- --Connection to internal FPGA logic (all addresses above 0x100)\r
- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);\r
- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);\r
- INTERNAL_READ_OUT : out std_logic;\r
- INTERNAL_WRITE_OUT : out std_logic;\r
- INTERNAL_DATAREADY_IN : in std_logic;\r
- INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
- --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)\r
- FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);\r
- FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);\r
- --Reset FPGA via Etrax\r
- EXTERNAL_RESET : out std_logic;\r
- STAT : out std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_fifo is\r
- generic (\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_NO;\r
- USE_DATA_COUNT : integer range 0 to 1 := c_NO;\r
- DEPTH : integer := 6\r
- );\r
- port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
- PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
- WRITE_ENABLE_IN : in std_logic;\r
- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
- PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
- READ_ENABLE_IN : in std_logic;\r
- DATA_COUNT_OUT : out std_logic_vector(10 downto 0);\r
- FULL_OUT : out std_logic;\r
- EMPTY_OUT : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net_fifo_16bit_bram_dualport is\r
- generic(\r
- USE_STATUS_FLAGS : integer := c_YES\r
- );\r
- port( read_clock_in : in std_logic;\r
- write_clock_in : in std_logic;\r
- read_enable_in : in std_logic;\r
- write_enable_in : in std_logic;\r
- fifo_gsr_in : in std_logic;\r
- write_data_in : in std_logic_vector(17 downto 0);\r
- read_data_out : out std_logic_vector(17 downto 0);\r
- full_out : out std_logic;\r
- empty_out : out std_logic;\r
- fifostatus_out : out std_logic_vector(3 downto 0);\r
- valid_read_out : out std_logic;\r
- almost_empty_out : out std_logic;\r
- almost_full_out : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
+ component trb_net16_med_scm_sfp_gbe is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE\r
+ USE_200_MHZ : integer range 0 to 1 := c_YES -- DO NOT CHANGE\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component trb_net16_med_scm_sfp_gbe;\r
+\r
+\r
+\r
+\r
+\r
+ component adc_ltc2308_readout is\r
+ generic(\r
+ CLOCK_FREQUENCY : integer := 100 --MHz\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ ADC_SCK : out std_logic;\r
+ ADC_SDI : out std_logic;\r
+ ADC_SDO : in std_logic;\r
+ ADC_CONVST : out std_logic;\r
+\r
+ DAT_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ DAT_READ_EN_IN : in std_logic;\r
+ DAT_WRITE_EN_IN : in std_logic;\r
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ DAT_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_DATAREADY_OUT : out std_logic;\r
+ DAT_NO_MORE_DATA_OUT : out std_logic;\r
+ DAT_WRITE_ACK_OUT : out std_logic;\r
+ DAT_UNKNOWN_ADDR_OUT : out std_logic;\r
+ DAT_TIMEOUT_IN : in std_logic;\r
+\r
+ STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_addresses is\r
+ generic(\r
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ RAM_DATA_IN : in std_logic_vector(15 downto 0);\r
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ RAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
+ RAM_WR_IN : in std_logic;\r
+ API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ ADDRESS_REJECTED : out std_logic;\r
+ DONT_UNDERSTAND_OUT : out std_logic;\r
+ API_SEND_OUT : out std_logic;\r
+ ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_api_base is\r
+ generic (\r
+ API_TYPE : integer range 0 to 1 := c_API_PASSIVE;\r
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; --std_FIFO_DEPTH;\r
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; --std_FIFO_DEPTH;\r
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES;\r
+ SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES;\r
+ APL_WRITE_ALL_WORDS : integer range 0 to 1 := c_NO;\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- APL Transmitter port\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic;\r
+ APL_READ_OUT : out std_logic;\r
+ APL_SHORT_TRANSFER_IN : in std_logic;\r
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+ APL_SEND_IN : in std_logic;\r
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- the target (only for active APIs)\r
+ -- Receiver port\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic;\r
+ APL_READ_IN : in std_logic;\r
+ -- APL Control port\r
+ APL_RUN_OUT : out std_logic;\r
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);\r
+ APL_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0);\r
+ -- Internal direction port\r
+ -- the ports with master or slave in their name are to be mapped by the active api\r
+ -- to the init respectivly the reply path and vice versa in the passive api.\r
+ -- lets define: the "master" path is the path that I send data on.\r
+ -- master_data_out and slave_data_in are only used in active API for termination\r
+ INT_MASTER_DATAREADY_OUT : out std_logic;\r
+ INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_IN : in std_logic;\r
+ INT_MASTER_DATAREADY_IN : in std_logic;\r
+ INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_MASTER_READ_OUT : out std_logic;\r
+ INT_SLAVE_DATAREADY_OUT : out std_logic;\r
+ INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_IN : in std_logic;\r
+ INT_SLAVE_DATAREADY_IN : in std_logic;\r
+ INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_SLAVE_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ CTRL_SEQNR_RESET : in std_logic;\r
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);\r
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
\r
\r
-component fifo_dualclock_width_16_reg is\r
- port (\r
- Data: in std_logic_vector(17 downto 0);\r
- WrClock: in std_logic;\r
- RdClock: in std_logic;\r
- WrEn: in std_logic;\r
- RdEn: in std_logic;\r
- Reset: in std_logic;\r
- RPReset: in std_logic;\r
- Q: out std_logic_vector(17 downto 0);\r
- Empty: out std_logic;\r
- Full: out std_logic);\r
-end component;\r
+\r
+ component trb_net16_api_ipu_streaming is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- Internal direction port\r
+\r
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_INIT_DATAREADY_OUT : out std_logic;\r
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_INIT_READ_IN : in std_logic;\r
+\r
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_REPLY_DATAREADY_IN : in std_logic;\r
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_REPLY_READ_OUT : out std_logic;\r
+\r
+ CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_INIT_DATAREADY_IN : in std_logic;\r
+ CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_INIT_READ_OUT : out std_logic;\r
+\r
+ CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ CTS_REPLY_DATAREADY_OUT : out std_logic;\r
+ CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ CTS_REPLY_READ_IN : in std_logic;\r
+\r
+ --Event information coming from CTS\r
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ CTS_START_READOUT_OUT : out std_logic;\r
+\r
+ --Information sent to CTS\r
+ --status data, equipped with DHDR\r
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);\r
+ CTS_DATAREADY_IN : in std_logic;\r
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM\r
+ CTS_READ_OUT : out std_logic;\r
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+\r
+ -- Data from Frontends\r
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);\r
+ FEE_DATAREADY_OUT : out std_logic;\r
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready\r
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ FEE_BUSY_OUT : out std_logic;\r
+\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ CTRL_SEQNR_RESET : in std_logic\r
+\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_api_ipu_streaming_internal is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- Internal direction port\r
+\r
+ FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_INIT_DATAREADY_OUT : out std_logic;\r
+ FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_INIT_READ_IN : in std_logic;\r
+\r
+ FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ FEE_REPLY_DATAREADY_IN : in std_logic;\r
+ FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ FEE_REPLY_READ_OUT : out std_logic;\r
+\r
+ --Event information coming from CTS\r
+ CTS_SEND_IN : in std_logic;\r
+ CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --valid while start_readout is high\r
+ CTS_CODE_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --valid while start_readout is high\r
+\r
+ CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ CTS_BUSY_OUT : out std_logic; --goes high after CTS_SEND_IN, goes low after GBE_READOUT_FINISHED_IN\r
+\r
+ --connection to GbE\r
+ GBE_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high\r
+ GBE_CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ GBE_CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high\r
+ GBE_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high\r
+ GBE_CTS_START_READOUT_OUT : out std_logic;\r
+\r
+ GBE_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle\r
+ GBE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high\r
+\r
+ GBE_FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE\r
+ GBE_FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid\r
+ GBE_FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready\r
+ GBE_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again\r
+ GBE_FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE\r
+ --has been read.\r
+\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+ CTRL_SEQNR_RESET : in std_logic\r
+\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_pcie_apl is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES)\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ --TrbNet connect\r
+ APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (3*4-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0);\r
+\r
+ --Internal Data Bus\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ --DMA interface\r
+\r
+ --Debug\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_pcie_endpoint is\r
+ generic(\r
+ USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES)\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+\r
+ MED_ERROR_IN : in std_logic_vector(2 downto 0);\r
+ SEND_RESET_OUT : out std_logic;\r
+ STAT : out std_logic_vector(31 downto 0);\r
+ STAT_ENDP : out std_logic_vector(31 downto 0);\r
+ STAT_API1 : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_pcie_endpoint_hub is\r
+ generic(\r
+ NUM_LINKS : integer range 1 to 4 := 2;\r
+ COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ RESET_TRBNET : in std_logic;\r
+ CLK : in std_logic;\r
+ CLK_125_IN : in std_logic;\r
+\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ SPI_CLK_OUT : out std_logic;\r
+ SPI_D_OUT : out std_logic;\r
+ SPI_D_IN : in std_logic;\r
+ SPI_CE_OUT : out std_logic;\r
+\r
+ MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+\r
+ MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+\r
+ MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+\r
+ REQUESTOR_ID_IN : in std_logic_vector(15 downto 0);\r
+ TX_ST_OUT : out std_logic; --tx first word\r
+ TX_END_OUT : out std_logic; --tx last word\r
+ TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit\r
+ TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out\r
+ TX_REQ_OUT : out std_logic; --tx request out\r
+ TX_RDY_IN : in std_logic; --tx arbiter can read\r
+ TX_VAL_IN : in std_logic; --tx data is valid\r
+ TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write\r
+ TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words\r
+ TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read\r
+\r
+ RX_CR_CPLH_OUT : out std_logic;\r
+ RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0);\r
+ UNEXP_CMPL_OUT : out std_logic;\r
+ RX_ST_IN : in std_logic;\r
+ RX_END_IN : in std_logic;\r
+ RX_DWEN_IN : in std_logic;\r
+ RX_DATA_IN : in std_logic_vector(63 downto 0);\r
+\r
+ PROGRMN_OUT : out std_logic;\r
+ SEND_RESET_OUT : out std_logic;\r
+ MAKE_RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component trb_net_CRC is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ CRC_OUT : out std_logic_vector(15 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_CRC8 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(7 downto 0);\r
+ CRC_OUT : out std_logic_vector(7 downto 0);\r
+ CRC_match : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component ddr_off is\r
+ port (\r
+ Clk : in std_logic;\r
+ Data : in std_logic_vector(1 downto 0);\r
+ Q : out std_logic_vector(0 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component dll_in100_out100 is\r
+ port (\r
+ clk : in std_logic;\r
+ aluhold : in std_logic;\r
+ clkop : out std_logic;\r
+ clkos : out std_logic;\r
+ lock : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component dll_in200_out100 is\r
+ port (\r
+ clk : in std_logic;\r
+ aluhold : in std_logic;\r
+ clkop : out std_logic;\r
+ clkos : out std_logic;\r
+ lock : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_dummy_fifo is\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
+ READ_ENABLE_IN : in std_logic;\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_endpoint_hades_full is\r
+ generic (\r
+ USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES);\r
+ IBUF_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1);\r
+ IBUF_SECURE_MODE : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ API_SECURE_MODE_TO_APL : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ API_SECURE_MODE_TO_INT : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_YES, c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ -- LVL1 trigger APL\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received\r
+\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+\r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+ TRG_LONG_TRG_OUT : out std_logic;\r
+ --Data Port\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT : out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+\r
+\r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ --IDRAM is used if no 1-wire interface, onewire used otherwise\r
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";\r
+ REGIO_IDRAM_WR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+\r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ MED_STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_endpoint_hades_full_handler is\r
+ generic (\r
+ IBUF_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8\r
+ );\r
+\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic := '1';\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN : in std_logic;\r
+ --LVL1 trigger to FEE\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+\r
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only\r
+\r
+ --Response from FEE\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ --Information about trigger handler errors\r
+ TRG_MULTIPLE_TRG_OUT : out std_logic;\r
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;\r
+ TRG_SPURIOUS_TRG_OUT : out std_logic;\r
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;\r
+ TRG_SPIKE_DETECTED_OUT : out std_logic;\r
+\r
+ --Slow Control Port\r
+ --common registers\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ --user defined registers\r
+ REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');\r
+ REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);\r
+ REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --internal data port\r
+ BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ BUS_READ_ENABLE_OUT : out std_logic;\r
+ BUS_WRITE_ENABLE_OUT : out std_logic;\r
+ BUS_TIMEOUT_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ BUS_DATAREADY_IN : in std_logic := '0';\r
+ BUS_WRITE_ACK_IN : in std_logic := '0';\r
+ BUS_NO_MORE_DATA_IN : in std_logic := '0';\r
+ BUS_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ --Onewire\r
+ ONEWIRE_INOUT : inout std_logic; --temperature sensor\r
+ ONEWIRE_MONITOR_IN : in std_logic := '0';\r
+ ONEWIRE_MONITOR_OUT : out std_logic;\r
+ --Config endpoint id, if not statically assigned\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');\r
+\r
+ --Timing registers\r
+ TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds\r
+ TIME_LOCAL_OUT : out std_logic_vector (7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger\r
+ TIME_TICKS_OUT : out std_logic_vector (1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+\r
+ --Debugging & Status information\r
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);\r
+ CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');\r
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');\r
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);\r
+ STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0);\r
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component trb_net16_endpoint_hades_cts is\r
+ generic(\r
+ USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES);\r
+ IBUF_DEPTH : channel_config_t := (1, 6, 6, 6);\r
+ FIFO_TO_INT_DEPTH : channel_config_t := (1, 1, 6, 6);\r
+ FIFO_TO_APL_DEPTH : channel_config_t := (1, 6, 6, 6);\r
+ INIT_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO);\r
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_YES);\r
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO);\r
+ USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES);\r
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO);\r
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";\r
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";\r
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers\r
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001";\r
+ --set to 0 for each unused bit in a register\r
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000";\r
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000";\r
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000";\r
+ REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR\r
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;\r
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+\r
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);\r
+\r
+ --LVL1 trigger\r
+ TRG_SEND_IN : in std_logic;\r
+ TRG_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ TRG_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ TRG_INFORMATION_IN : in std_logic_vector (23 downto 0);\r
+ TRG_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ TRG_BUSY_OUT : out std_logic;\r
+\r
+ --IPU Channel\r
+ IPU_SEND_IN : in std_logic;\r
+ IPU_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_RND_CODE_IN : in std_logic_vector (7 downto 0);\r
+ -- Receiver port\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_BUSY_OUT : out std_logic;\r
+\r
+ -- Slow Control Data Port\r
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');\r
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);\r
+ --following ports only used when using internal data port\r
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);\r
+ REGIO_READ_ENABLE_OUT : out std_logic;\r
+ REGIO_WRITE_ENABLE_OUT : out std_logic;\r
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);\r
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');\r
+ REGIO_DATAREADY_IN : in std_logic := '0';\r
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';\r
+ REGIO_WRITE_ACK_IN : in std_logic := '0';\r
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';\r
+ REGIO_TIMEOUT_OUT : out std_logic;\r
+ REGIO_ONEWIRE_INOUT : inout std_logic;\r
+ REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
+ REGIO_ONEWIRE_MONITOR_IN : in std_logic;\r
+ REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');\r
+ TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received\r
+ GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick\r
+ STAT_DEBUG_1 : out std_logic_vector(31 downto 0);\r
+ STAT_DEBUG_2 : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component etrax_interface is\r
+ generic(\r
+ STATUS_REGISTERS : integer := 4;\r
+ CONTROL_REGISTERS : integer := 4\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ --Connection to Etrax\r
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);\r
+ ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);\r
+ ETRAX_BUS_BUSY : out std_logic;\r
+ --Connection to internal FPGA logic (all addresses above 0x100)\r
+ INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);\r
+ INTERNAL_READ_OUT : out std_logic;\r
+ INTERNAL_WRITE_OUT : out std_logic;\r
+ INTERNAL_DATAREADY_IN : in std_logic;\r
+ INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)\r
+ FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);\r
+ FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);\r
+ --Reset FPGA via Etrax\r
+ EXTERNAL_RESET : out std_logic;\r
+ STAT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_fifo is\r
+ generic (\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_NO;\r
+ USE_DATA_COUNT : integer range 0 to 1 := c_NO;\r
+ DEPTH : integer := 6\r
+ );\r
+ port (\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_IN : in std_logic_vector(1 downto 0);\r
+ WRITE_ENABLE_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);\r
+ PACKET_NUM_OUT : out std_logic_vector(1 downto 0);\r
+ READ_ENABLE_IN : in std_logic;\r
+ DATA_COUNT_OUT : out std_logic_vector(10 downto 0);\r
+ FULL_OUT : out std_logic;\r
+ EMPTY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_fifo_16bit_bram_dualport is\r
+ generic(\r
+ USE_STATUS_FLAGS : integer := c_YES\r
+ );\r
+ port(read_clock_in : in std_logic;\r
+ write_clock_in : in std_logic;\r
+ read_enable_in : in std_logic;\r
+ write_enable_in : in std_logic;\r
+ fifo_gsr_in : in std_logic;\r
+ write_data_in : in std_logic_vector(17 downto 0);\r
+ read_data_out : out std_logic_vector(17 downto 0);\r
+ full_out : out std_logic;\r
+ empty_out : out std_logic;\r
+ fifostatus_out : out std_logic_vector(3 downto 0);\r
+ valid_read_out : out std_logic;\r
+ almost_empty_out : out std_logic;\r
+ almost_full_out : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component fifo_dualclock_width_16_reg is\r
+ port (\r
+ Data : in std_logic_vector(17 downto 0);\r
+ WrClock : in std_logic;\r
+ RdClock : in std_logic;\r
+ WrEn : in std_logic;\r
+ RdEn : in std_logic;\r
+ Reset : in std_logic;\r
+ RPReset : in std_logic;\r
+ Q : out std_logic_vector(17 downto 0);\r
+ Empty : out std_logic;\r
+ Full : out std_logic);\r
+ end component;\r
\r
\r
\r
\r
-- component trb_net16_gbe_buf is\r
-- generic(\r
--- DO_SIMULATION : integer range 0 to 1 := 1;\r
--- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
+-- DO_SIMULATION : integer range 0 to 1 := 1;\r
+-- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
-- );\r
-- port(\r
--- CLK : in std_logic;\r
--- TEST_CLK : in std_logic; -- only for simulation!\r
--- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
--- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
--- RESET : in std_logic;\r
--- GSR_N : in std_logic;\r
--- -- Debug\r
--- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
--- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
--- -- configuration interface\r
--- IP_CFG_START_IN : in std_logic;\r
--- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
--- IP_CFG_DONE_OUT : out std_logic;\r
--- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
--- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
--- IP_CFG_MEM_CLK_OUT : out std_logic;\r
--- MR_RESET_IN : in std_logic;\r
--- MR_MODE_IN : in std_logic;\r
--- MR_RESTART_IN : in std_logic;\r
--- -- gk 29.03.10\r
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
--- SLV_READ_IN : in std_logic;\r
--- SLV_WRITE_IN : in std_logic;\r
--- SLV_BUSY_OUT : out std_logic;\r
--- SLV_ACK_OUT : out std_logic;\r
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
--- -- gk 22.04.10\r
--- -- registers setup interface\r
--- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
--- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
--- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
--- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
--- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
--- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
--- -- gk 23.04.10\r
--- LED_PACKET_SENT_OUT : out std_logic;\r
--- LED_AN_DONE_N_OUT : out std_logic;\r
--- -- CTS interface\r
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
--- CTS_START_READOUT_IN : in std_logic;\r
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
--- CTS_DATAREADY_OUT : out std_logic;\r
--- CTS_READOUT_FINISHED_OUT : out std_logic;\r
--- CTS_READ_IN : in std_logic;\r
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
--- -- Data payload interface\r
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
--- FEE_DATAREADY_IN : in std_logic;\r
--- FEE_READ_OUT : out std_logic;\r
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
--- FEE_BUSY_IN : in std_logic;\r
--- --SFP Connection\r
--- SFP_RXD_P_IN : in std_logic;\r
--- SFP_RXD_N_IN : in std_logic;\r
--- SFP_TXD_P_OUT : out std_logic;\r
--- SFP_TXD_N_OUT : out std_logic;\r
--- SFP_REFCLK_P_IN : in std_logic;\r
--- SFP_REFCLK_N_IN : in std_logic;\r
--- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
--- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
--- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
--- -- debug ports\r
--- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+-- CLK : in std_logic;\r
+-- TEST_CLK : in std_logic; -- only for simulation!\r
+-- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+-- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+-- RESET : in std_logic;\r
+-- GSR_N : in std_logic;\r
+-- -- Debug\r
+-- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
+-- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
+-- -- configuration interface\r
+-- IP_CFG_START_IN : in std_logic;\r
+-- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
+-- IP_CFG_DONE_OUT : out std_logic;\r
+-- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
+-- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- IP_CFG_MEM_CLK_OUT : out std_logic;\r
+-- MR_RESET_IN : in std_logic;\r
+-- MR_MODE_IN : in std_logic;\r
+-- MR_RESTART_IN : in std_logic;\r
+-- -- gk 29.03.10\r
+-- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+-- SLV_READ_IN : in std_logic;\r
+-- SLV_WRITE_IN : in std_logic;\r
+-- SLV_BUSY_OUT : out std_logic;\r
+-- SLV_ACK_OUT : out std_logic;\r
+-- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+-- -- gk 22.04.10\r
+-- -- registers setup interface\r
+-- BUS_ADDR_IN : in std_logic_vector(7 downto 0);\r
+-- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10\r
+-- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10\r
+-- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10\r
+-- BUS_ACK_OUT : out std_logic; -- gk 26.04.10\r
+-- -- gk 23.04.10\r
+-- LED_PACKET_SENT_OUT : out std_logic;\r
+-- LED_AN_DONE_N_OUT : out std_logic;\r
+-- -- CTS interface\r
+-- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+-- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+-- CTS_START_READOUT_IN : in std_logic;\r
+-- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
+-- CTS_DATAREADY_OUT : out std_logic;\r
+-- CTS_READOUT_FINISHED_OUT : out std_logic;\r
+-- CTS_READ_IN : in std_logic;\r
+-- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+-- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+-- -- Data payload interface\r
+-- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
+-- FEE_DATAREADY_IN : in std_logic;\r
+-- FEE_READ_OUT : out std_logic;\r
+-- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+-- FEE_BUSY_IN : in std_logic;\r
+-- --SFP Connection\r
+-- SFP_RXD_P_IN : in std_logic;\r
+-- SFP_RXD_N_IN : in std_logic;\r
+-- SFP_TXD_P_OUT : out std_logic;\r
+-- SFP_TXD_N_OUT : out std_logic;\r
+-- SFP_REFCLK_P_IN : in std_logic;\r
+-- SFP_REFCLK_N_IN : in std_logic;\r
+-- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+-- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+-- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
+-- -- debug ports\r
+-- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-- );\r
-- end component;\r
\r
\r
-component fpga_reboot is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- DO_REBOOT : in std_logic;\r
- PROGRAMN : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component handler_data is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
-\r
- --LVL1 Handler\r
- LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts\r
- LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type\r
- LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number\r
- LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
- LVL1_TRG_RELEASE_OUT : out std_logic;\r
-\r
- --FEE\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
-\r
- --IPU Handler\r
- IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
- IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
-\r
- IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
- IPU_HDR_DATA_READ_IN : in std_logic;\r
- IPU_HDR_DATA_EMPTY_OUT : out std_logic;\r
-\r
- TMG_TRG_ERROR_IN : in std_logic;\r
- MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; \r
- --Status\r
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
-\r
- --Debug\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component handler_ipu is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
-\r
- --From Data Handler\r
- DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
- DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
- DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);\r
- DAT_HDR_DATA_READ_OUT : out std_logic;\r
- DAT_HDR_DATA_EMPTY_IN : in std_logic;\r
-\r
- --To IPU Channel\r
- IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
- IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
- IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
- IPU_START_READOUT_IN : in std_logic;\r
- IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_OUT : out std_logic;\r
- IPU_READOUT_FINISHED_OUT : out std_logic;\r
- IPU_READ_IN : in std_logic;\r
- IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
-\r
- --Debug\r
- STATUS_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-\r
-end component;\r
-\r
-\r
-\r
-component handler_lvl1 is\r
- generic(\r
- TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- RESET : in std_logic;\r
- RESET_FLAGS_IN : in std_logic;\r
- RESET_STATS_IN : in std_logic;\r
- CLOCK : in std_logic;\r
- --Timing Trigger\r
- LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics\r
- LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger\r
- --LVL1_handler connection\r
- LVL1_TRG_RECEIVED_IN : in std_logic;\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS\r
- LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS\r
-\r
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release\r
- LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter\r
- LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter\r
-\r
- --FEE logic / Data Handler\r
- LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid\r
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received\r
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received\r
- LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
- LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected\r
- LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);\r
- LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10\r
- LVL1_LONG_TRG_OUT : out std_logic; \r
- SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10\r
-\r
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE\r
- LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE\r
-\r
- --Stat/Control\r
- STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers\r
- TRG_ENABLE_IN : in std_logic; -- trigger enable flag\r
- TRG_INVERT_IN : in std_logic; -- trigger invert flag\r
- COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0);\r
- --Debug\r
- DEBUG_OUT : out std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component handler_trigger_and_data is\r
- generic(\r
- DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
- DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
- TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
- HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
- );\r
- port(\r
- CLOCK : in std_logic;\r
- RESET : in std_logic;\r
- RESET_IPU : in std_logic;\r
-\r
- --To Endpoint\r
- --Timing Trigger (registered)\r
- LVL1_VALID_TRIGGER_IN : in std_logic;\r
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- --LVL1_handler connection\r
- LVL1_TRG_DATA_VALID_IN : in std_logic;\r
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
- LVL1_TRG_RELEASE_OUT : out std_logic;\r
-\r
- --IPU channel\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
- IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);\r
- IPU_START_READOUT_IN : in std_logic;\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0);\r
- IPU_DATAREADY_OUT : out std_logic;\r
- IPU_READOUT_FINISHED_OUT : out std_logic;\r
- IPU_READ_IN : in std_logic;\r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
-\r
- --To FEE\r
- --FEE to Trigger\r
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
-\r
- --Data Input from FEE\r
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
-\r
- TMG_TRG_ERROR_IN : in std_logic;\r
- --Status Registers\r
- STATUS_OUT : out std_logic_vector(127 downto 0);\r
- STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
- STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
- TIMER_TICKS_IN : in std_logic_vector(1 downto 0);\r
- STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);\r
- STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);\r
- STATISTICS_READY_OUT : out std_logic;\r
- STATISTICS_READ_IN : in std_logic;\r
- STATISTICS_UNKNOWN_OUT : out std_logic;\r
-\r
- --Debug\r
- DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);\r
- DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)\r
-\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_ibuf is\r
- generic (\r
- DEPTH : integer range 0 to 7 := c_FIFO_BRAM;\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
- USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
- -- Internal direction port\r
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_DATAREADY_OUT : out std_logic;\r
- INT_INIT_READ_IN : in std_logic;\r
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_DATAREADY_OUT : out std_logic;\r
- INT_REPLY_READ_IN : in std_logic;\r
- INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
- -- Status and control port\r
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_BUFFER : out std_logic_vector (31 downto 0);\r
- CTRL_STAT : in std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component fifo_36x512 is\r
- port (\r
- Data: in std_logic_vector(35 downto 0);\r
- Clock: in std_logic;\r
- WrEn: in std_logic;\r
- RdEn: in std_logic;\r
- Reset: in std_logic;\r
- Q: out std_logic_vector(35 downto 0);\r
- Empty: out std_logic;\r
- Full: out std_logic\r
- );\r
-end component;\r
+ component fpga_reboot is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DO_REBOOT : in std_logic;\r
+ PROGRAMN : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component handler_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --LVL1 Handler\r
+ LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type\r
+ LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number\r
+ LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+\r
+ --FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ --IPU Handler\r
+ IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+\r
+ IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_HDR_DATA_READ_IN : in std_logic;\r
+ IPU_HDR_DATA_EMPTY_OUT : out std_logic;\r
+\r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF";\r
+ --Status\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+\r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component handler_ipu is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --From Data Handler\r
+ DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0);\r
+ DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0);\r
+ DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0);\r
+ DAT_HDR_DATA_READ_OUT : out std_logic;\r
+ DAT_HDR_DATA_EMPTY_IN : in std_logic;\r
+\r
+ --To IPU Channel\r
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+\r
+ --Debug\r
+ STATUS_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+\r
+ end component;\r
+\r
+\r
+\r
+ component handler_lvl1 is\r
+ generic(\r
+ TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ RESET_FLAGS_IN : in std_logic;\r
+ RESET_STATS_IN : in std_logic;\r
+ CLOCK : in std_logic;\r
+ --Timing Trigger\r
+ LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics\r
+ LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger\r
+ --LVL1_handler connection\r
+ LVL1_TRG_RECEIVED_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS\r
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS\r
+\r
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release\r
+ LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter\r
+ LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter\r
+\r
+ --FEE logic / Data Handler\r
+ LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid\r
+ LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received\r
+ LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received\r
+ LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...)\r
+ LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected\r
+ LVL1_DELAY_OUT : out std_logic_vector(15 downto 0);\r
+ LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10\r
+ LVL1_LONG_TRG_OUT : out std_logic;\r
+ SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10\r
+\r
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE\r
+ LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE\r
+\r
+ --Stat/Control\r
+ STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers\r
+ TRG_ENABLE_IN : in std_logic; -- trigger enable flag\r
+ TRG_INVERT_IN : in std_logic; -- trigger invert flag\r
+ COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0);\r
+ --Debug\r
+ DEBUG_OUT : out std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component handler_trigger_and_data is\r
+ generic(\r
+ DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;\r
+ DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;\r
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8;\r
+ TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;\r
+ HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;\r
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8\r
+ );\r
+ port(\r
+ CLOCK : in std_logic;\r
+ RESET : in std_logic;\r
+ RESET_IPU : in std_logic;\r
+\r
+ --To Endpoint\r
+ --Timing Trigger (registered)\r
+ LVL1_VALID_TRIGGER_IN : in std_logic;\r
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ --LVL1_handler connection\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+ LVL1_TRG_RELEASE_OUT : out std_logic;\r
+\r
+ --IPU channel\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ IPU_START_READOUT_IN : in std_logic;\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ IPU_DATAREADY_OUT : out std_logic;\r
+ IPU_READOUT_FINISHED_OUT : out std_logic;\r
+ IPU_READ_IN : in std_logic;\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0);\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);\r
+\r
+ --To FEE\r
+ --FEE to Trigger\r
+ FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+\r
+ --Data Input from FEE\r
+ FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+ FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);\r
+\r
+ TMG_TRG_ERROR_IN : in std_logic;\r
+ MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF";\r
+ --Status Registers\r
+ STATUS_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);\r
+ STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector(1 downto 0);\r
+ STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0);\r
+ STATISTICS_READY_OUT : out std_logic;\r
+ STATISTICS_READ_IN : in std_logic;\r
+ STATISTICS_UNKNOWN_OUT : out std_logic;\r
+\r
+ --Debug\r
+ DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0);\r
+ DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0)\r
+\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_ibuf is\r
+ generic (\r
+ DEPTH : integer range 0 to 7 := c_FIFO_BRAM;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
+ -- Status and control port\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component fifo_36x512 is\r
+ port (\r
+ Data : in std_logic_vector(35 downto 0);\r
+ Clock : in std_logic;\r
+ WrEn : in std_logic;\r
+ RdEn : in std_logic;\r
+ Reset : in std_logic;\r
+ Q : out std_logic_vector(35 downto 0);\r
+ Empty : out std_logic;\r
+ Full : out std_logic\r
+ );\r
+ end component;\r
\r
\r
--component fifo_var_oreg is\r
\r
\r
\r
-component trb_net16_iobuf is\r
- generic (\r
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;\r
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
- SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;\r
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;\r
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
- USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
- INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES;\r
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;\r
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_INIT_DATAREADY_OUT : out std_logic;\r
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_INIT_READ_IN : in std_logic;\r
- MED_REPLY_DATAREADY_OUT : out std_logic;\r
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_REPLY_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic;\r
- MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
- -- Internal direction port\r
- INT_INIT_DATAREADY_OUT : out std_logic;\r
- INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_READ_IN : in std_logic;\r
- INT_INIT_DATAREADY_IN : in std_logic;\r
- INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_INIT_READ_OUT : out std_logic;\r
- INT_REPLY_DATAREADY_OUT : out std_logic;\r
- INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_READ_IN : in std_logic;\r
- INT_REPLY_DATAREADY_IN : in std_logic;\r
- INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_REPLY_READ_OUT : out std_logic;\r
- -- Status and control port\r
- STAT_GEN : out std_logic_vector (31 downto 0);\r
- STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);\r
- CTRL_GEN : in std_logic_vector (31 downto 0);\r
- CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');\r
- STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
- STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
- STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
- STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
- TIMER_TICKS_IN : in std_logic_vector (1 downto 0);\r
- CTRL_STAT : in std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_io_multiplexer is\r
- generic(\r
- USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_IN : in STD_LOGIC;\r
- MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out STD_LOGIC;\r
- MED_DATAREADY_OUT : out STD_LOGIC;\r
- MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN : in STD_LOGIC;\r
- -- Internal direction port\r
- INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);\r
- INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
- INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);\r
- INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
- INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);\r
- -- Status and control port\r
- CTRL : in STD_LOGIC_VECTOR (31 downto 0);\r
- STAT : out STD_LOGIC_VECTOR (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_ipudata is\r
- generic(\r
- DO_CHECKS : integer range c_NO to c_YES := c_YES\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Port to API\r
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_DATAREADY_OUT : out std_logic;\r
- API_READ_IN : in std_logic;\r
- API_SHORT_TRANSFER_OUT : out std_logic;\r
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- API_SEND_OUT : out std_logic;\r
- -- Receiver port\r
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_TYP_IN : in std_logic_vector (2 downto 0);\r
- API_DATAREADY_IN : in std_logic;\r
- API_READ_OUT : out std_logic;\r
- -- APL Control port\r
- API_RUN_IN : in std_logic;\r
- API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
- API_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
-\r
- --Information received with request\r
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);\r
- --start strobe\r
- IPU_START_READOUT_OUT: out std_logic;\r
- --detector data, equipped with DHDR\r
- IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
- IPU_DATAREADY_IN : in std_logic;\r
- --no more data, end transfer, send TRM\r
- IPU_READOUT_FINISHED_IN : in std_logic;\r
- --will be low every second cycle due to 32bit -> 16bit conversion\r
- IPU_READ_OUT : out std_logic;\r
- IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
- IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
-\r
- STAT_DEBUG : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
+ component trb_net16_iobuf is\r
+ generic (\r
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; --std_FIFO_DEPTH;\r
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; --std_IBUF_SECURE_MODE;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;\r
+ SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION;\r
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;\r
+ INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;\r
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;\r
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_INIT_DATAREADY_OUT : out std_logic;\r
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_INIT_READ_IN : in std_logic;\r
+ MED_REPLY_DATAREADY_OUT : out std_logic;\r
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_REPLY_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_INIT_DATAREADY_OUT : out std_logic;\r
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_IN : in std_logic;\r
+ INT_INIT_DATAREADY_IN : in std_logic;\r
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_INIT_READ_OUT : out std_logic;\r
+ INT_REPLY_DATAREADY_OUT : out std_logic;\r
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_IN : in std_logic;\r
+ INT_REPLY_DATAREADY_IN : in std_logic;\r
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_REPLY_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ STAT_GEN : out std_logic_vector (31 downto 0);\r
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_GEN : in std_logic_vector (31 downto 0);\r
+ CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0');\r
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0);\r
+ STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);\r
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0);\r
+ CTRL_STAT : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_io_multiplexer is\r
+ generic(\r
+ USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO)\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ -- Internal direction port\r
+ INT_DATA_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);\r
+ INT_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);\r
+ INT_DATAREADY_IN : in std_logic_vector (2**c_MUX_WIDTH-1 downto 0);\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);\r
+ INT_READ_OUT : out std_logic_vector (2**c_MUX_WIDTH-1 downto 0);\r
+ -- Status and control port\r
+ CTRL : in std_logic_vector (31 downto 0);\r
+ STAT : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_ipudata is\r
+ generic(\r
+ DO_CHECKS : integer range c_NO to c_YES := c_YES\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Port to API\r
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ API_SHORT_TRANSFER_OUT : out std_logic;\r
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ API_SEND_OUT : out std_logic;\r
+ -- Receiver port\r
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_TYP_IN : in std_logic_vector (2 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ -- APL Control port\r
+ API_RUN_IN : in std_logic;\r
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
+ API_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);\r
+\r
+ --Information received with request\r
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);\r
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ --start strobe\r
+ IPU_START_READOUT_OUT : out std_logic;\r
+ --detector data, equipped with DHDR\r
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ IPU_DATAREADY_IN : in std_logic;\r
+ --no more data, end transfer, send TRM\r
+ IPU_READOUT_FINISHED_IN : in std_logic;\r
+ --will be low every second cycle due to 32bit -> 16bit conversion\r
+ IPU_READ_OUT : out std_logic;\r
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);\r
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);\r
+\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
-- \r
-- component trb_net16_gbe_buf is\r
-- generic(\r
--- DO_SIMULATION : integer range 0 to 1 := 1;\r
+-- DO_SIMULATION : integer range 0 to 1 := 1;\r
-- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1\r
-- );\r
-- port(\r
--- CLK : in std_logic;\r
--- TEST_CLK : in std_logic; -- only for simulation!\r
--- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
--- RESET : in std_logic;\r
--- GSR_N : in std_logic;\r
+-- CLK : in std_logic;\r
+-- TEST_CLK : in std_logic; -- only for simulation!\r
+-- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode\r
+-- RESET : in std_logic;\r
+-- GSR_N : in std_logic;\r
-- -- Debug\r
--- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
--- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
+-- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0);\r
+-- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0);\r
-- -- configuration interface\r
--- IP_CFG_START_IN : in std_logic;\r
--- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
--- IP_CFG_DONE_OUT : out std_logic;\r
--- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
--- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
--- IP_CFG_MEM_CLK_OUT : out std_logic;\r
--- MR_RESET_IN : in std_logic;\r
--- MR_MODE_IN : in std_logic;\r
--- MR_RESTART_IN : in std_logic;\r
+-- IP_CFG_START_IN : in std_logic;\r
+-- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0);\r
+-- IP_CFG_DONE_OUT : out std_logic;\r
+-- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0);\r
+-- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0);\r
+-- IP_CFG_MEM_CLK_OUT : out std_logic;\r
+-- MR_RESET_IN : in std_logic;\r
+-- MR_MODE_IN : in std_logic;\r
+-- MR_RESTART_IN : in std_logic;\r
-- -- gk 29.03.10\r
-- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
-- SLV_READ_IN : in std_logic;\r
-- LED_PACKET_SENT_OUT : out std_logic;\r
-- LED_AN_DONE_N_OUT : out std_logic;\r
-- -- CTS interface\r
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
--- CTS_START_READOUT_IN : in std_logic;\r
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
--- CTS_DATAREADY_OUT : out std_logic;\r
--- CTS_READOUT_FINISHED_OUT : out std_logic;\r
--- CTS_READ_IN : in std_logic;\r
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+-- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);\r
+-- CTS_CODE_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);\r
+-- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);\r
+-- CTS_START_READOUT_IN : in std_logic;\r
+-- CTS_DATA_OUT : out std_logic_vector (31 downto 0);\r
+-- CTS_DATAREADY_OUT : out std_logic;\r
+-- CTS_READOUT_FINISHED_OUT : out std_logic;\r
+-- CTS_READ_IN : in std_logic;\r
+-- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);\r
+-- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
-- -- Data payload interface\r
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
--- FEE_DATAREADY_IN : in std_logic;\r
--- FEE_READ_OUT : out std_logic;\r
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
--- FEE_BUSY_IN : in std_logic;\r
+-- FEE_DATA_IN : in std_logic_vector (15 downto 0);\r
+-- FEE_DATAREADY_IN : in std_logic;\r
+-- FEE_READ_OUT : out std_logic;\r
+-- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);\r
+-- FEE_BUSY_IN : in std_logic;\r
-- --SFP Connection\r
--- SFP_RXD_P_IN : in std_logic;\r
--- SFP_RXD_N_IN : in std_logic;\r
--- SFP_TXD_P_OUT : out std_logic;\r
--- SFP_TXD_N_OUT : out std_logic;\r
--- SFP_REFCLK_P_IN : in std_logic;\r
--- SFP_REFCLK_N_IN : in std_logic;\r
--- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
--- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
--- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
+-- SFP_RXD_P_IN : in std_logic;\r
+-- SFP_RXD_N_IN : in std_logic;\r
+-- SFP_TXD_P_OUT : out std_logic;\r
+-- SFP_TXD_N_OUT : out std_logic;\r
+-- SFP_REFCLK_P_IN : in std_logic;\r
+-- SFP_REFCLK_N_IN : in std_logic;\r
+-- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+-- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+-- SFP_TXDIS_OUT : out std_logic; -- SFP disable\r
-- -- debug ports\r
-- MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);\r
--- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+-- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)\r
-- );\r
-- end component;\r
\r
\r
\r
\r
-component ipu_dummy is\r
- port( CLK_IN : in std_logic; -- 100MHz local clock\r
- CLEAR_IN : in std_logic;\r
- RESET_IN : in std_logic; -- synchronous reset\r
- -- Slow control signals\r
- MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
- MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
- CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
- -- IPU channel connections\r
- IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
- IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
- IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
- IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
- IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
- IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
- IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
- IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
- IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
- -- DHDR buffer\r
- LVL1_FIFO_RD_OUT : out std_logic;\r
- LVL1_FIFO_EMPTY_IN : in std_logic;\r
- LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
- LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
- LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
- LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
- -- Debug signals\r
- DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
- DBG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_lsm_sfp is\r
- generic(\r
- CHECK_FOR_CV : integer := c_YES;\r
- HIGHSPEED_STARTUP : integer := c_NO \r
- );\r
- port(\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
- -- status signals\r
- SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)\r
- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
- SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
- SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
- SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
- SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)\r
- SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)\r
- -- control signals\r
- FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
- LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
- TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation\r
- RX_ALLOW_OUT : out std_logic; -- allow normal receive operation\r
- SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)\r
- -- debug signals\r
- STAT_OP : out std_logic_vector(15 downto 0);\r
- CTRL_OP : in std_logic_vector(15 downto 0);\r
- STAT_DEBUG : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_8_SDR_OS is\r
- generic(\r
- TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1\r
- );\r
- port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- INT_DATAREADY_OUT : out std_logic;\r
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_IN : in std_logic;\r
-\r
- INT_DATAREADY_IN : in std_logic;\r
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_OUT : out std_logic;\r
-\r
- -- Media direction port\r
- TX_DATA_OUT : out std_logic_vector (7 downto 0);\r
- TX_CLK_OUT : out std_logic;\r
- TX_CTRL_OUT : out std_logic_vector (1 downto 0);\r
- RX_DATA_IN : in std_logic_vector (7 downto 0);\r
- RX_CLK_IN : in std_logic;\r
- RX_CTRL_IN : in std_logic_vector (1 downto 0);\r
-\r
- -- Status and control port\r
- STAT_OP: out std_logic_vector (15 downto 0);\r
- CTRL_OP: in std_logic_vector (15 downto 0);\r
-\r
- STAT: out std_logic_vector (31 downto 0);\r
- CTRL: in std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_fot is\r
- port(\r
- CLK : in std_logic;\r
- CLK_25 : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
- CLEAR : in std_logic;\r
-\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
-\r
- --SFP Connection\r
- TXP : out std_logic;\r
- TXN : out std_logic;\r
- RXP : in std_logic;\r
- RXN : in std_logic;\r
- SD : in std_logic;\r
-\r
- -- Status and control port\r
- RX_CLOCK_OUT : out std_logic;\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_fot_4 is\r
- generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO\r
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
- port(\r
- CLK : in std_logic;\r
- CLK_25 : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
- --SFP Connection\r
- TXP : out std_logic_vector(3 downto 0);\r
- TXN : out std_logic_vector(3 downto 0);\r
- RXP : in std_logic_vector(3 downto 0);\r
- RXN : in std_logic_vector(3 downto 0);\r
- SD : in std_logic_vector(3 downto 0);\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (63 downto 0);\r
- CTRL_OP : in std_logic_vector (63 downto 0);\r
- STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
- STAT_DEBUG : out std_logic_vector (255 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_fot_4_ctc is\r
- generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO\r
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
- port(\r
- CLK : in std_logic;\r
- CLK_25 : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
- CLEAR : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
-\r
- --SFP Connection\r
- TXP : out std_logic_vector(3 downto 0);\r
- TXN : out std_logic_vector(3 downto 0);\r
- RXP : in std_logic_vector(3 downto 0);\r
- RXN : in std_logic_vector(3 downto 0);\r
- SD : in std_logic_vector(3 downto 0);\r
-\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (63 downto 0);\r
- CTRL_OP : in std_logic_vector (63 downto 0);\r
- STAT_REG_OUT : out std_logic_vector (511 downto 0);\r
- STAT_DEBUG : out std_logic_vector (255 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_sfp is\r
- generic(\r
- SERDES_NUM : integer range 0 to 3 := 0;\r
- EXT_CLOCK : integer range 0 to 1 := c_NO\r
- );\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_sfp_gbe is\r
- generic(\r
- SERDES_NUM : integer range 0 to 3 := 0;\r
- EXT_CLOCK : integer range 0 to 1 := c_NO;\r
- USE_200_MHZ : integer range 0 to 1 := c_NO\r
- );\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_med_ecp_sfp_4 is\r
- generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO\r
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
- SD_LOS_IN : in std_logic_vector(3 downto 0);\r
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component trb_net16_med_ecp_sfp_4_gbe is\r
- generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO\r
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
- SD_LOS_IN : in std_logic_vector(3 downto 0);\r
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_med_ecp3_sfp is\r
-generic(\r
- SERDES_NUM : integer range 0 to 3 := 0;\r
- EXT_CLOCK : integer range 0 to 1 := c_NO;\r
- USE_200_MHZ: integer range 0 to 1 := c_YES;\r
- USE_125_MHZ: integer range 0 to 1 := c_NO;\r
- USE_CTC : integer range 0 to 1 := c_YES;\r
- USE_SLAVE : integer range 0 to 1 := c_NO\r
- );\r
-port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- REFCLK2CORE_OUT : out std_logic;\r
- CLK_RX_HALF_OUT : out std_logic;\r
- CLK_RX_FULL_OUT : out std_logic;\r
- \r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic;\r
- SD_RXD_N_IN : in std_logic;\r
- SD_TXD_P_OUT : out std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic; -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (63 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-component trb_net16_med_ecp3_sfp_4_onboard is\r
-generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO;\r
- FREQUENCY : integer range 125 to 200 := 200\r
+ component ipu_dummy is\r
+ port(CLK_IN : in std_logic; -- 100MHz local clock\r
+ CLEAR_IN : in std_logic;\r
+ RESET_IN : in std_logic; -- synchronous reset\r
+ -- Slow control signals\r
+ MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value\r
+ MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value\r
+ CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control\r
+ -- IPU channel connections\r
+ IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag\r
+ IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information\r
+ IPU_START_READOUT_IN : in std_logic; -- gimme data!\r
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR\r
+ IPU_DATAREADY_OUT : out std_logic; -- data is valid\r
+ IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM\r
+ IPU_READ_IN : in std_logic; -- read strobe, low every second cycle\r
+ IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?)\r
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern\r
+ -- DHDR buffer\r
+ LVL1_FIFO_RD_OUT : out std_logic;\r
+ LVL1_FIFO_EMPTY_IN : in std_logic;\r
+ LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ -- Debug signals\r
+ DBG_BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DBG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_lsm_sfp is\r
+ generic(\r
+ CHECK_FOR_CV : integer := c_YES;\r
+ HIGHSPEED_STARTUP : integer := c_NO\r
+ );\r
+ port(\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available\r
+ -- status signals\r
+ SFP_MISSING_IN : in std_logic; -- SFP Present ('0' = no SFP mounted, '1' = SFP in place)\r
+ SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_LINK_OK_IN : in std_logic; -- SerDes Link OK ('0' = not linked, '1' link established)\r
+ SD_LOS_IN : in std_logic; -- SerDes Loss Of Signal ('0' = OK, '1' = signal lost)\r
+ SD_TXCLK_BAD_IN : in std_logic; -- SerDes Tx Clock locked ('0' = locked, '1' = not locked)\r
+ SD_RXCLK_BAD_IN : in std_logic; -- SerDes Rx Clock locked ('0' = locked, '1' = not locked)\r
+ SD_RETRY_IN : in std_logic; -- '0' = handle byte swapping in logic, '1' = simply restart link and hope\r
+ SD_ALIGNMENT_IN : in std_logic_vector(1 downto 0); -- SerDes Byte alignment ("10" = swapped, "01" = correct)\r
+ SD_CV_IN : in std_logic_vector(1 downto 0); -- SerDes Code Violation ("00" = OK, everything else = BAD)\r
+ -- control signals\r
+ FULL_RESET_OUT : out std_logic; -- full reset AKA quad_reset\r
+ LANE_RESET_OUT : out std_logic; -- partial reset AKA lane_reset\r
+ TX_ALLOW_OUT : out std_logic; -- allow normal transmit operation\r
+ RX_ALLOW_OUT : out std_logic; -- allow normal receive operation\r
+ SWAP_BYTES_OUT : out std_logic; -- bytes need swapping ('0' = correct order, '1' = swapped order)\r
+ -- debug signals\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_8_SDR_OS is\r
+ generic(\r
+ TRANSMISSION_CLOCK_DIV : integer range 1 to 10 := 1\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+\r
+ -- Media direction port\r
+ TX_DATA_OUT : out std_logic_vector (7 downto 0);\r
+ TX_CLK_OUT : out std_logic;\r
+ TX_CTRL_OUT : out std_logic_vector (1 downto 0);\r
+ RX_DATA_IN : in std_logic_vector (7 downto 0);\r
+ RX_CLK_IN : in std_logic;\r
+ RX_CTRL_IN : in std_logic_vector (1 downto 0);\r
+\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ CLEAR : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ --SFP Connection\r
+ TXP : out std_logic;\r
+ TXN : out std_logic;\r
+ RXP : in std_logic;\r
+ RXN : in std_logic;\r
+ SD : in std_logic;\r
+\r
+ -- Status and control port\r
+ RX_CLOCK_OUT : out std_logic;\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot_4 is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ --SFP Connection\r
+ TXP : out std_logic_vector(3 downto 0);\r
+ TXN : out std_logic_vector(3 downto 0);\r
+ RXP : in std_logic_vector(3 downto 0);\r
+ RXN : in std_logic_vector(3 downto 0);\r
+ SD : in std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (63 downto 0);\r
+ CTRL_OP : in std_logic_vector (63 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(127 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (255 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_fot_4_ctc is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_25 : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ CLEAR : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+\r
+ --SFP Connection\r
+ TXP : out std_logic_vector(3 downto 0);\r
+ TXN : out std_logic_vector(3 downto 0);\r
+ RXP : in std_logic_vector(3 downto 0);\r
+ RXN : in std_logic_vector(3 downto 0);\r
+ SD : in std_logic_vector(3 downto 0);\r
+\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (63 downto 0);\r
+ CTRL_OP : in std_logic_vector (63 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector (511 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (255 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0;\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_gbe is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0;\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO;\r
+ USE_200_MHZ : integer range 0 to 1 := c_NO\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_4 is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_med_ecp_sfp_4_gbe is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0);\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_med_ecp3_sfp is\r
+ generic(\r
+ SERDES_NUM : integer range 0 to 3 := 0;\r
+ EXT_CLOCK : integer range 0 to 1 := c_NO;\r
+ USE_200_MHZ : integer range 0 to 1 := c_YES;\r
+ USE_125_MHZ : integer range 0 to 1 := c_NO;\r
+ USE_CTC : integer range 0 to 1 := c_YES;\r
+ USE_SLAVE : integer range 0 to 1 := c_NO\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ CLK_RX_HALF_OUT : out std_logic;\r
+ CLK_RX_FULL_OUT : out std_logic;\r
+\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic; -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+ component trb_net16_med_ecp3_sfp_4_onboard is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO;\r
+ FREQUENCY : integer range 125 to 200 := 200\r
-- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
-port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0';\r
- SCI_ACK : out std_logic := '0';\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
- STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_med_ecp3_sfp_4 is\r
- generic(\r
- REVERSE_ORDER : integer range 0 to 1 := c_NO;\r
- FREQUENCY : integer range 125 to 200 := 200 --200 or 125\r
- -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
- );\r
- port(\r
- CLK : in std_logic; -- SerDes clock\r
- SYSCLK : in std_logic; -- fabric clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
- CLK_EN : in std_logic;\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
- MED_READ_OUT : out std_logic_vector(3 downto 0);\r
- MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
- MED_READ_IN : in std_logic_vector(3 downto 0);\r
- REFCLK2CORE_OUT : out std_logic;\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
- SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
- SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
- SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
- SD_REFCLK_P_IN : in std_logic;\r
- SD_REFCLK_N_IN : in std_logic;\r
- SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable\r
- --Control Interface\r
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
- SCI_READ : in std_logic := '0';\r
- SCI_WRITE : in std_logic := '0'; \r
- SCI_ACK : out std_logic := '0';\r
- -- Status and control port\r
- STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
- CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
- STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);\r
- CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-component trb_net16_med_16_CC is\r
-port(\r
- CLK : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
-\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
-\r
- DATA_OUT : out std_logic_vector(15 downto 0);\r
- DATA_VALID_OUT : out std_logic;\r
- DATA_CTRL_OUT : out std_logic;\r
- DATA_IN : in std_logic_vector(15 downto 0);\r
- DATA_VALID_IN : in std_logic;\r
- DATA_CTRL_IN : in std_logic;\r
-\r
- STAT_OP : out std_logic_vector(15 downto 0);\r
- CTRL_OP : in std_logic_vector(15 downto 0);\r
- STAT_DEBUG : out std_logic_vector(63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_med_16_IC is\r
-generic(\r
-DATA_CLK_OUT_PHASE : std_logic := '1'\r
-);\r
-port(\r
- CLK : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
-\r
- --Internal Connection\r
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
-\r
- DATA_OUT : out std_logic_vector(15 downto 0);\r
- DATA_VALID_OUT : out std_logic;\r
- DATA_CTRL_OUT : out std_logic;\r
- DATA_CLK_OUT : out std_logic;\r
- DATA_IN : in std_logic_vector(15 downto 0);\r
- DATA_VALID_IN : in std_logic;\r
- DATA_CTRL_IN : in std_logic;\r
- DATA_CLK_IN : in std_logic;\r
-\r
- STAT_OP : out std_logic_vector(15 downto 0);\r
- CTRL_OP : in std_logic_vector(15 downto 0);\r
- STAT_DEBUG : out std_logic_vector(63 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_med_tlk is\r
-port (\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- TLK_CLK : in std_logic;\r
- TLK_ENABLE : out std_logic;\r
- TLK_LCKREFN : out std_logic;\r
- TLK_LOOPEN : out std_logic;\r
- TLK_PRBSEN : out std_logic;\r
- TLK_RXD : in std_logic_vector(15 downto 0);\r
- TLK_RX_CLK : in std_logic;\r
- TLK_RX_DV : in std_logic;\r
- TLK_RX_ER : in std_logic;\r
- TLK_TXD : out std_logic_vector(15 downto 0);\r
- TLK_TX_EN : out std_logic;\r
- TLK_TX_ER : out std_logic;\r
- SFP_LOS : in std_logic;\r
- SFP_TX_DIS : out std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_READ_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_OUT : out std_logic;\r
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- STAT : out std_logic_vector (63 downto 0);\r
- STAT_MONITOR : out std_logic_vector ( 100 downto 0);\r
- STAT_OP : out std_logic_vector (15 downto 0);\r
- CTRL_OP : in std_logic_vector (15 downto 0)\r
- --connect STAT(0) to LED\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net_onewire is\r
-generic(\r
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;\r
- PARASITIC_MODE : integer range 0 to 1 := c_NO;\r
- CLK_PERIOD : integer := 10 --clk period in ns\r
- );\r
-port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- READOUT_ENABLE_IN : in std_logic := '1';\r
- --connection to 1-wire interface\r
- ONEWIRE : inout std_logic;\r
- MONITOR_OUT : out std_logic;\r
- --connection to id ram, according to memory map in TrbNetRegIO\r
- DATA_OUT : out std_logic_vector(15 downto 0);\r
- ADDR_OUT : out std_logic_vector(2 downto 0);\r
- WRITE_OUT: out std_logic;\r
- TEMP_OUT : out std_logic_vector(11 downto 0);\r
- ID_OUT : out std_logic_vector(63 downto 0);\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net_onewire_listener is\r
-port(\r
- CLK : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
- MONITOR_IN : in std_logic;\r
- DATA_OUT : out std_logic_vector(15 downto 0);\r
- ADDR_OUT : out std_logic_vector(2 downto 0);\r
- WRITE_OUT: out std_logic;\r
- TEMP_OUT : out std_logic_vector(11 downto 0);\r
- ID_OUT : out std_logic_vector(63 downto 0);\r
- STAT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_obuf is\r
-generic (\r
- DATA_COUNT_WIDTH : integer := 5;\r
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
- USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
- SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_OUT: out std_logic;\r
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN: in std_logic;\r
- -- Internal direction port\r
- INT_DATAREADY_IN: in std_logic;\r
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_OUT: out std_logic;\r
- -- Status and control port\r
- STAT_BUFFER: out std_logic_vector (31 downto 0);\r
- CTRL_BUFFER: in std_logic_vector (31 downto 0);\r
- CTRL_SETTINGS : in std_logic_vector (15 downto 0);\r
- STAT_DEBUG : out std_logic_vector (31 downto 0);\r
- TIMER_TICKS_IN : in std_logic_vector (1 downto 0)\r
- );\r
-end component;\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_med_ecp3_sfp_4 is\r
+ generic(\r
+ REVERSE_ORDER : integer range 0 to 1 := c_NO;\r
+ FREQUENCY : integer range 125 to 200 := 200 --200 or 125\r
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"\r
+ );\r
+ port(\r
+ CLK : in std_logic; -- SerDes clock\r
+ SYSCLK : in std_logic; -- fabric clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ CLK_EN : in std_logic;\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);\r
+ MED_READ_OUT : out std_logic_vector(3 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);\r
+ MED_READ_IN : in std_logic_vector(3 downto 0);\r
+ REFCLK2CORE_OUT : out std_logic;\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic_vector(3 downto 0);\r
+ SD_RXD_N_IN : in std_logic_vector(3 downto 0);\r
+ SD_TXD_P_OUT : out std_logic_vector(3 downto 0);\r
+ SD_TXD_N_OUT : out std_logic_vector(3 downto 0);\r
+ SD_REFCLK_P_IN : in std_logic;\r
+ SD_REFCLK_N_IN : in std_logic;\r
+ SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (4*16-1 downto 0);\r
+ CTRL_OP : in std_logic_vector (4*16-1 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (64*4-1 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net16_med_16_CC is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_VALID_OUT : out std_logic;\r
+ DATA_CTRL_OUT : out std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ DATA_VALID_IN : in std_logic;\r
+ DATA_CTRL_IN : in std_logic;\r
+\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_16_IC is\r
+ generic(\r
+ DATA_CLK_OUT_PHASE : std_logic := '1'\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+\r
+ --Internal Connection\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ DATA_VALID_OUT : out std_logic;\r
+ DATA_CTRL_OUT : out std_logic;\r
+ DATA_CLK_OUT : out std_logic;\r
+ DATA_IN : in std_logic_vector(15 downto 0);\r
+ DATA_VALID_IN : in std_logic;\r
+ DATA_CTRL_IN : in std_logic;\r
+ DATA_CLK_IN : in std_logic;\r
+\r
+ STAT_OP : out std_logic_vector(15 downto 0);\r
+ CTRL_OP : in std_logic_vector(15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector(63 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_med_tlk is\r
+ port (\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ TLK_CLK : in std_logic;\r
+ TLK_ENABLE : out std_logic;\r
+ TLK_LCKREFN : out std_logic;\r
+ TLK_LOOPEN : out std_logic;\r
+ TLK_PRBSEN : out std_logic;\r
+ TLK_RXD : in std_logic_vector(15 downto 0);\r
+ TLK_RX_CLK : in std_logic;\r
+ TLK_RX_DV : in std_logic;\r
+ TLK_RX_ER : in std_logic;\r
+ TLK_TXD : out std_logic_vector(15 downto 0);\r
+ TLK_TX_EN : out std_logic;\r
+ TLK_TX_ER : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_TX_DIS : out std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ STAT : out std_logic_vector (63 downto 0);\r
+ STAT_MONITOR : out std_logic_vector (100 downto 0);\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0)\r
+ --connect STAT(0) to LED\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
\r
+ component trb_net_onewire is\r
+ generic(\r
+ USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;\r
+ PARASITIC_MODE : integer range 0 to 1 := c_NO;\r
+ CLK_PERIOD : integer := 10 --clk period in ns\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ READOUT_ENABLE_IN : in std_logic := '1';\r
+ --connection to 1-wire interface\r
+ ONEWIRE : inout std_logic;\r
+ MONITOR_OUT : out std_logic;\r
+ --connection to id ram, according to memory map in TrbNetRegIO\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(2 downto 0);\r
+ WRITE_OUT : out std_logic;\r
+ TEMP_OUT : out std_logic_vector(11 downto 0);\r
+ ID_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_onewire_listener is\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ MONITOR_IN : in std_logic;\r
+ DATA_OUT : out std_logic_vector(15 downto 0);\r
+ ADDR_OUT : out std_logic_vector(2 downto 0);\r
+ WRITE_OUT : out std_logic;\r
+ TEMP_OUT : out std_logic_vector(11 downto 0);\r
+ ID_OUT : out std_logic_vector(63 downto 0);\r
+ STAT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_obuf is\r
+ generic (\r
+ DATA_COUNT_WIDTH : integer := 5;\r
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;\r
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;\r
+ SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ -- Internal direction port\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+ -- Status and control port\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_BUFFER : in std_logic_vector (31 downto 0);\r
+ CTRL_SETTINGS : in std_logic_vector (15 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (31 downto 0);\r
+ TIMER_TICKS_IN : in std_logic_vector (1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_obuf_nodata is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_IN : in std_logic;\r
+ --STAT\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0);\r
+ CTRL_BUFFER : in std_logic_vector (31 downto 0);\r
+ STAT_DEBUG : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
\r
\r
\r
\r
+ component pll_in100_out100 is\r
+ port (\r
+ CLK : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component pll_in100_out20 is\r
+ port (\r
+ CLK : in std_logic;\r
+ CLKOP : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll_in200_out100 is\r
+ port (\r
+ RESET : in std_logic := '0';\r
+ CLK : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOK : out std_logic;\r
+ CLKOS : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll_in100_out25 is\r
+ port (\r
+ CLK : in std_logic;\r
+ CLKOP : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component pll25 is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLKOP : out std_logic;\r
+ CLKOK : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
\r
\r
\r
-component trb_net16_obuf_nodata is\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_OUT: out std_logic;\r
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_IN: in std_logic;\r
- --STAT\r
- STAT_BUFFER: out std_logic_vector (31 downto 0);\r
- CTRL_BUFFER: in std_logic_vector (31 downto 0);\r
- STAT_DEBUG : out std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
+ component pll_in25_out100 is\r
+ port (\r
+ CLK : in std_logic;\r
+ CLKOP : out std_logic;\r
+ LOCK : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
\r
\r
\r
\r
-component pll_in100_out100 is\r
-port (\r
- CLK: in std_logic;\r
- CLKOP: out std_logic;\r
- CLKOS: out std_logic;\r
- LOCK: out std_logic\r
- );\r
-end component;\r
+ component trb_net_pattern_gen is\r
+ generic (\r
+ WIDTH : integer := 6\r
+ );\r
+ port(\r
+ INPUT_IN : in std_logic_vector (WIDTH-1 downto 0);\r
+ RESULT_OUT : out std_logic_vector (2**WIDTH-1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component priority_arbiter is\r
+ generic(\r
+ INPUT_WIDTH : integer := 8\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ ENABLE : in std_logic;\r
+ INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0);\r
+ OUTPUT_VEC : out std_logic_vector(INPUT_WIDTH-1 downto 0);\r
+ OUTPUT_NUM : out integer range 0 to INPUT_WIDTH-1\r
+ );\r
+ end component;\r
\r
\r
\r
-component pll_in100_out20 is\r
-port (\r
- CLK: in std_logic;\r
- CLKOP: out std_logic;\r
- LOCK: out std_logic\r
- );\r
-end component;\r
+ component trb_net_priority_arbiter is\r
+ generic (\r
+ WIDTH : integer := 2\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ INPUT_IN : in std_logic_vector (WIDTH-1 downto 0);\r
+ RESULT_OUT : out std_logic_vector (WIDTH-1 downto 0);\r
+ ENABLE : in std_logic;\r
+ CTRL : in std_logic_vector (9 downto 0)\r
+ );\r
+ end component;\r
\r
\r
-component pll_in200_out100 is\r
-port (\r
- RESET : in std_logic := '0';\r
- CLK: in std_logic;\r
- CLKOP: out std_logic;\r
- CLKOK: out std_logic;\r
- CLKOS: out std_logic;\r
- LOCK: out std_logic\r
- );\r
-end component;\r
\r
+ component pulse_sync is\r
+ port(\r
+ CLK_A_IN : in std_logic;\r
+ RESET_A_IN : in std_logic;\r
+ PULSE_A_IN : in std_logic;\r
+ CLK_B_IN : in std_logic;\r
+ RESET_B_IN : in std_logic;\r
+ PULSE_B_OUT : out std_logic\r
+ );\r
+ end component;\r
\r
-component pll_in100_out25 is\r
-port (\r
- CLK: in std_logic;\r
- CLKOP: out std_logic;\r
- LOCK: out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component pll25 is\r
-port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLKOP : out std_logic;\r
- CLKOK : out std_logic;\r
- LOCK : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-component pll_in25_out100 is\r
-port (\r
- CLK: in std_logic;\r
- CLKOP: out std_logic;\r
- LOCK: out std_logic\r
- );\r
-end component;\r
\r
\r
+ component ram_dp is\r
+ generic(\r
+ depth : integer := 3;\r
+ width : integer := 16\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ wr1 : in std_logic;\r
+ a1 : in std_logic_vector(depth-1 downto 0);\r
+ dout1 : out std_logic_vector(width-1 downto 0);\r
+ din1 : in std_logic_vector(width-1 downto 0);\r
+ a2 : in std_logic_vector(depth-1 downto 0);\r
+ dout2 : out std_logic_vector(width-1 downto 0)\r
+ );\r
+ end component;\r
\r
\r
\r
\r
-component trb_net_pattern_gen is\r
-generic (\r
- WIDTH : integer := 6\r
- );\r
-port(\r
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
- RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component priority_arbiter is\r
- generic(\r
- INPUT_WIDTH : integer := 8\r
- );\r
- port(\r
- CLK : in std_logic;\r
- ENABLE : in std_logic;\r
- INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0);\r
- OUTPUT_VEC : out std_logic_vector(INPUT_WIDTH-1 downto 0);\r
- OUTPUT_NUM : out integer range 0 to INPUT_WIDTH-1\r
- );\r
-end component;\r
-\r
-\r
-\r
-component trb_net_priority_arbiter is\r
-generic (\r
- WIDTH : integer := 2\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
- RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0);\r
- ENABLE : in std_logic;\r
- CTRL: in STD_LOGIC_VECTOR (9 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component pulse_sync is\r
-port(\r
- CLK_A_IN : in std_logic;\r
- RESET_A_IN : in std_logic;\r
- PULSE_A_IN : in std_logic;\r
- CLK_B_IN : in std_logic;\r
- RESET_B_IN : in std_logic;\r
- PULSE_B_OUT : out std_logic\r
-);\r
-end component;\r
-\r
-\r
-\r
-component ram_dp is\r
-generic(\r
- depth : integer := 3;\r
- width : integer := 16\r
- );\r
-port(\r
- CLK : in std_logic;\r
- wr1 : in std_logic;\r
- a1 : in std_logic_vector(depth-1 downto 0);\r
- dout1 : out std_logic_vector(width-1 downto 0);\r
- din1 : in std_logic_vector(width-1 downto 0);\r
- a2 : in std_logic_vector(depth-1 downto 0);\r
- dout2 : out std_logic_vector(width-1 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component ram_dp_rw\r
-generic(\r
- depth : integer := 3;\r
- width : integer := 16\r
- );\r
-port(\r
- CLK : in std_logic;\r
- wr1 : in std_logic;\r
- a1 : in std_logic_vector(depth-1 downto 0);\r
- din1 : in std_logic_vector(width-1 downto 0);\r
- a2 : in std_logic_vector(depth-1 downto 0);\r
- dout2 : out std_logic_vector(width-1 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_regIO is\r
-generic (\r
- NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers\r
- NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
- --standard values for output registers\r
- INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
- --set to 0 for unused ctrl registers to save resources\r
- USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
- --set to 0 for each unused bit in a register\r
- USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
- USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
- CLOCK_FREQ : integer range 1 to 200 := 100 --MHz\r
- );\r
-port(\r
+ component ram_dp_rw\r
+ generic(\r
+ depth : integer := 3;\r
+ width : integer := 16\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ wr1 : in std_logic;\r
+ a1 : in std_logic_vector(depth-1 downto 0);\r
+ din1 : in std_logic_vector(width-1 downto 0);\r
+ a2 : in std_logic_vector(depth-1 downto 0);\r
+ dout2 : out std_logic_vector(width-1 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_regIO is\r
+ generic (\r
+ NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers\r
+ NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers\r
+ --standard values for output registers\r
+ INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');\r
+ --set to 0 for unused ctrl registers to save resources\r
+ USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1');\r
+ --set to 0 for each unused bit in a register\r
+ USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');\r
+ USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port\r
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";\r
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";\r
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";\r
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";\r
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";\r
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";\r
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";\r
+ CLOCK_FREQ : integer range 1 to 200 := 100 --MHz\r
+ );\r
+ port(\r
-- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
-- Port to API\r
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_DATAREADY_OUT : out std_logic;\r
- API_READ_IN : in std_logic;\r
- API_SHORT_TRANSFER_OUT : out std_logic;\r
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
- API_SEND_OUT : out std_logic;\r
- -- Receiver port\r
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- API_TYP_IN : in std_logic_vector (2 downto 0);\r
- API_DATAREADY_IN : in std_logic;\r
- API_READ_OUT : out std_logic;\r
- -- APL Control port\r
- API_RUN_IN : in std_logic;\r
- API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
-\r
- --Port to write Unique ID (-> 1-wire)\r
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);\r
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
- IDRAM_WR_IN : in std_logic;\r
-\r
- --Informations\r
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
- TRIGGER_MONITOR : in std_logic;\r
- GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds\r
- LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
- TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
- TIMER_US_TICK : out std_logic; --1 tick every microsecond\r
- TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds\r
+ API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_DATAREADY_OUT : out std_logic;\r
+ API_READ_IN : in std_logic;\r
+ API_SHORT_TRANSFER_OUT : out std_logic;\r
+ API_DTYPE_OUT : out std_logic_vector (3 downto 0);\r
+ API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);\r
+ API_SEND_OUT : out std_logic;\r
+ -- Receiver port\r
+ API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ API_TYP_IN : in std_logic_vector (2 downto 0);\r
+ API_DATAREADY_IN : in std_logic;\r
+ API_READ_OUT : out std_logic;\r
+ -- APL Control port\r
+ API_RUN_IN : in std_logic;\r
+ API_SEQNR_IN : in std_logic_vector (7 downto 0);\r
+\r
+ --Port to write Unique ID (-> 1-wire)\r
+ IDRAM_DATA_IN : in std_logic_vector(15 downto 0);\r
+ IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);\r
+ IDRAM_WR_IN : in std_logic;\r
+\r
+ --Informations\r
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);\r
+ TRIGGER_MONITOR : in std_logic;\r
+ GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds\r
+ LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency\r
+ TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger\r
+ TIMER_US_TICK : out std_logic; --1 tick every microsecond\r
+ TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds\r
\r
--Common Register in / out\r
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);\r
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);\r
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0);\r
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0);\r
--Custom Register in / out\r
- REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);\r
- REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);\r
- COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);\r
- COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);\r
- STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);\r
- CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);\r
+ REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);\r
+ REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);\r
+ COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0);\r
+ COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0);\r
+ STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);\r
+ CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);\r
--Internal Data Port\r
- DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
- DAT_READ_ENABLE_OUT : out std_logic;\r
- DAT_WRITE_ENABLE_OUT: out std_logic;\r
- DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
- DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
- DAT_DATAREADY_IN : in std_logic;\r
- DAT_NO_MORE_DATA_IN : in std_logic;\r
- DAT_WRITE_ACK_IN : in std_logic;\r
- DAT_UNKNOWN_ADDR_IN : in std_logic;\r
- DAT_TIMEOUT_OUT : out std_logic;\r
+ DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
+ DAT_READ_ENABLE_OUT : out std_logic;\r
+ DAT_WRITE_ENABLE_OUT : out std_logic;\r
+ DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
+ DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0);\r
+ DAT_DATAREADY_IN : in std_logic;\r
+ DAT_NO_MORE_DATA_IN : in std_logic;\r
+ DAT_WRITE_ACK_IN : in std_logic;\r
+ DAT_UNKNOWN_ADDR_IN : in std_logic;\r
+ DAT_TIMEOUT_OUT : out std_logic;\r
\r
--Additional write access to ctrl registers\r
- STAT : out std_logic_vector(31 downto 0);\r
- STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_regio_bus_handler is\r
-generic(\r
- PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;\r
- PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));\r
- PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)\r
- );\r
-port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
- DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- DAT_READ_ENABLE_IN : in std_logic; -- read pulse\r
- DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- DAT_TIMEOUT_IN : in std_logic; -- access timed out\r
- DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- DAT_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
-\r
- BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);\r
- BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
- BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
- BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
-\r
- BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);\r
- BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
- BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
- BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
- BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
-\r
- STAT_DEBUG : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net_reset_handler is\r
-generic(\r
- RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
- );\r
-port(\r
- CLEAR_IN : in std_logic; -- reset input (high active, async)\r
- CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
- CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
- SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
- PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
- RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
- TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
- CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
- RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component rom_16x8 is\r
-generic(\r
- INIT0 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT1 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT2 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT3 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT4 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT5 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT6 : std_logic_vector(15 downto 0) := x"0000";\r
- INIT7 : std_logic_vector(15 downto 0) := x"0000"\r
- );\r
-port(\r
- CLK : in std_logic;\r
- a : in std_logic_vector(2 downto 0);\r
- dout : out std_logic_vector(15 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component trb_net16_rx_control is\r
-port(\r
- RESET_IN : in std_logic;\r
- QUAD_RST_IN : in std_logic;\r
- -- raw data from SerDes receive path\r
- CLK_IN : in std_logic;\r
- RX_DATA_IN : in std_logic_vector(7 downto 0);\r
- RX_K_IN : in std_logic;\r
- RX_CV_IN : in std_logic;\r
- RX_DISP_ERR_IN : in std_logic;\r
- RX_ALLOW_IN : in std_logic;\r
- -- media interface\r
- SYSCLK_IN : in std_logic; -- 100MHz master clock\r
- MED_DATA_OUT : out std_logic_vector(15 downto 0);\r
- MED_DATAREADY_OUT : out std_logic;\r
- MED_READ_IN : in std_logic;\r
- MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);\r
- -- request retransmission in case of error while receiving\r
- REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse\r
- REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0);\r
- -- command decoding\r
- START_RETRANSMIT_OUT : out std_logic;\r
- START_POSITION_OUT : out std_logic_vector( 7 downto 0);\r
- -- reset handling\r
- SEND_RESET_WORDS_OUT : out std_logic;\r
- MAKE_TRBNET_RESET_OUT : out std_logic;\r
- -- Status signals\r
- PACKET_TIMEOUT_OUT : out std_logic;\r
- ENABLE_CORRECTION_IN : in std_logic;\r
- -- Debugging\r
- DEBUG_OUT : out std_logic_vector(31 downto 0);\r
- STAT_REG_OUT : out std_logic_vector(95 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_sbuf is\r
-generic (\r
- VERSION : integer := 0\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- port to combinatorial logic\r
- COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word\r
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
- COMB_READ_IN : in STD_LOGIC; --comb logic IS reading\r
- COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);\r
- -- Port to synchronous output.\r
- SYN_DATAREADY_OUT : out STD_LOGIC;\r
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);\r
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);\r
- SYN_READ_IN : in STD_LOGIC;\r
- -- Status and control port\r
- DEBUG_OUT : out std_logic_vector(15 downto 0);\r
- STAT_BUFFER : out STD_LOGIC\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net_sbuf is\r
-generic (\r
- DATA_WIDTH : integer := 18;\r
- VERSION: integer := std_SBUF_VERSION);\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- port to combinatorial logic\r
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_DATAREADY_OUT: out STD_LOGIC;\r
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_READ_IN: in STD_LOGIC;\r
- DEBUG_OUT : out std_logic_vector(15 downto 0);\r
- STAT_BUFFER: out STD_LOGIC\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_sbuf2 is\r
-generic (\r
- DATA_WIDTH : integer := 18\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- port to combinatorial logic\r
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_DATAREADY_OUT: out STD_LOGIC;\r
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_READ_IN: in STD_LOGIC;\r
- STAT_BUFFER: out STD_LOGIC\r
- );\r
-end component;\r
-\r
-component trb_net_sbuf3 is\r
-generic (\r
- DATA_WIDTH : integer := 18\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- port to combinatorial logic\r
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_DATAREADY_OUT: out STD_LOGIC;\r
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_READ_IN: in STD_LOGIC;\r
- STAT_BUFFER: out STD_LOGIC\r
- );\r
-end component;\r
-\r
-component trb_net_sbuf4 is\r
-generic (\r
- DATA_WIDTH : integer := 18\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- port to combinatorial logic\r
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word\r
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle\r
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading\r
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_DATAREADY_OUT: out STD_LOGIC;\r
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);\r
- SYN_READ_IN: in STD_LOGIC;\r
- STAT_BUFFER: out STD_LOGIC\r
- );\r
-end component;\r
-\r
-component trb_net_sbuf5 is\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- input\r
- COMB_DATAREADY_IN : in std_logic;\r
- COMB_next_READ_OUT : out std_logic;\r
- COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
- -- output\r
- SYN_DATAREADY_OUT : out std_logic;\r
- SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word\r
- SYN_READ_IN : in std_logic;\r
- -- Status and control port\r
- DEBUG : out std_logic_vector(7 downto 0);\r
- DEBUG_BSM : out std_logic_vector(3 downto 0);\r
- DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
- STAT_BUFFER : out std_logic\r
-);\r
-end component;\r
-\r
-component trb_net_sbuf6 is\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- input\r
- COMB_DATAREADY_IN : in std_logic;\r
- COMB_next_READ_OUT : out std_logic;\r
- COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
- -- output\r
- SYN_DATAREADY_OUT : out std_logic;\r
- SYN_DATA_OUT : out std_logic_vector(18 downto 0);\r
- SYN_READ_IN : in std_logic;\r
- -- Status and control port\r
- DEBUG : out std_logic_vector(7 downto 0);\r
- DEBUG_BSM : out std_logic_vector(3 downto 0);\r
- DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
- STAT_BUFFER : out std_logic\r
-);\r
-end component;\r
-\r
-component slv_mac_memory is\r
-port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- BUSY_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- MEM_CLK_IN : in std_logic;\r
- MEM_ADDR_IN : in std_logic_vector(7 downto 0);\r
- MEM_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
-end component;\r
-\r
-\r
-\r
-component slv_register is\r
-generic(\r
- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
- );\r
-port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUSY_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
-end component;\r
-\r
-\r
-\r
-component spi_databus_memory is\r
-port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
- BUS_READ_IN : in std_logic;\r
- BUS_WRITE_IN : in std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- state machine connections\r
- BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
- BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_WE_IN : in std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
-);\r
-end component;\r
-\r
-\r
-component spi_dpram_32_to_8 is\r
-port (\r
- DataInA: in std_logic_vector(31 downto 0);\r
- DataInB: in std_logic_vector(7 downto 0);\r
- AddressA: in std_logic_vector(5 downto 0);\r
- AddressB: in std_logic_vector(7 downto 0);\r
- ClockA: in std_logic;\r
- ClockB: in std_logic;\r
- ClockEnA: in std_logic;\r
- ClockEnB: in std_logic;\r
- WrA: in std_logic;\r
- WrB: in std_logic;\r
- ResetA: in std_logic;\r
- ResetB: in std_logic;\r
- QA: out std_logic_vector(31 downto 0);\r
- QB: out std_logic_vector(7 downto 0));\r
-end component;\r
-\r
-\r
-component spi_slim is\r
-port(\r
- SYSCLK : in std_logic; -- 100MHz sysclock\r
- RESET : in std_logic; -- synchronous reset\r
- -- Command interface\r
- START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
- ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
- ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
- ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
- MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
- TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
- TX_RD_OUT : out std_logic;\r
- RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
- RX_WR_OUT : out std_logic;\r
- TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
- -- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
-);\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component spi_master is\r
-port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- BUS_READ_IN : in std_logic;\r
- BUS_WRITE_IN : in std_logic;\r
- BUS_BUSY_OUT : out std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
- BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- -- BRAM for read/write data\r
- BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WE_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
-);\r
-end component;\r
-\r
-\r
-\r
-component spi_ltc2600 is\r
- port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- BUS_READ_IN : in std_logic;\r
- BUS_WRITE_IN : in std_logic;\r
- BUS_BUSY_OUT : out std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
- BUS_ADDR_IN : in std_logic_vector(4 downto 0);\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic_vector(15 downto 0);\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component signal_sync is\r
-generic(\r
- WIDTH : integer := 1; --\r
- DEPTH : integer := 3\r
- );\r
-port(\r
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register\r
- CLK0 : in std_logic; --clock for first FF\r
- CLK1 : in std_logic; --Clock for other FF\r
- D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input\r
- D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_term is\r
-generic (\r
- USE_APL_PORT : integer range 0 to 1 := c_YES;\r
- --even when 0, ERROR_PACKET_IN is used for automatic replys\r
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
- --if secure_mode is not used, apl must provide error pattern and dtype until\r
- --next trigger comes in. In secure mode these need to be available while relase_trg is high\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- INT_DATAREADY_OUT : out std_logic;\r
- INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
- INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_IN : in std_logic;\r
-\r
- INT_DATAREADY_IN : in std_logic;\r
- INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
- INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_OUT : out std_logic;\r
- APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_term_buf is\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- MED_INIT_DATAREADY_OUT : out std_logic;\r
- MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
- MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_INIT_READ_IN : in std_logic;\r
- MED_REPLY_DATAREADY_OUT : out std_logic;\r
- MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
- MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_REPLY_READ_IN : in std_logic;\r
- MED_DATAREADY_IN : in std_logic;\r
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-\r
-component trb_net16_term_ibuf is\r
-generic(\r
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE;\r
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- -- Media direction port\r
- MED_DATAREADY_IN: in std_logic;\r
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- MED_READ_OUT: out std_logic;\r
- MED_ERROR_IN: in std_logic_vector (2 downto 0);\r
- -- Internal direction port\r
- INT_DATAREADY_OUT: out std_logic;\r
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
- INT_READ_IN: in std_logic;\r
- INT_ERROR_OUT: out std_logic_vector (2 downto 0);\r
- -- Status and control port\r
- STAT_BUFFER: out std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component trb_net16_trigger is\r
-generic (\r
- USE_TRG_PORT : integer range 0 to 1 := c_YES;\r
- --even when NO, ERROR_PACKET_IN is used for automatic replys\r
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
- --if secure_mode is not used, apl must provide error pattern and dtype until\r
- --next trigger comes in. In secure mode these need to be available while relase_trg is high only\r
- );\r
-port(\r
- -- Misc\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
-\r
- INT_DATAREADY_OUT: out std_logic;\r
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_IN: in std_logic;\r
-\r
- INT_DATAREADY_IN: in std_logic;\r
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
- INT_READ_OUT: out std_logic;\r
-\r
- -- Trigger information output\r
- TRG_TYPE_OUT : out std_logic_vector (3 downto 0);\r
- TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
- TRG_CODE_OUT : out std_logic_vector (7 downto 0);\r
- TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);\r
- TRG_RECEIVED_OUT : out std_logic;\r
- TRG_RELEASE_IN : in std_logic;\r
- TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-component trb_net16_tx_control is\r
-port(\r
- TXCLK_IN : in std_logic;\r
- RXCLK_IN : in std_logic;\r
- SYSCLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
-\r
- TX_DATA_IN : in std_logic_vector(15 downto 0);\r
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
- TX_WRITE_IN : in std_logic;\r
- TX_READ_OUT : out std_logic;\r
-\r
- TX_DATA_OUT : out std_logic_vector( 7 downto 0);\r
- TX_K_OUT : out std_logic;\r
-\r
- REQUEST_RETRANSMIT_IN : in std_logic;\r
- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0);\r
-\r
- START_RETRANSMIT_IN : in std_logic;\r
- START_POSITION_IN : in std_logic_vector( 7 downto 0);\r
-\r
- SEND_LINK_RESET_IN : in std_logic;\r
- TX_ALLOW_IN : in std_logic;\r
-\r
- DEBUG_OUT : out std_logic_vector(31 downto 0);\r
- STAT_REG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-\r
-\r
-component wide_adder_17x16 is\r
-generic(\r
- SIZE : integer := 16;\r
- WORDS: integer := 17 --fixed\r
- );\r
-port(\r
- CLK : in std_logic;\r
- CLK_EN : in std_logic;\r
- RESET : in std_logic;\r
- INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0);\r
- START_IN : in std_logic;\r
- VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0);\r
- RESULT_OUT : out std_logic_vector(SIZE-1 downto 0);\r
- OVERFLOW_OUT : out std_logic;\r
- READY_OUT : out std_logic\r
- );\r
-end component;\r
-\r
-\r
-component trb_net_bridge_etrax_apl is\r
- port(\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- CLK_EN : in std_logic;\r
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
- CPU_READ : in STD_LOGIC;\r
- CPU_WRITE : in STD_LOGIC;\r
- CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0);\r
- CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0);\r
- CPU_DATAREADY_OUT : out std_logic;\r
- CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0);\r
- STAT : out std_logic_vector (31 downto 0);\r
- CTRL : in std_logic_vector (31 downto 0)\r
- );\r
-end component;\r
-\r
-\r
-end package;
\ No newline at end of file
+ STAT : out std_logic_vector(31 downto 0);\r
+ STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_regio_bus_handler is\r
+ generic(\r
+ PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;\r
+ PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));\r
+ PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
+ DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
+ DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
+ DAT_READ_ENABLE_IN : in std_logic; -- read pulse\r
+ DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
+ DAT_TIMEOUT_IN : in std_logic; -- access timed out\r
+ DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
+ DAT_WRITE_ACK_OUT : out std_logic; -- data accepted\r
+ DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
+ DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
+\r
+ BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0);\r
+ BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0);\r
+\r
+ BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0);\r
+ BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+ BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0);\r
+\r
+ STAT_DEBUG : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net_reset_handler is\r
+ generic(\r
+ RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff"\r
+ );\r
+ port(\r
+ CLEAR_IN : in std_logic; -- reset input (high active, async)\r
+ CLEAR_N_IN : in std_logic; -- reset input (low active, async)\r
+ CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async)\r
+ RESET_IN : in std_logic; -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE!\r
+ RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component rom_16x8 is\r
+ generic(\r
+ INIT0 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT1 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT2 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT3 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT4 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT5 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT6 : std_logic_vector(15 downto 0) := x"0000";\r
+ INIT7 : std_logic_vector(15 downto 0) := x"0000"\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ a : in std_logic_vector(2 downto 0);\r
+ dout : out std_logic_vector(15 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_rx_control is\r
+ port(\r
+ RESET_IN : in std_logic;\r
+ QUAD_RST_IN : in std_logic;\r
+ -- raw data from SerDes receive path\r
+ CLK_IN : in std_logic;\r
+ RX_DATA_IN : in std_logic_vector(7 downto 0);\r
+ RX_K_IN : in std_logic;\r
+ RX_CV_IN : in std_logic;\r
+ RX_DISP_ERR_IN : in std_logic;\r
+ RX_ALLOW_IN : in std_logic;\r
+ -- media interface\r
+ SYSCLK_IN : in std_logic; -- 100MHz master clock\r
+ MED_DATA_OUT : out std_logic_vector(15 downto 0);\r
+ MED_DATAREADY_OUT : out std_logic;\r
+ MED_READ_IN : in std_logic;\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);\r
+ -- request retransmission in case of error while receiving\r
+ REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse\r
+ REQUEST_POSITION_OUT : out std_logic_vector(7 downto 0);\r
+ -- command decoding\r
+ START_RETRANSMIT_OUT : out std_logic;\r
+ START_POSITION_OUT : out std_logic_vector(7 downto 0);\r
+ -- reset handling\r
+ SEND_RESET_WORDS_OUT : out std_logic;\r
+ MAKE_TRBNET_RESET_OUT : out std_logic;\r
+ -- Status signals\r
+ PACKET_TIMEOUT_OUT : out std_logic;\r
+ ENABLE_CORRECTION_IN : in std_logic;\r
+ -- Debugging\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(95 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_sbuf is\r
+ generic (\r
+ VERSION : integer := 0\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word\r
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in std_logic; --comb logic IS reading\r
+ COMB_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ COMB_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ -- Port to synchronous output.\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ SYN_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net_sbuf is\r
+ generic (\r
+ DATA_WIDTH : integer := 18;\r
+ VERSION : integer := std_SBUF_VERSION);\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word\r
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in std_logic; --comb logic IS reading\r
+ COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_sbuf2 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word\r
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in std_logic; --comb logic IS reading\r
+ COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf3 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word\r
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in std_logic; --comb logic IS reading\r
+ COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf4 is\r
+ generic (\r
+ DATA_WIDTH : integer := 18\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- port to combinatorial logic\r
+ COMB_DATAREADY_IN : in std_logic; --comb logic provides data word\r
+ COMB_next_READ_OUT : out std_logic; --sbuf can read in NEXT cycle\r
+ COMB_READ_IN : in std_logic; --comb logic IS reading\r
+ COMB_DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf5 is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- input\r
+ COMB_DATAREADY_IN : in std_logic;\r
+ COMB_next_READ_OUT : out std_logic;\r
+ COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
+ -- output\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG : out std_logic_vector(7 downto 0);\r
+ DEBUG_BSM : out std_logic_vector(3 downto 0);\r
+ DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component trb_net_sbuf6 is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- input\r
+ COMB_DATAREADY_IN : in std_logic;\r
+ COMB_next_READ_OUT : out std_logic;\r
+ COMB_DATA_IN : in std_logic_vector(18 downto 0);\r
+ -- output\r
+ SYN_DATAREADY_OUT : out std_logic;\r
+ SYN_DATA_OUT : out std_logic_vector(18 downto 0);\r
+ SYN_READ_IN : in std_logic;\r
+ -- Status and control port\r
+ DEBUG : out std_logic_vector(7 downto 0);\r
+ DEBUG_BSM : out std_logic_vector(3 downto 0);\r
+ DEBUG_WCNT : out std_logic_vector(4 downto 0);\r
+ STAT_BUFFER : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component slv_mac_memory is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ MEM_CLK_IN : in std_logic;\r
+ MEM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ MEM_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component slv_register is\r
+ generic(\r
+ RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ BUSY_IN : in std_logic;\r
+ -- Slave bus\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_BUSY_OUT : out std_logic;\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- I/O to the backend\r
+ REG_DATA_IN : in std_logic_vector(31 downto 0);\r
+ REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component spi_databus_memory is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- state machine connections\r
+ BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WE_IN : in std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+ component spi_dpram_32_to_8 is\r
+ port (\r
+ DataInA : in std_logic_vector(31 downto 0);\r
+ DataInB : in std_logic_vector(7 downto 0);\r
+ AddressA : in std_logic_vector(5 downto 0);\r
+ AddressB : in std_logic_vector(7 downto 0);\r
+ ClockA : in std_logic;\r
+ ClockB : in std_logic;\r
+ ClockEnA : in std_logic;\r
+ ClockEnB : in std_logic;\r
+ WrA : in std_logic;\r
+ WrB : in std_logic;\r
+ ResetA : in std_logic;\r
+ ResetB : in std_logic;\r
+ QA : out std_logic_vector(31 downto 0);\r
+ QB : out std_logic_vector(7 downto 0));\r
+ end component;\r
+\r
+\r
+ component spi_slim is\r
+ port(\r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
+ ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
+ ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
+ MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
+ TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
+ TX_RD_OUT : out std_logic;\r
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
+ RX_WR_OUT : out std_logic;\r
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component spi_master is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_BUSY_OUT : out std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- BRAM for read/write data\r
+ BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component spi_ltc2600 is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_BUSY_OUT : out std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(4 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic_vector(15 downto 0);\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component signal_sync is\r
+ generic(\r
+ WIDTH : integer := 1; --\r
+ DEPTH : integer := 3\r
+ );\r
+ port(\r
+ RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register\r
+ CLK0 : in std_logic; --clock for first FF\r
+ CLK1 : in std_logic; --Clock for other FF\r
+ D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input\r
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term is\r
+ generic (\r
+ USE_APL_PORT : integer range 0 to 1 := c_YES;\r
+ --even when 0, ERROR_PACKET_IN is used for automatic replys\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
+ --if secure_mode is not used, apl must provide error pattern and dtype until\r
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+ APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term_buf is\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ MED_INIT_DATAREADY_OUT : out std_logic;\r
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_INIT_READ_IN : in std_logic;\r
+ MED_REPLY_DATAREADY_OUT : out std_logic;\r
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_REPLY_READ_IN : in std_logic;\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word\r
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+\r
+ component trb_net16_term_ibuf is\r
+ generic(\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE;\r
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ -- Media direction port\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_READ_OUT : out std_logic;\r
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);\r
+ -- Internal direction port\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+ INT_ERROR_OUT : out std_logic_vector (2 downto 0);\r
+ -- Status and control port\r
+ STAT_BUFFER : out std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component trb_net16_trigger is\r
+ generic (\r
+ USE_TRG_PORT : integer range 0 to 1 := c_YES;\r
+ --even when NO, ERROR_PACKET_IN is used for automatic replys\r
+ SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE\r
+ --if secure_mode is not used, apl must provide error pattern and dtype until\r
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high only\r
+ );\r
+ port(\r
+ -- Misc\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+\r
+ INT_DATAREADY_OUT : out std_logic;\r
+ INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_IN : in std_logic;\r
+\r
+ INT_DATAREADY_IN : in std_logic;\r
+ INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);\r
+ INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);\r
+ INT_READ_OUT : out std_logic;\r
+\r
+ -- Trigger information output\r
+ TRG_TYPE_OUT : out std_logic_vector (3 downto 0);\r
+ TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);\r
+ TRG_CODE_OUT : out std_logic_vector (7 downto 0);\r
+ TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0);\r
+ TRG_RECEIVED_OUT : out std_logic;\r
+ TRG_RELEASE_IN : in std_logic;\r
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+ component trb_net16_tx_control is\r
+ port(\r
+ TXCLK_IN : in std_logic;\r
+ RXCLK_IN : in std_logic;\r
+ SYSCLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ TX_DATA_IN : in std_logic_vector(15 downto 0);\r
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
+ TX_WRITE_IN : in std_logic;\r
+ TX_READ_OUT : out std_logic;\r
+\r
+ TX_DATA_OUT : out std_logic_vector(7 downto 0);\r
+ TX_K_OUT : out std_logic;\r
+\r
+ REQUEST_RETRANSMIT_IN : in std_logic;\r
+ REQUEST_POSITION_IN : in std_logic_vector(7 downto 0);\r
+\r
+ START_RETRANSMIT_IN : in std_logic;\r
+ START_POSITION_IN : in std_logic_vector(7 downto 0);\r
+\r
+ SEND_LINK_RESET_IN : in std_logic;\r
+ TX_ALLOW_IN : in std_logic;\r
+\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+\r
+\r
+ component wide_adder_17x16 is\r
+ generic(\r
+ SIZE : integer := 16;\r
+ WORDS : integer := 17 --fixed\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ RESET : in std_logic;\r
+ INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0);\r
+ START_IN : in std_logic;\r
+ VAL_ENABLE_IN : in std_logic_vector(WORDS-1 downto 0);\r
+ RESULT_OUT : out std_logic_vector(SIZE-1 downto 0);\r
+ OVERFLOW_OUT : out std_logic;\r
+ READY_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+\r
+ component trb_net_bridge_etrax_apl is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ CLK_EN : in std_logic;\r
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
+ CPU_READ : in std_logic;\r
+ CPU_WRITE : in std_logic;\r
+ CPU_DATA_OUT : out std_logic_vector (31 downto 0);\r
+ CPU_DATA_IN : in std_logic_vector (31 downto 0);\r
+ CPU_DATAREADY_OUT : out std_logic;\r
+ CPU_ADDRESS : in std_logic_vector (15 downto 0);\r
+ STAT : out std_logic_vector (31 downto 0);\r
+ CTRL : in std_logic_vector (31 downto 0)\r
+ );\r
+ end component;\r
+\r
+\r
+end package;\r
jspc29 / trbnet.git / commitdiff