%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{CTS Control Registers}
+subsection{CTS Control Registers}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
For all registers described in this subsection refer to the Fig.\ref{cts_logic}
\end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{CTS Status Registers}
+subsection{CTS Status Registers}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{CTS Data structure}
+subsection{CTS Data structure}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
When there is trigger type which is not equal 0x9 (MDC calibration trigger sent each second) then the data from CTS contains 5 data words.
\begin{figure}
\centering
- \includegraphics[width=.9\textwidth]{cts_doc.pdf}
+ \includegraphics[height=.95\textheight]{cts_doc.pdf}
\caption{CTS trigger box logic}
\label{cts_logic}
\end{figure}
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\subsubsection*{Exclude Systems}
\begin{description}
- \item[Nocts, Nohub, Nomdc, Norich, Norpc, \\Noshower, Nowall, Nostart, Notof] These commands remove the given system from loading settings, loading FPGA designs and the TRB list.
- \item[\textsc{All, Tof, Rich, Rpc, Shower, Mdc, Wall, Mdc12, Mdc34}] These commands include the given systems in the network by switching on the corresponding port on the central Hub. Please note that the default (without these commands) is all detectors off!
+ \item[Nocts, Nohub, Nomdc, Norich, Norpc, \\Noshower, Nowall, Nostart, Notof] ~\\These commands remove the given system from loading settings, loading FPGA designs and the TRB list.
+ \item[\textsc{All, Tof, Rich, Rpc, Shower, Mdc, Wall, Mdc12, Mdc34}] ~\\These commands include the given systems in the network by switching on the corresponding port on the central Hub. Please note that the default (without these commands) is all detectors off!
\end{description}
\end{description}
\item[Execution examples] :
\begin{description}
-\item[Start EBs] : start\_eb\_gbe.pl -e start
-\item[Stop EBs] : start\_eb\_gbe.pl -e stop
-\item[Start 6 EBs with the numbers 0,1,2,3,5,7] : start\_eb\_gbe.pl -e start -n 0-3 -n 5 -n 7
-\item[Start Epics IOCs] : start\_eb\_gbe.pl -i start
-\item[Stop Epics IOCs] : start\_eb\_gbe.pl -i stop
+\item[Start EBs] : \\\verb!start_eb_gbe.pl -e start!
+\item[Stop EBs] : \\\verb!start_eb_gbe.pl -e stop!
+\item[Start 6 EBs with the 0,1,2,3,5,7] : \\\verb!start_eb_gbe.pl -e start -n 0-3 -n 5 -n 7!
+\item[Start Epics IOCs] : \\\verb!start_eb_gbe.pl -i start!
+\item[Stop Epics IOCs] : \\\verb!start_eb_gbe.pl -i stop!
\end{description}
\end{description}
\subsection{Monitoring Event Builders}
As has been already said the monitoring of EBs is based on the IOC processes running on each EB server.
+\\Usually the monitoring is already running at vncserver lxhadesdaq:3. Before starting the monitoring one should set two environment variables:
+\\\verb!export EPICS_CA_ADDR_LIST=192.168.101.255!
+\\\verb!export EPICS_CA_AUTO_ADDR_LIST=NO!
+\\The monitoring can be started by executing:
+\\\verb!lxhadesdaq:/home/scs/Desktop/DAQ/EB_Monitor.desktop!
-Usually the monitoring is already running at vncserver lxhadesdaq:3.
-
-Before starting the monitoring one should set two env variables:
-\begin{itemize}
- \item export EPICS\_CA\_ADDR\_LIST=192.168.101.255
- \item export EPICS\_CA\_AUTO\_ADDR\_LIST=NO
- \end{itemize}
-
-The monitoring can be started by executing:
-lxhadesdaq: /home/scs/Desktop/DAQ/EB\_Monitor.desktop
\subsection{Monitoring Event Builder's Logs}
To learn more details about the running Event Builders on can look at
the output of the monitoring stript which scans the log files of all the
EBs.
-\newline
-\newline
-Usually you can find the output of this script at vncserver lxhadesdaq:3.
-\newline
-\newline
-For example the log file of EB 1 running on the lxhadeb01 cab be found on lxhadesdaq
-/home/hadaq/oper/oper\_1/eb1\_log.txt.
-\newline
-\newline
-The script can be started by executing:
-lxhadesdaq: /home/hadaq/Desktop/DAQ/EBLog\_Watch.desktop
+\\For example the log file of EB 1 running on the lxhadeb01 can be found on
+\\\verb!lxhadesdaq:/home/hadaq/oper/oper_1/eb1_log.txt!.
+\\The script can be started by executing:
+\\\verb!lxhadesdaq:/home/hadaq/Desktop/DAQ/EBLog_Watch.desktop!
+\\Usually you can find the output of this script at vncserver lxhadesdaq:3.
\section{Storing data to Oracle database}
\subsection{Time stamp and current info on boards}
The DAQ startup script writes the ascii file with all the active boards in the system and the time stamp.
-The daq2ora\_client.pl script reads this ascii file on lxhadesdaq (/home/hadaq/\-oper/daq2ora/\-daq2ora\_2010-08-30\_12.49.50.txt) and stores the info in the Oracle database. The info consists of board unique Id, TRB-Net address, subEvent Id, TDC RC Mode, threshold version for RICH and MDC as well as MDC TDC mask version.
+The daq2ora\_client.pl script reads this ascii file on lxhadesdaq e.g. \\\verb!~/oper/daq2ora/daq2ora_2010-08-30_12.49.50.txt!
+\\and stores the info in the Oracle database. The info consists of board unique Id, TRB-Net address, subEvent Id, TDC RC Mode, threshold version for RICH and MDC as well as MDC TDC mask version.
\begin{description}
\item[Script options] :
\end{description}
\item[More info] :
\begin{description}
- \item[Execute on lxhadesdaq] : /home/hadaq/\-trbsoft/daq/oracle/\-daq2ora\_client.pl -o -v -d \&
- \item[More info can be found here] : http://hades-wiki.gsi.de/\-cgi-bin/\-view/\-DaqSlowControl/\-SoftTools\-\#daq2ora\_client\_pl\_daemon\_to\_inse
+ \item[Execute on lxhadesdaq] : \\\verb!~/trbsoft/daq/oracle/daq2ora_client.pl -o -v -d &!
+ \item[More info can be found here] : \\\href{http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/SoftTools\#daq2ora_client_pl_daemon_to_inse}{Wiki: DaqSlowControl -> SoftTools -> daq2ora\_client}
\end{description}
\end{description}
Port C: RPC sector 4,5,6 \newline
Port D: RPC sector 1,2,3 \\
\hline
-5\newline hadswXX & rear right corner& Longshine LCS-GS9240 \newline
+5\newline hadswX & rear right corner& Longshine LCS-GS9240 \newline
2 links to both RPC hub TRB \newline
1 link to Shower hub TRB \newline
6 links to all RPC/Shower sector hubs \newline
Port C: MDC 3/4 Hub 4 (address 1130) \newline
Port D: MDC 3/4 Hub 3 (address 1120) \\
\hline
-10\newline hadsw03 & front rack & Netgear 12 port \newline
+10\newline hadsw13 & front rack & Longshine LCS-GS9240 \newline
Port 1: Uplink 01C-02 \newline
Port 9: MDC1/2 Hub \newline
Port 10: MDC3/4 Hub \newline
Uplink via switch 11 \newline
TOF TRB \newline
Hub TOF, Hub MDC 3/4 \\
-
+\hline
\caption{Position and usage of GbE switches}
\label{NetworkSwitch}
\end{longtable}
22 & severe problem & serious sync problem detected - intervention needed. Set by user. \\
23 & single broken event & event data corrupted, next event most likely not affected. Set by user. \\
24 & Ethernet link broken & Ethernet link to send data is down. Data has been lost. \\
-25 & SubEvent buffer almost full & The buffer to store events in the Ethernet interface is almost full, a stop within the next few events is likely \\
+25 & SubEvent buffer full & The buffer to store events in the Ethernet interface is almost full, a stop within the next few events is likely \\
26 & Ethernet error & The ethernet interface found partially corrupted data and discarded this event. Only partial data has been transmitted to the EB. \\
-27 & & \\
+27 & timing trigger error & There was a problem related to the timing trigger, e.g. multiple or missing timing triggers, spikes \\
28 & & \\
29 & & \\
30 & & \\
\label{fig:timingtriggercase6}
\end{figure}
-
+\subsubsection{Status and Statistics Registers}
+The LVL1 trigger handler features four 32 bit status registers. They are accessible at register addresses 2,3,6,7 in each network endpoint. The definitions can be found in tables \ref{CommonStatReg2}, \ref{CommonStatReg3}, \ref{CommonStatReg6} and \ref{CommonStatReg7}.
21 & buffers almost full & The event data buffers are almost full. Set by user. \\
22 & not configured & Frontend is not configured correctly to handle triggers, an initilization is needed. Set by user. \\
23 & frontend error & Parts of the connected frontend are not behaving correctly: no response, not synchronized, token missing...\\
-24 - 31 & t.b.d. & Not yet defined \\
+24 & spike detected & A spike was detected on the timing trigger input. \\
+25 & trigger timeout & The delay between timing trigger and LVL1 trigger was longer than expected \\
+26 - 31 & t.b.d. & Not yet defined \\
\end{tabularx}
\caption{Error- and Status information contained in the network termination packet}
\label{LVL1Errorbits}
-
\documentclass[11pt,a4paper,twoside]{scrartcl} %twoside
%Einstellungen der Seitenr�nder
%\usepackage{mathptmx}
%\usepackage{pslatex}
-\title{A Users Guide\\to the\\HADES DAQ Network}
+\title{A Users Guide\\to the\\HADES DAQ System}
\date{\today ~-~\thistime}
-\author{Jan Michel, Michael B\"ohmer, Grzegorz Korcyl, Marek Palka}
+\author{Jan Michel, Michael B\"ohmer, Grzegorz Korcyl, Marek Palka, Sergey Yurevich}
\newcommand{\filename}[1]{\textit{#1}}
\label{MediaInterfaceControl}
\end{center}
\end{table}
+
+
+
+\subsection{ECP2M FOT Interface}
+\subsubsection{Status Register}
+
+\begin{table}[hbtp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|X|}
+\hline
+\textbf{Reg.} & \textbf{Bit} & \textbf{Description} \\
+\hline\hline
+\multicolumn{3}{|l|}{TX Control}\\
+\hline
+0 & 7 -- 0 & RAM fill level \\
+0 & 15 -- 8 & RAM read address \\
+0 & 16 & RAM almost full \\
+0 & 17 & RAM empty \\
+0 & 18 & TX allow (sync'ed to TX clock) \\
+0 & 19 & TX allow \\
+0 & 20 & Restart transmission from given RAM position \\
+0 & 21 & Request a restart of transmission \\
+0 & 31 -- 24 & Request restart position \\
+\hline
+\multicolumn{3}{|l|}{RX Full Packets}\\
+\hline
+1 & 3 -- 0 & Status of state machine \\
+1 & 4 & got timeout (toc\_done) \\
+1 & 5 & packet in transit (transit)\\
+1 & 6 & packet timeout (pkt\_timeout)\\
+1 & 7 & timeout counter clock enable (ce\_toc)\\
+1 & 10 -- 8 & RX counter \\
+\hline
+\multicolumn{3}{|l|}{RX Comma Handler}\\
+\hline
+1 & 20 -- 16 & Counter for reset words \\
+1 & 21 & writing to RX Fifo is blocked (fifo\_inhibit) \\
+1 & 22 & locked to comma (comma\_locked) \\
+\hline
+1 & 31 -- 24 & load buffer position for start retransmit (rx\_position) \\
+\hline
+\multicolumn{3}{|l|}{RX Checker}\\
+\hline
+2 & 3 -- 0 & State machine \\
+2 & 4 & Fifo reset (fifo\_rst) \\
+2 & 5 & request a retransmission (request) \\
+2 & 6 & resume receiving (resume) \\
+\hline
+\multicolumn{3}{|l|}{RX Control}\\
+\hline
+2 & 15 -- 8 & Position to start retransmission from (start\_position) \\
+2 & 16 & Timeout while receiving one packet (packet\_timeout) \\
+2 & 17 & Experienced a RX error(rx\_gone\_wrong) \\
+2 & 18 & packet in transit (pkt\_in\_transit) \\
+2 & 31 -- 24 & Request retransmission position (request\_position) \\
+\hline
+\end{tabularx}
+\caption{Status Registers of the FOT media interface}
+\label{MediaInterfaceFOTRegs}
+\end{center}
+\end{table}
+
\hline
\textbf{Address} & \textbf{Mnemonics} & \textbf{Name} & \textbf{Description} \\
\hline\hline
-00 & common status register 0 & CSR0 & Basic Error Flags and Temperature (see below) (r) \\
-01 & common status register 1 & CSR1 & LVL1 trigger number (Bits 15..0), timing Trigger number (Bits 31..16) (r) \\
-02 & common status register 2 & CSR2 & Status of LVL1 handler \\
-03 & common status register 3 & CSR3 & Trigger input monitor. Bit 15..0: Edge count, Bit 31..16: Length of last pulse \\
-04 & common status register 4 & CSR4 & Link and reset status register \\
-20 & common control register 0 & CCR0 & Strobes for board resets and test triggers (see below) (w)\\
-21 & common control register 1 & CCR1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
-22 & common control register 2 & CCR2 & frontend enable, trigger enable, debug enable (r/w)\\
-40 & information ROM 0 & ROM0 & Compile Time (set by generic) (r)\\
-41 & information ROM 1 & ROM1 & Design Version (set by generic) (r) \\
-42 & information ROM 2 & ROM2 & Hardware Information (set by generic) (r)\\
-50 & global time & TME & Global Time (r/w)\\
-51 & time since trigger & TSTR & Time since last timing trigger (r)\\
-80 -- BF & user status registers & SRn & User status registers \\
-C0 -- FF & user control registers & CRn & User control registers \\
+00 & common status reg 0 & CSR0 & Basic Error Flags and Temperature (see below) (r) \\
+01 & common status reg 1 & CSR1 & LVL1 and IPU event numbers \\
+02 & common status reg 2 & CSR2 & LVL1 handler status register \\
+03 & common status reg 3 & CSR3 & LVL1 handler statistics 0. \\
+04 & common status reg 4 & CSR4 & Link and reset status register \\
+05 & common status reg 5 & CSR5 & Trigger data register \\
+06 & common status reg 6 & CSR6 & LVL1 handler statistics 1 \\
+07 & common status reg 7 & CSR7 & LVL1 handler statistics 2 \\
+20 & common control reg 0 & CCR0 & Strobes for board resets and test triggers (see below) (w)\\
+21 & common control reg 1 & CCR1 & Sets LVL1 trigger number (Bits 15..0) (r/w)\\
+22 & common control reg 2 & CCR2 & frontend enable, trigger enable, debug enable (r/w)\\
+40 & information ROM 0 & ROM0 & Compile Time (set by generic) (r)\\
+41 & information ROM 1 & ROM1 & Design Version (set by generic) (r) \\
+42 & information ROM 2 & ROM2 & Hardware Information (set by generic) (r)\\
+50 & global time & TME & Global Time (r/w)\\
+51 & time since trigger & TSTR & Time since last timing trigger (r)\\
+80 -- BF & user status reg & SRn & User status registers \\
+C0 -- FF & user control reg & CRn & User control registers \\
0100 -- 6FFF & reserved & --- & Reserved addresses on internal data port (e.g. for monitoring and other features)\\
7000 -- 7FFF & endpoint monitoring & --- & Monitoring Registers for Endpoint\\
8000 -- FFFF & user defined & --- & User defined address space on the internal data bus \\
\end{table}
-\paragraph{Common Control and Status Registers (0x00 - 0x03, 0x20 - 0x22)}
+\paragraph{Common Control and Status Registers (0x00 - 0x05, 0x20 - 0x22)}
The first common status register (0x00) is described in table \ref{CommonStatReg0}. It is used for error flags
and readback of the boards temperature. The second status register (0x01) is used to read the LVL1 trigger number
\end{center}
\end{table}
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 16 & Last read-out event number on IPU channel \\
+15 -- 0 & Internal LVL1 trigger number \\
+\hline
+\end{tabularx}
+\caption{Common Status Register 1 (CSR1): IPU and trigger event numbers}
+\label{CommonStatReg1}
+\end{center}
+\end{table}
+
\begin{table}
\begin{center}
\begin{tabularx}{\textwidth}{|c|X|}
3 -- 0 & Status of LVL1 handler state machine. 0: idle, 1: timing trigger found, 3: LVL1 trigger received, 5: bad combination of timing trigger and LVL1 trigger, 7: done.\\
\hline
\end{tabularx}
-\caption{Common Status Register 2 (CSR2)}
+\caption{Common Status Register 2 (CSR2): LVL1 handler status}
\label{CommonStatReg2}
\end{center}
\end{table}
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 16 & Length of last timing trigger signal $(length = (value+1)*10~\mbox{ns})$ \\
+15 -- 0 & Number of seen rising edges on the timing trigger input \\
+\hline
+\end{tabularx}
+\caption{Common Status Register 3 (CSR3): LVL1 handler statistics 0}
+\label{CommonStatReg3}
+\end{center}
+\end{table}
+
\begin{table}
\begin{center}
3 -- 0 & counter for received network resets (written by endpoint) \\
\hline
\end{tabularx}
-\caption{Common Status Register 4 (CSR4)}
+\caption{Common Status Register 4 (CSR4): Link and reset statistics}
\label{CommonStatReg4}
\end{center}
\end{table}
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 24 & Trigger code of the last received LVL1 trigger \\
+23 -- 20 & Lower 4 bits of the last received trigger number \\
+19 -- 16 & Trigger type of last received LVL1 trigger\\
+15 -- 0 & Trigger information from last received LVL1 trigger \\
+\hline
+\end{tabularx}
+\caption{Common Status Register 5 (CSR5): Trigger information}
+\label{CommonStatReg5}
+\end{center}
+\end{table}
+
+
+
+
+
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 16 & Number occurences of multiple timing trigger before a LVL1 trigger \\
+15 -- 0 & Number of invalid triggers (i.e. LVL1 triggers not preceeded by a timing trigger signal\\
+\hline
+\end{tabularx}
+\caption{Common Status Register 6 (CSR6): LVL1 handler statistics 1}
+\label{CommonStatReg6}
+\end{center}
+\end{table}
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 16 & Number of spurious triggers (i.e. timing triggers preceeding a timing triggerless trigger) \\
+15 -- 0 & Number of spikes seen on the timing trigger input \\
+\hline
+\end{tabularx}
+\caption{Common Status Register 7 (CSR7): LVL1 handler statistics 2}
+\label{CommonStatReg7}
+\end{center}
+\end{table}
+
+
\begin{table}
\begin{center}
\begin{tabular}{|c|c|}
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