entity tomcat_tools is
port(
- CLK : in std_logic;
- RESET : in std_logic;
-
- --Flash & Reload
- FLASH_CS : out std_logic;
- FLASH_CLK : out std_logic;
- FLASH_IN : in std_logic;
- FLASH_OUT : out std_logic;
- PROGRAMN : out std_logic;
- REBOOT_IN : in std_logic;
-
- --SPI
- SPI_CS_OUT : out std_logic_vector(15 downto 0);
- SPI_MOSI_OUT: out std_logic_vector(15 downto 0);
- SPI_MISO_IN : in std_logic_vector(15 downto 0) := (others => '0');
- SPI_CLK_OUT : out std_logic_vector(15 downto 0);
-
- --LCD
- LCD_DATA_IN : in std_logic_vector(511 downto 0) := (others => '0');
- ADDITIONAL_REG : out std_logic_vector(31 downto 0);
- --HDR_IO
- HEADER_IO : inout std_logic_vector(10 downto 1);
-
- --ADC
- ADC_CS : out std_logic := '0';
- ADC_MOSI : out std_logic := '0';
- ADC_MISO : in std_logic := '0';
- ADC_CLK : out std_logic := '0';
-
- --Trigger & Monitor
- MONITOR_INPUTS : in std_logic_vector(MONITOR_INPUT_NUM-1 downto 0) := (others => '0');
- TRIG_GEN_INPUTS : in std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0) := (others => '0');
- TRIG_GEN_OUTPUTS : out std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);
- --SED
- SED_ERROR_OUT : out std_logic;
-
- --Slowcontrol
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX;
-
- --Control master for default settings
- BUS_MASTER_IN : in CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0');
- BUS_MASTER_OUT : out CTRLBUS_RX;
- BUS_MASTER_ACTIVE : out std_logic;
-
- DEBUG_OUT : out std_logic_vector(31 downto 0)
- );
+ CLK : in std_logic;
+ RESET : in std_logic;
+ -- Flash & Reload
+ FLASH_CS : out std_logic;
+ FLASH_CLK : out std_logic;
+ FLASH_IN : in std_logic;
+ FLASH_OUT : out std_logic;
+ PROGRAMN : out std_logic;
+ REBOOT_IN : in std_logic;
+ -- Slowcontrol
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+ -- Control master for default settings
+ BUS_MASTER_IN : in CTRLBUS_TX := (data => (others => '0'), unknown => '1', others => '0');
+ BUS_MASTER_OUT : out CTRLBUS_RX;
+ BUS_MASTER_ACTIVE : out std_logic;
+ -- Additional regs
+ ADDITIONAL_REG : out std_logic_vector(31 downto 0);
+ -- I2C
+ SDA_INOUT : inout std_logic;
+ SCL_INOUT : inout std_logic;
+ -- Debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
end entity;
-
-
architecture tomcat_tools_arch of tomcat_tools is
-signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx, busspi_rx, busadc_rx, bussed_rx,
- busuart_rx, busflashset_rx, busmon_rx, bustrig_rx, busctrl_rx : CTRLBUS_RX;
-signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx,
- busuart_tx, busflashset_tx, busmon_tx, bustrig_tx, busctrl_tx : CTRLBUS_TX;
-
-signal spi_sdi, spi_sdo, spi_sck : std_logic_vector(15 downto 0);
-signal spi_cs : std_logic_vector(15 downto 0);
-signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic;
-signal uart_rx, uart_tx : std_logic;
+signal bus_debug_rx_out, bus_flash_rx_out, busflash_rx,
+ busflashset_rx, busctrl_rx, busi2c_rx : CTRLBUS_RX;
+signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx,
+ busflashset_tx, busctrl_tx, busi2c_tx : CTRLBUS_TX;
signal flashset_active, debug_active : std_logic;
signal flash_cs_i, flash_clk_i, flash_out_i : std_logic;
signal flash_cs_s, flash_clk_s, flash_out_s : std_logic;
-signal debug_rx, debug_tx : std_logic;
-signal debug_status : std_logic_vector(31 downto 0);
-signal additional_reg_i : std_logic_vector(31 downto 0);
+signal debug_rx : std_logic;
+signal debug_tx : std_logic;
+signal debug_status : std_logic_vector(31 downto 0);
+signal additional_reg_i : std_logic_vector(31 downto 0);
+
+signal i2c_reg0_i : std_logic_vector(31 downto 0) := x"0000_0000";
+signal i2c_reg1_i : std_logic_vector(31 downto 0) := x"0000_0000";
+signal i2c_reg2_i : std_logic_vector(31 downto 0) := x"0000_0000";
+signal i2c_reg3_i : std_logic_vector(31 downto 0) := x"0000_003f";
+signal i2c_status_i : std_logic_vector(31 downto 0);
+signal sda_drv : std_logic;
+signal scl_drv : std_logic;
+signal i2c_start_x : std_logic;
+signal i2c_start : std_logic;
begin
-- Bus Handler
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
- generic map(
- PORT_NUMBER => 9,
- PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600",
- 5 => x"0180", 6 => x"0f00", 7 => x"0f80", 8 => x"0580", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 2, 4 => 2,
- 5 => 4, 6 => 7, 7 => 7, 8 => 0, others => 0),
- PORT_MASK_ENABLE => 1
- )
- -- 0 flash, 1 SPU, 2 ADC, 3 SED, 4 UART, 5 flashset, 6 trig, 7 mon, 8 ctrl
- port map(
- CLK => CLK,
- RESET => RESET,
+ generic map(
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0180", 2 => x"0580", 3 => x"0700", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 4, 2 => 0, 3 => 2, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ -- 0 flash, 1 flashset, 2 ctrl, 3 I2C
+ port map(
+ CLK => CLK,
+ RESET => RESET,
- REGIO_RX => BUS_RX,
- REGIO_TX => BUS_TX,
+ REGIO_RX => BUS_RX,
+ REGIO_TX => BUS_TX,
- BUS_RX(0) => busflash_rx,
- BUS_RX(1) => busspi_rx,
- BUS_RX(2) => busadc_rx,
- BUS_RX(3) => bussed_rx,
- BUS_RX(4) => busuart_rx,
- BUS_RX(5) => busflashset_rx,
- BUS_RX(6) => bustrig_rx,
- BUS_RX(7) => busmon_rx,
- BUS_RX(8) => busctrl_rx,
- BUS_TX(0) => busflash_tx,
- BUS_TX(1) => busspi_tx,
- BUS_TX(2) => busadc_tx,
- BUS_TX(3) => bussed_tx,
- BUS_TX(4) => busuart_tx,
- BUS_TX(5) => busflashset_tx,
- BUS_TX(6) => bustrig_tx,
- BUS_TX(7) => busmon_tx,
- BUS_TX(8) => busctrl_tx,
- STAT_DEBUG => open
- );
-
-
+ BUS_RX(0) => busflash_rx,
+ BUS_RX(1) => busflashset_rx,
+ BUS_RX(2) => busctrl_rx,
+ BUS_RX(3) => busi2c_rx,
+ BUS_TX(0) => busflash_tx,
+ BUS_TX(1) => busflashset_tx,
+ BUS_TX(2) => busctrl_tx,
+ BUS_TX(3) => busi2c_tx,
+ STAT_DEBUG => open
+ );
---------------------------------------------------------------------------
-- Flash & Reboot
---------------------------------------------------------------------------
THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record
- port map(
- CLK_IN => CLK,
- RESET_IN => RESET,
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
- BUS_RX => busflash_rx,
- BUS_TX => busflash_tx,
+ BUS_RX => busflash_rx,
+ BUS_TX => busflash_tx,
- DO_REBOOT_IN => REBOOT_IN,
- PROGRAMN => PROGRAMN,
+ DO_REBOOT_IN => REBOOT_IN,
+ PROGRAMN => PROGRAMN,
- SPI_CS_OUT => flash_cs_i,
- SPI_SCK_OUT => flash_clk_i,
- SPI_SDO_OUT => flash_out_i,
- SPI_SDI_IN => FLASH_IN
- );
+ SPI_CS_OUT => flash_cs_i,
+ SPI_SCK_OUT => flash_clk_i,
+ SPI_SDO_OUT => flash_out_i,
+ SPI_SDI_IN => FLASH_IN
+ );
---------------------------------------------------------------------------
-- Load Settings from Flash
---------------------------------------------------------------------------
-THE_FLASH_REGS : entity work.load_settings
+ THE_FLASH_REGS : entity work.load_settings
port map(
- CLK => CLK,
- RST => RESET,
+ CLK => CLK,
+ RST => RESET,
- -- the bus handler signals
BUS_RX => busflashset_rx,
BUS_TX => busflashset_tx,
SPI_MISO => FLASH_IN,
SPI_SCK => flash_clk_s,
SPI_NCS => flash_cs_s
-
- );
+ );
BUS_MASTER_ACTIVE <= flashset_active or debug_active;
FLASH_CS <= flash_cs_i when flashset_active = '0' else flash_cs_s;
BUS_MASTER_OUT <= bus_debug_rx_out when debug_active = '1' else
bus_flash_rx_out;
-
-
----------------------------------------------------------------------------
--- SED Detection
----------------------------------------------------------------------------
- THE_SED : entity work.sedcheck
- port map(
- CLK => CLK,
- ERROR_OUT => SED_ERROR_OUT,
- BUS_RX => bussed_rx,
- BUS_TX => bussed_tx,
- DEBUG => open
- );
-
-
----------------------------------------------------------------------------
--- ADC
----------------------------------------------------------------------------
- busadc_tx.unknown <= '1';
- busadc_tx.nack <= '0';
- busadc_tx.ack <= '0';
- busadc_tx.data <= (others => '0');
-
-
----------------------------------------------------------------------------
--- ADC
----------------------------------------------------------------------------
-gen_lcd : if INCLUDE_LCD = 1 generate
- THE_LCD : entity work.lcd
- port map(
- CLK => CLK,
- RESET => RESET,
-
- MOSI => lcd_mosi,
- SCK => lcd_sck,
- DC => lcd_dc,
- CS => lcd_cs,
- RST => lcd_rst,
-
- INPUT => LCD_DATA_IN,
- DEBUG => open
- );
-end generate;
-
----------------------------------------------------------------------------
--- SPI
----------------------------------------------------------------------------
- gen_SPI : if INCLUDE_SPI = 1 generate
- THE_SPI : spi_ltc2600
- port map(
- CLK_IN => CLK,
- RESET_IN => RESET,
- -- Slave bus
- BUS_ADDR_IN => busspi_rx.addr(4 downto 0),
- BUS_READ_IN => busspi_rx.read,
- BUS_WRITE_IN => busspi_rx.write,
- BUS_ACK_OUT => busspi_tx.ack,
- BUS_BUSY_OUT => busspi_tx.nack,
- BUS_DATA_IN => busspi_rx.data,
- BUS_DATA_OUT => busspi_tx.data,
- -- SPI connections
- SPI_CS_OUT(15 downto 0) => spi_cs,
- SPI_SDI_IN => spi_sdi,
- SPI_SDO_OUT => spi_sdo,
- SPI_SCK_OUT => spi_sck
- );
- SPI_CS_OUT <= spi_cs;
- SPI_CLK_OUT <= spi_sck;
- SPI_MOSI_OUT <= spi_sdo;
-
- spi_sdi <= SPI_MISO_IN(15 downto 9) & HEADER_IO(4) & ADC_MISO & SPI_MISO_IN(6 downto 0);
-
- ADC_CLK <= not spi_sck(7);
- ADC_CS <= spi_cs(7);
- ADC_MOSI <= spi_sdo(7);
-
- busspi_tx.unknown <= '0';
- end generate;
-
- gen_no_spi : if INCLUDE_SPI = 0 generate
- busspi_tx.unknown <= busspi_rx.write or busspi_rx.read;
- busspi_tx.ack <= '0'; busspi_tx.nack <= '0';
- busspi_tx.data <= (others => '0');
- end generate;
-
----------------------------------------------------------------------------
--- UART
----------------------------------------------------------------------------
- gen_uart : if INCLUDE_UART = 1 generate
- THE_UART : entity work.uart
- generic map(
- OUTPUTS => 1
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- UART_RX(0) => uart_rx,
- UART_TX(0) => uart_tx,
- BUS_RX => busuart_rx,
- BUS_TX => busuart_tx
- );
- end generate;
- gen_no_uart : if INCLUDE_UART = 0 generate
- busuart_tx.unknown <= busuart_rx.write or busuart_rx.read;
- busuart_tx.ack <= '0'; busuart_tx.nack <= '0';
- busuart_tx.data <= (others => '0');
- end generate;
---------------------------------------------------------------------------
-- Debug Connection
BUS_DEBUG_RX => bus_debug_rx_out,
STATUS => debug_status
-
- );
+ );
end generate;
+
gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate
bus_debug_rx_out.write <= '0';
bus_debug_rx_out.read <= '0';
debug_active <= '0';
end generate;
----------------------------------------------------------------------------
--- Trigger logic
----------------------------------------------------------------------------
-gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
- THE_TRIG_LOGIC : entity work.input_to_trigger_logic_record
- generic map(
- INPUTS => TRIG_GEN_INPUT_NUM,
- OUTPUTS => TRIG_GEN_OUTPUT_NUM
- )
- port map(
- CLK => CLK,
-
- INPUT => TRIG_GEN_INPUTS,
- OUTPUT => TRIG_GEN_OUTPUTS,
-
- BUS_RX => bustrig_rx,
- BUS_TX => bustrig_tx
- );
-
-end generate;
-
-gen_noTRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate
- bustrig_tx.unknown <= bustrig_rx.write or bustrig_rx.read;
- bustrig_tx.ack <= '0'; bustrig_tx.nack <= '0';
- bustrig_tx.data <= (others => '0');
-end generate;
-
----------------------------------------------------------------------------
--- Input Statistics
----------------------------------------------------------------------------
-gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
-
- THE_STAT_LOGIC : entity work.input_statistics
- generic map(
- INPUTS => MONITOR_INPUT_NUM,
- SINGLE_FIFO_ONLY => c_YES
- )
- port map(
- CLK => CLK,
-
- INPUT => MONITOR_INPUTS,
-
- DATA_IN => busmon_rx.data,
- DATA_OUT => busmon_tx.data,
- WRITE_IN => busmon_rx.write,
- READ_IN => busmon_rx.read,
- ACK_OUT => busmon_tx.ack,
- NACK_OUT => busmon_tx.nack,
- ADDR_IN => busmon_rx.addr
- );
- busmon_tx.unknown <= '0';
-end generate;
-
-gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate
- busmon_tx.unknown <= busmon_rx.write or busmon_rx.read;
- busmon_tx.ack <= '0'; busmon_tx.nack <= '0';
- busmon_tx.data <= (others => '0');
-end generate;
-
---------------------------------------------------------------------------
-- Additional control register
---------------------------------------------------------------------------
-proc_add_reg : process begin
- wait until rising_edge(CLK);
- busctrl_tx.ack <= '0';
- busctrl_tx.nack <= '0';
- busctrl_tx.unknown <= '0';
+ PROC_ADD_REG : process begin
+ wait until rising_edge(CLK);
+ busctrl_tx.ack <= '0';
+ busctrl_tx.nack <= '0';
+ busctrl_tx.unknown <= '0';
- if busctrl_rx.read = '1' then
- busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
- busctrl_tx.ack <= '1';
- elsif busctrl_rx.write = '1' then
- additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0);
- busctrl_tx.ack <= '1';
- end if;
-end process;
+ if busctrl_rx.read = '1' then
+ busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
+ busctrl_tx.ack <= '1';
+ elsif busctrl_rx.write = '1' then
+ additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0);
+ busctrl_tx.ack <= '1';
+ end if;
+ end process PROC_ADD_REG;
ADDITIONAL_REG <= additional_reg_i;
---------------------------------------------------------------------------
--- HEADER_IO
----------------------------------------------------------------------------
--- 1 UART TX
--- 2 UART RX
--- 3 SPI MOSI
--- 4 SPI MISO
--- 5 SPI CLK
--- 6 SPI CS
--- 7 lcd_dc
--- 8 lcd_rst
--- 9 Debug RX
--- 10 Debug TX
--- 11 3.3V
--- 12 3.3V
--- 13 GND
--- 14 GND
-
-HEADER_IO(1) <= uart_tx;
-uart_rx <= HEADER_IO(2);
-
-gen_lcdio : if INCLUDE_LCD = 1 generate
- HEADER_IO(3) <= lcd_mosi;
- HEADER_IO(5) <= lcd_sck;
- HEADER_IO(6) <= lcd_cs;
-end generate;
-gen_nolcdio : if INCLUDE_LCD = 0 generate
- HEADER_IO(3) <= spi_sdo(8);
- -- HEADER_IO(4) <= ;
- HEADER_IO(5) <= spi_sck(8);
- HEADER_IO(6) <= spi_cs(8);
-end generate;
-
-
-HEADER_IO(7) <= lcd_dc;
-HEADER_IO(8) <= lcd_rst;
-debug_rx <= HEADER_IO(9);
-HEADER_IO(10) <= debug_tx;
-
-DEBUG_OUT <= debug_status;
+-- I2C
+---------------------------------------------------------------------------
+ THE_I2C_REG_PROC: process( CLK )
+ begin
+ if( rising_edge(CLK) ) then
+ busi2c_tx.ack <= '0';
+ busi2c_tx.nack <= '0';
+ busi2c_tx.unknown <= '0';
+
+ if ( busi2c_rx.read = '1' ) then
+ case busi2c_rx.addr(1 downto 0) is
+-- when b"00" => busi2c_tx.data <= i2c_reg0_i;
+ when b"00" => busi2c_tx.data <= i2c_status_i;
+ when b"01" => busi2c_tx.data <= i2c_reg1_i;
+ when b"10" => busi2c_tx.data <= i2c_reg2_i;
+ when others => busi2c_tx.data <= i2c_reg3_i;
+ end case;
+ busi2c_tx.ack <= '1';
+ elsif( busi2c_rx.write = '1' ) then
+ case busi2c_rx.addr(1 downto 0) is
+ when b"00" => i2c_reg0_i <= busi2c_rx.data;
+ when b"01" => i2c_reg1_i <= busi2c_rx.data;
+ when b"10" => i2c_reg2_i <= busi2c_rx.data;
+ when others => i2c_reg3_i <= busi2c_rx.data;
+ end case;
+ busi2c_tx.ack <= '1';
+ end if;
+ end if;
+ end process THE_I2C_REG_PROC;
+
+ i2c_start_x <= '1' when ((busi2c_rx.addr(1 downto 0) = b"10") and (busi2c_rx.write = '1'))
+ else '0';
+
+ i2c_start <= i2c_start_x when rising_edge(CLK);
+
+ THE_I2C_SLIM: entity work.i2c_slim2
+ port map(
+ CLOCK => CLK,
+ RESET => RESET,
+ -- I2C command / setup
+ I2C_GO_IN => i2c_start, --i2c_reg2_i(31), -- 1
+ ACTION_IN => i2c_reg2_i(1), -- 1
+ WORD_IN => i2c_reg2_i(0), -- 1
+ DIRECT_IN => i2c_reg2_i(2), -- 1
+ I2C_SPEED_IN => i2c_reg3_i(5 downto 0), -- 6
+ I2C_ADDR_IN => i2c_reg0_i(31 downto 24), -- 8
+ I2C_CMD_IN => i2c_reg0_i(23 downto 16), -- 8
+ I2C_DW_IN => i2c_reg0_i(15 downto 0), -- 16
+ I2C_DR_OUT => i2c_status_i(15 downto 0), -- 16
+ STATUS_OUT => i2c_status_i(23 downto 16), -- 8
+ VALID_OUT => i2c_status_i(24), -- 1
+ I2C_BUSY_OUT => i2c_status_i(25), -- 1
+ I2C_DONE_OUT => i2c_status_i(26), -- 1
+ -- I2C connections
+ SDA_IN => SDA_INOUT,
+ SDA_OUT => sda_drv,
+ SCL_IN => SCL_INOUT,
+ SCL_OUT => scl_drv,
+ -- Debug
+ BSM_OUT => i2c_status_i(31 downto 28)
+ );
+
+ i2c_status_i(27) <= '0'; -- spare
+
+ SDA_INOUT <= '0' when (sda_drv = '0') else 'Z';
+ SCL_INOUT <= '0' when (scl_drv = '0') else 'Z';
+
+
+
+ DEBUG_OUT <= debug_status;
-
end architecture;
signal tx_pcs_rst_i : std_logic;
signal link_tx_ready_i : std_logic;
+ signal led_i : std_logic_vector(3 downto 0);
+
begin
-------------------------------------------------------------------------------
trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger"
-- at least 100ns!
-INTCOM(9 downto 1) <= std_logic_vector(testctr(8 downto 0));
+INTCOM(9 downto 1) <= (others => '0'); --std_logic_vector(testctr(8 downto 0));
-TIMING_TEST <= std_logic(testctr(31));
+TIMING_TEST <= '0'; --std_logic(testctr(31));
-------------------------------------------------------------------------------
-- Endpoint
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
REGIO_INIT_ENDPOINT_ID => x"0001",
- REGIO_USE_1WIRE_INTERFACE => c_I2C,
+ REGIO_USE_1WIRE_INTERFACE => c_I2C_TC,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
BUS_MASTER_ACTIVE => bus_master_active,
--UniqueID
ONEWIRE_INOUT => open,
- I2C_SCL => I2C_SCL,
- I2C_SDA => I2C_SDA,
+ I2C_SCL => I2C_SCL, --open,
+ I2C_SDA => I2C_SDA, --open,
--Timing registers
TIMERS_OUT => timer
);
generic map(
PORT_NUMBER => 4,
PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
-------------------------------------------------------------------------------
THE_TOOLS : entity work.tomcat_tools
port map(
- CLK => clk_sys,
- RESET => reset_i,
+ CLK => clk_sys,
+ RESET => reset_i,
--Flash & Reload
- FLASH_CS => FLASH_NCS,
- FLASH_CLK => FLASH_SCLK,
- FLASH_IN => FLASH_MISO,
- FLASH_OUT => FLASH_MOSI,
- PROGRAMN => PROGRAMN,
- REBOOT_IN => common_ctrl_reg(15),
- --SPI
- SPI_CS_OUT => open,
- SPI_MOSI_OUT => open,
- SPI_MISO_IN => (others => '0'),
- SPI_CLK_OUT => open,
- --Header
- HEADER_IO => open,
- ADDITIONAL_REG(0) => led_off,
- --LCD
- LCD_DATA_IN => (others => '0'),
- --ADC
- ADC_CS => open,
- ADC_MOSI => open,
- ADC_MISO => '0',
- ADC_CLK => open,
- --Trigger & Monitor
- MONITOR_INPUTS => (others => '0'),
- TRIG_GEN_INPUTS => (others => '0'),
- TRIG_GEN_OUTPUTS(1 downto 0) => open,
- TRIG_GEN_OUTPUTS(3 downto 2) => open,
- --SED
- SED_ERROR_OUT => open,
+ FLASH_CS => FLASH_NCS,
+ FLASH_CLK => FLASH_SCLK,
+ FLASH_IN => FLASH_MISO,
+ FLASH_OUT => FLASH_MOSI,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ -- I2C
+ SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
+ SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
+ -- Additional register
+ ADDITIONAL_REG(31) => led_off,
+ ADDITIONAL_REG(0) => led_i(0),
+ ADDITIONAL_REG(1) => led_i(1),
+ ADDITIONAL_REG(2) => led_i(2),
+ ADDITIONAL_REG(3) => led_i(3),
--Slowcontrol
- BUS_RX => bustools_rx,
- BUS_TX => bustools_tx,
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
--Control master for default settings
- BUS_MASTER_IN => bus_master_in,
- BUS_MASTER_OUT => bus_master_out,
- BUS_MASTER_ACTIVE => bus_master_active,
- DEBUG_OUT => debug_tools
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => debug_tools
);
FLASH_HOLD <= '1';
-------------------------------------------------------------------------------
-- I/O
-------------------------------------------------------------------------------
- GPIO <= std_logic_vector(testctr(15 downto 0));
+ GPIO <= (others => '0'); --std_logic_vector(testctr(15 downto 0));
-------------------------------------------------------------------------------
-- LED
LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
- LED(3) <= not std_logic(testctr(27));
- LED(2) <= not std_logic(testctr(26));
- LED(1) <= not std_logic(testctr(25));
- LED(0) <= not std_logic(testctr(24));
+ LED(3) <= not led_i(3) or led_off; --std_logic(testctr(27));
+ LED(2) <= not led_i(2) or led_off; --std_logic(testctr(26));
+ LED(1) <= not led_i(1) or led_off; --std_logic(testctr(25));
+ LED(0) <= not led_i(0) or led_off; --std_logic(testctr(24));
-------------------------------------------------------------------------------
-- No trigger/data endpoint included
jspc29 / TOMcat.git / commitdiff