Still occasional reset problems: got_link_ready_i sometimes goes low, indicating link-loss
Dedicated signal introduced for LINK_PHASE (for proper start of 8-bit tx in 16-bit interface) and
TX_DLM_INIT (early warning to tx_control state-machine; 1st byte loss is mended.
--- /dev/null
+../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
<Option name="HDL type" value="VHDL"/>
</Options>
<Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
- <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+ <Options top="trb3_periph_sodaclient"/>
<Source name="source/version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="source/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
+ <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="source/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodaclient"/>
</Source>
<Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="source/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="source/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
<Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.med_sync_define.all;
+use work.soda_components.all;
entity med_ecp3_sfp_sync_down is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0;
--- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
- IS_SYNC_SLAVE : integer := c_NO --select slave mode
- );
- port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
+ generic( SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ port(
+ CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
+ --Internal Connection RX
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
+ CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM_INIT : in std_logic := '0'; --PL!\r
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
end entity;
signal rx_error : std_logic;
signal rst_n : std_logic;
+signal rst : std_logic; -- PL!
signal rx_serdes_rst : std_logic;
signal tx_serdes_rst : std_logic;
signal tx_pcs_rst : std_logic;
signal rx_pcs_rst : std_logic;
signal rst_qd : std_logic;
signal serdes_rst_qd : std_logic;
+signal sd_los_i : std_logic; --PL!
signal rx_los_low : std_logic;
signal lsm_status : std_logic;
signal rx_allow : std_logic;
signal tx_allow_q : std_logic;
signal rx_allow_q : std_logic;
+signal link_phase_S : std_logic; --PL!
signal request_retr_i : std_logic;
signal start_retr_i : std_logic;
signal request_retr_position_i : std_logic_vector(7 downto 0);
SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-rst_n <= not CLEAR;
+--rst_n <= not CLEAR; PL!
+rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out);
gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
hdinn_ch0 => SD_RXD_N_IN,
hdoutp_ch0 => SD_TXD_P_OUT,
hdoutn_ch0 => SD_TXD_N_OUT,
- rxiclk_ch0 => clk_200_i,
+-- rxiclk_ch0 => clk_200_i,
txiclk_ch0 => clk_200_i,
rx_full_clk_ch0 => clk_rx_full,
rx_half_clk_ch0 => clk_rx_half,
);
-- Master does not do bit-locking
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = 1) else x"0000";
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
PROC_ALLOW : process begin
wait until rising_edge(clk_200_i);
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
rx_allow <= '1';
else
rx_allow <= '0';
end if;
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
tx_allow <= '1';
else
tx_allow <= '0';
-------------------------------------------------
-- TX Data
-------------------------------------------------
-THE_TX : tx_control
- port map(
- CLK_200 => clk_200_i,
- CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
-
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
-
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
-
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
-
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => request_retr_position_i, --TODO
-
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
-
- SEND_LINK_RESET_IN => CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
-
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
- );
-
-
+THE_TX : soda_tx_control
+ port map(
+ CLK_200 => clk_200_i,
+ CLK_100 => SYSCLK,
+ RESET_IN => rst, --CLEAR, PL!
+
+ TX_DATA_IN => MED_DATA_IN,
+ TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
+ TX_WRITE_IN => MED_DATAREADY_IN,
+ TX_READ_OUT => MED_READ_OUT,
+
+ TX_DATA_OUT => tx_data,
+ TX_K_OUT => tx_k,
+
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO
+
+ START_RETRANSMIT_IN => start_retr_i, --TODO
+ START_POSITION_IN => request_retr_position_i, --TODO
+\r
+ TX_DLM_INIT => TX_DLM_INIT,
+ SEND_DLM => TX_DLM,
+ SEND_DLM_WORD => TX_DLM_WORD,
+
+ SEND_LINK_RESET_IN => CTRL_OP(15),
+ TX_ALLOW_IN => tx_allow,
+ RX_ALLOW_IN => rx_allow,\r
+ LINK_PHASE_OUT => link_phase_S, --PL!
+
+ DEBUG_OUT => debug_tx_control_i,
+ STAT_REG_OUT => stat_tx_control_i
+);
+
+LINK_PHASE_OUT <= link_phase_S; --PL!
-------------------------------------------------
-- RX Data
-------------------------------------------------
port map(
CLK_200 => clk_200_i,
CLK_100 => SYSCLK,
- RESET_IN => CLEAR,
+ RESET_IN => rst, --CLEAR, PL!
RX_DATA_OUT => MED_DATA_OUT,
RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
STAT_DEBUG <= debug_reg;
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0';
-
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
STAT_OP(14) <= '0';
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 09 11 08:27:01.177" version="8.1" type="IP" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 10:05:44.402" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 09 11 08:26:59.000"/>
- <File name="serdes_sync_downstream.pp" type="pp" modified="2013 09 11 08:26:59.000"/>
- <File name="serdes_sync_downstream.sym" type="sym" modified="2013 09 11 08:26:59.000"/>
- <File name="serdes_sync_downstream.tft" type="tft" modified="2013 09 11 08:26:59.000"/>
- <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 09 11 08:26:59.000"/>
+ <File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 10 02 10:05:42.000"/>
+ <File name="serdes_sync_downstream.pp" type="pp" modified="2013 10 02 10:05:42.000"/>
+ <File name="serdes_sync_downstream.sym" type="sym" modified="2013 10 02 10:05:43.000"/>
+ <File name="serdes_sync_downstream.tft" type="tft" modified="2013 10 01 11:57:48.000"/>
+ <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 10 02 10:05:42.000"/>
+ <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2013 10 01 11:57:48.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=09/11/2013
-Time=08:26:59
+Date=10/02/2013
+Time=10:05:42
[Parameters]
Verilog=0
_tx_data_width1=8
_tx_data_width2=8
_tx_data_width3=8
-_tx_fifo0=DISABLED
+_tx_fifo0=ENABLED
_tx_fifo1=ENABLED
_tx_fifo2=ENABLED
_tx_fifo3=ENABLED
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
CH0_TX_DATA_RATE "FULL"
CH0_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "ENABLED"
+CH0_TX_FIFO "ENABLED"
+CH0_RX_FIFO "DISABLED"
CH0_TDRV "0"
#CH0_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
CH0_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
+INT_ALL "ENABLED"
QD_REFCK2CORE "DISABLED"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
- rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_RXI_CLK_0 => fpsc_vlo,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 09 11 07:50:28.463" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 09:44:25.936" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2013 09 11 07:50:24.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2013 09 11 07:50:24.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2013 09 11 07:50:24.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2013 09 11 07:50:24.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2013 09 11 07:50:24.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2013 09 11 07:50:24.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2013 10 02 09:44:23.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2013 10 02 09:44:23.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2013 10 02 09:44:24.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2013 10 02 09:44:23.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2013 10 02 09:44:23.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2013 10 02 09:44:23.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=09/11/2013
-Time=07:50:24
+Date=10/02/2013
+Time=09:44:23
[Parameters]
Verilog=0
CH0_SSLB "DISABLED"
CH0_SPLBPORTS "DISABLED"
CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
+INT_ALL "ENABLED"
QD_REFCK2CORE "DISABLED"
\r
entity soda_calibration_timer is\r
port(\r
- SYSCLK : in std_logic; -- fabric clock\r
+ SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
\r
begin\r
\r
- packet_fsm_proc : process(SYSCLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)\r
+ packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)\r
begin\r
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
if (RESET='1') then
CALIB_VALID_OUT <= '0';\r
CALIB_TIME_OUT <= (others => '0');
package soda_components is
+ constant c_NOT_IN_SYNC : std_logic := '1';
+ constant c_IN_SYNC : std_logic := '0';
constant c_HUB_CHILDREN : natural range 1 to 4 := 2;
type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic;\r
type t_HUB_DLM_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
--Internal Connection
- LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0');
+ LINK_PHASE_IN : in std_logic := '0';
SODA_CMD_STROBE_IN : in std_logic := '0'; --
START_OF_SUPERBURST : in std_logic := '0';
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ TX_DLM_INIT_OUT : out std_logic := '0'; --PL!
+ LINK_PHASE_IN : in std_logic := '0'; --PL!
+
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
component soda_reply_handler
port(
- SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
component soda_calibration_timer\r
port(\r
- SYSCLK : in std_logic; -- fabric clock\r
+ SODACLK : in std_logic; -- fabric clock\r
RESET : in std_logic; -- synchronous reset\r
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
end component;
component med_ecp3_sfp_sync_down is
- generic(
- SERDES_NUM : integer range 0 to 3 := 0;
--- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO
- IS_SYNC_SLAVE : integer := c_NO --select slave mode
- );
- port(
- CLK : in std_logic; -- _internal_ 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
- CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 0;
+ IS_SYNC_SLAVE : integer := c_NO); --select slave mode
+ port(
+ CLK : in std_logic; -- _internal_ 200 MHz reference clock
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ --Internal Connection TX
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic := '0';
+ --Internal Connection RX
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ MED_DATAREADY_OUT : out std_logic := '0';
+ MED_READ_IN : in std_logic;
+ CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz
+ CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz
+
+ --Sync operation
+ RX_DLM : out std_logic := '0';
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
+ TX_DLM : in std_logic := '0';
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM_INIT : in std_logic := '0'; --PL!\r
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic; --not used
+ SD_REFCLK_N_IN : in std_logic; --not used
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+ --Control Interface
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
+ SCI_READ : in std_logic := '0';
+ SCI_WRITE : in std_logic := '0';
+ SCI_ACK : out std_logic := '0';
+ SCI_NACK : out std_logic := '0';
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
+ );
end component;
component med_ecp3_sfp_sync_up is
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
-
+
--SFP Connection
SD_RXD_P_IN : in std_logic;
SD_RXD_N_IN : in std_logic;
);
end component;
\r
+component soda_tx_control
+ port(
+ CLK_200 : in std_logic;
+ CLK_100 : in std_logic;
+ RESET_IN : in std_logic;
+
+ TX_DATA_IN : in std_logic_vector(15 downto 0);
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
+ TX_WRITE_IN : in std_logic;
+ TX_READ_OUT : out std_logic;
+
+ TX_DATA_OUT : out std_logic_vector( 7 downto 0);
+ TX_K_OUT : out std_logic;
+
+ REQUEST_RETRANSMIT_IN : in std_logic := '0';
+ REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
+
+ START_RETRANSMIT_IN : in std_logic := '0';
+ START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
+ TX_DLM_INIT : in std_logic := '0';
+ SEND_DLM : in std_logic := '0';
+ SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');
+
+ SEND_LINK_RESET_IN : in std_logic := '0';
+ TX_ALLOW_IN : in std_logic := '0';
+ RX_ALLOW_IN : in std_logic := '0';
+ LINK_PHASE_OUT : out std_logic := '0';
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0);
+ STAT_REG_OUT : out std_logic_vector(31 downto 0)
+ );
+end component;\r
+\r
end package;
CLEAR : in std_logic; -- asynchronous reset\r
CLK_EN : in std_logic; \r
--Internal Connection\r
- LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0');
+ LINK_PHASE_IN : in std_logic := '0'; --_vector(1 downto 0) := (others => '0');
SODA_CMD_STROBE_IN : in std_logic := '0'; -- \r
START_OF_SUPERBURST : in std_logic := '0';\r
SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');\r
c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
);\r
signal packet_state_S : packet_state_type := c_IDLE;\r
+ \r
\r
begin\r
\r
TX_DLM_OUT <= soda_pkt_valid_S;\r
\r
\r
- packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S)\r
+ packet_fsm_proc : process(SODACLK)\r
begin\r
if rising_edge(SODACLK) then\r
if (RESET='1') then\r
case packet_state_S is\r
when c_IDLE =>\r
if (START_OF_SUPERBURST='1') then
- if (LINK_PHASE_IN = "00") then\r
- packet_state_S <= c_BST1;
+ if (LINK_PHASE_IN = c_IN_SYNC) then\r
+ packet_state_S <= c_BST1;
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);
else
- packet_state_S <= c_WAIT4BST1;
+ packet_state_S <= c_WAIT4BST1;
+ soda_pkt_valid_S <= '0';
end if;\r
elsif (soda_cmd_strobe_S='1') then\r
- if (LINK_PHASE_IN = "00") then\r
- packet_state_S <= c_CMD1;\r
+ if (LINK_PHASE_IN = c_IN_SYNC) then\r
+ packet_state_S <= c_CMD1;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
else
- packet_state_S <= c_WAIT4CMD1;
+ packet_state_S <= c_WAIT4CMD1;
+ soda_pkt_valid_S <= '0';\r
end if;\r
else
packet_state_S <= c_IDLE;
+ TIME_CAL_OUT <= '0';
+ soda_pkt_valid_S <= '0';
+ soda_pkt_word_S <= (others=>'0');
end if;\r
when c_WAIT4BST1 =>\r
- if (LINK_PHASE_IN = "00") then\r
- packet_state_S <= c_BST1;
- else
- packet_state_S <= c_WAIT4BST1;
- end if;\r
+ packet_state_S <= c_BST1;
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);
when c_BST1 =>\r
packet_state_S <= c_BST2;\r
+ soda_pkt_valid_S <= '0';
when c_BST2 =>\r
packet_state_S <= c_BST3;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= super_burst_nr_S(23 downto 16);
when c_BST3 =>\r
packet_state_S <= c_BST4;\r
+ soda_pkt_valid_S <= '0';
when c_BST4 =>\r
packet_state_S <= c_BST5;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= super_burst_nr_S(15 downto 8);
when c_BST5 =>\r
packet_state_S <= c_BST6;\r
+ soda_pkt_valid_S <= '0';
when c_BST6 =>\r
packet_state_S <= c_BST7;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= super_burst_nr_S(7 downto 0);
when c_BST7 =>\r
packet_state_S <= c_BST8;\r
+ soda_pkt_valid_S <= '0';
when c_BST8 =>\r
if (soda_cmd_strobe_S='0') then\r
packet_state_S <= c_IDLE;\r
else\r
packet_state_S <= c_CMD1;\r
end if;\r
+ soda_pkt_valid_S <= '0';
+ soda_pkt_word_S <= (others=>'0');
when c_WAIT4CMD1 =>\r
- if (LINK_PHASE_IN = "00") then
- packet_state_S <= c_CMD1;\r
- else
- packet_state_S <= c_WAIT4CMD1;
- end if;\r
+ packet_state_S <= c_CMD1;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
when c_CMD1 =>\r
- packet_state_S <= c_CMD2;\r
+ packet_state_S <= c_CMD2;\r
+ soda_pkt_valid_S <= '0';
when c_CMD2 =>\r
- packet_state_S <= c_CMD3;\r
+ packet_state_S <= c_CMD3;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);
when c_CMD3 =>\r
- packet_state_S <= c_CMD4;\r
+ packet_state_S <= c_CMD4;\r
+ soda_pkt_valid_S <= '0';
when c_CMD4 =>\r
- packet_state_S <= c_CMD5;\r
+ packet_state_S <= c_CMD5;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= soda_cmd_word_S(15 downto 8);
when c_CMD5 =>\r
- packet_state_S <= c_CMD6;\r
+ packet_state_S <= c_CMD6;\r
+ soda_pkt_valid_S <= '0';
when c_CMD6 =>\r
- packet_state_S <= c_CMD7;\r
+ packet_state_S <= c_CMD7;\r
+ soda_pkt_valid_S <= '1';
+ soda_pkt_word_S <= soda_cmd_word_S(7 downto 0);
when c_CMD7 =>\r
if (crc_valid_S = '0') then
packet_state_S <= c_ERROR;\r
else
packet_state_S <= c_CMD8;\r
end if;\r
+ soda_pkt_valid_S <= '0';
when c_CMD8 =>
packet_state_S <= c_IDLE;\r
+ soda_pkt_valid_S <= '0';
+ soda_pkt_word_S <= (others=>'0');
when c_ERROR =>
packet_state_S <= c_IDLE;\r
+ soda_pkt_valid_S <= '0';
when others =>\r
packet_state_S <= c_IDLE;\r
+ soda_pkt_valid_S <= '0';
end case;\r
end if;\r
end if;\r
end process;\r
\r
- soda_packet_fill_proc : process(SODACLK, packet_state_S)\r
- begin\r
- if rising_edge(SODACLK) then\r
- case packet_state_S is\r
- when c_IDLE =>\r
- TIME_CAL_OUT <= '0';\r
- soda_pkt_valid_S <= '0';\r
- soda_pkt_word_S <= (others=>'0');\r
- when c_WAIT4BST1 => -- no need to do anything just yet.\r
- when c_BST1 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);\r
- when c_BST2 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_BST3 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= super_burst_nr_S(23 downto 16);\r
- when c_BST4 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_BST5 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= super_burst_nr_S(15 downto 8);\r
- when c_BST6 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_BST7 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= super_burst_nr_S(7 downto 0);\r
- EXPECTED_REPLY_OUT <= super_burst_nr_S(7 downto 0);\r
- when c_BST8 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_WAIT4CMD1 => -- no need to do anything just yet.\r
- when c_CMD1 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);\r
- when c_CMD2 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_CMD3 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);\r
- when c_CMD4 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_CMD5 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= soda_cmd_word_S(15 downto 8);\r
- when c_CMD6 =>\r
- soda_pkt_valid_S <= '0';\r
- when c_CMD7 =>\r
- soda_pkt_valid_S <= '1';\r
- soda_pkt_word_S <= crc_out_S;
- EXPECTED_REPLY_OUT <= crc_out_S;
- TIME_CAL_OUT <= '1';\r
- when c_CMD8 =>
- TIME_CAL_OUT <= '0';\r
- soda_pkt_valid_S <= '0';\r
- when others =>\r
- TIME_CAL_OUT <= '0';\r
- soda_pkt_valid_S <= '0';\r
- soda_pkt_word_S <= (others=>'0');\r
- end case; \r
- end if;\r
- end process;\r
+ --soda_packet_fill_proc : process(SODACLK, packet_state_S)\r
+ --begin\r
+ --if rising_edge(SODACLK) then\r
+ --case packet_state_S is\r
+ --when c_IDLE =>\r
+ --TIME_CAL_OUT <= '0';\r
+ --soda_pkt_valid_S <= '0';\r
+ --soda_pkt_word_S <= (others=>'0');\r
+ --when c_WAIT4BST1 => -- no need to do anything just yet.\r
+ --when c_BST1 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);\r
+ --when c_BST2 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_BST3 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= super_burst_nr_S(23 downto 16);\r
+ --when c_BST4 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_BST5 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= super_burst_nr_S(15 downto 8);\r
+ --when c_BST6 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_BST7 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= super_burst_nr_S(7 downto 0);\r
+ --EXPECTED_REPLY_OUT <= super_burst_nr_S(7 downto 0);\r
+ --when c_BST8 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_WAIT4CMD1 => -- no need to do anything just yet.\r
+ --when c_CMD1 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);\r
+ --when c_CMD2 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_CMD3 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);\r
+ --when c_CMD4 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_CMD5 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= soda_cmd_word_S(15 downto 8);\r
+ --when c_CMD6 =>\r
+ --soda_pkt_valid_S <= '0';\r
+ --when c_CMD7 =>\r
+ --soda_pkt_valid_S <= '1';\r
+ --soda_pkt_word_S <= crc_out_S;
+ --EXPECTED_REPLY_OUT <= crc_out_S;
+ --TIME_CAL_OUT <= '1';\r
+ --when c_CMD8 =>
+ --TIME_CAL_OUT <= '0';\r
+ --soda_pkt_valid_S <= '0';\r
+ --when others =>\r
+ --TIME_CAL_OUT <= '0';\r
+ --soda_pkt_valid_S <= '0';\r
+ --soda_pkt_word_S <= (others=>'0');\r
+ --end case; \r
+ --end if;\r
+ --end process;\r
\r
\r
crc_gen_proc : process(SODACLK, packet_state_S)\r
entity soda_reply_handler is
port(
- SYSCLK : in std_logic; -- fabric clock
+ SODACLK : in std_logic; -- fabric clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
begin
- reply_fsm_proc : process(SYSCLK)
+ reply_fsm_proc : process(SODACLK)
begin
- if rising_edge(SYSCLK) then\r
+ if rising_edge(SODACLK) then\r
if (RESET='1') then
REPLY_VALID_OUT <= '0';
REPLY_OK_OUT <= '0';
SODA_BURST_PULSE_IN : in std_logic := '0'; --
RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic;
+ RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ TX_DLM_INIT_OUT : out std_logic := '0'; --PL!
+ LINK_PHASE_IN : in std_logic := '0'; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
architecture Behavioral of soda_source is
--SODA
- signal link_phase_S : std_logic_vector(1 downto 0) := (others => '0');
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
signal soda_cmd_strobe_S : std_logic := '0';
signal soda_cmd_strobe_sodaclk_S : std_logic := '0';
CLEAR => '0',
CLK_EN => CLK_EN,
--Internal Connection
- LINK_PHASE_IN => link_phase_S,
+ LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL!
SODA_CMD_STROBE_IN => soda_cmd_strobe_sodaclk_S,
START_OF_SUPERBURST => start_of_superburst_S,
SUPER_BURST_NR_IN => super_burst_nr_S,
src_reply_handler : soda_reply_handler
port map(
- SYSCLK => SODACLK,
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => '1',
src_calibration_timer : soda_calibration_timer
port map(
- SYSCLK => SODACLK,
+ SODACLK => SODACLK,
RESET => RESET,
CLEAR => '0',
CLK_EN => '1',
end if;
end if;
end process;
+\r
+\r
+\r
-----------------------------------------------------------
--- Phase fsm for 16-bit transmissions --
+-- TX_DLM_INIT for media-interface transmissions --
-----------------------------------------------------------
- phase_fsm_proc : process(SODACLK)
- begin
- if rising_edge(SODACLK) then
- if( RESET = '1' ) then
- link_phase_S <= (0 => '1', others => '0');
- elsif (link_phase_S < 1) then
- link_phase_S <= link_phase_S + 1;
- else
- link_phase_S <= (others => '0');
- end if;
- end if;
+ tx_dlm_init_proc : process (SODACLK, start_of_superburst_S, soda_cmd_strobe_S)\r
+ begin\r
+ if( RESET = '1' ) then \r
+ TX_DLM_INIT_OUT <= '0';\r
+ elsif ((start_of_superburst_S='1' or soda_cmd_strobe_S='1') and LINK_PHASE_IN=c_IN_SYNC) then\r
+ TX_DLM_INIT_OUT <= '1';\r
+ elsif rising_edge(SODACLK) then\r
+ if (start_of_superburst_S='1' or soda_cmd_strobe_S='1') then
+ TX_DLM_INIT_OUT <= '1';\r
+ else\r
+ TX_DLM_INIT_OUT <= '0';
+ end if;\r
+ end if;\r
end process;
+\r
+ \r
+\r
+-----------------------------------------------------------
+-- Phase fsm for 16-bit transmissions --
+-----------------------------------------------------------
+-- phase_fsm_proc : process(SODACLK)
+-- begin
+-- if rising_edge(SODACLK) then
+-- if( RESET = '1' ) then
+-- link_phase_S <= '0'; -- (0 => '1', others => '0');
+-- elsif (link_phase_S='0') then
+-- link_phase_S <= '1';
+-- else
+-- link_phase_S <= '0'; --(others => '0');
+-- end if;
+-- end if;
+-- end process;
---------------------------------------------------------
-- RegIO Statemachine
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
--- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
--- LED_YELLOW <= '1';
--- LED_GREEN <= not med_stat_op(9);
--- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
- LED_ORANGE <= soda_leds(0);
- LED_YELLOW <= soda_leds(1);
- LED_GREEN <= soda_leds(2);
- LED_RED <= soda_leds(3);
+ LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+ LED_YELLOW <= soda_leds(0); --'1';
+ LED_GREEN <= not med_stat_op(9);
+ LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+-- LED_ORANGE <= soda_leds(0);
+-- LED_YELLOW <= soda_leds(1);
+-- LED_GREEN <= soda_leds(2);
+-- LED_RED <= soda_leds(3);
---------------------------------------------------------------------------
-- DEBUG\r
--SODA
signal soda_ack : std_logic;
--- signal soda_nack : std_logic;
signal soda_write : std_logic;
signal soda_read : std_logic;
signal soda_data_in : std_logic_vector(31 downto 0);
signal soda_data_out : std_logic_vector(31 downto 0);
signal soda_addr : std_logic_vector(3 downto 0);
signal soda_leds : std_logic_vector(3 downto 0);
+\r
--TDC
signal hit_in_i : std_logic_vector(63 downto 0);
signal rx_dlm_i : std_logic;
signal tx_dlm_word : std_logic_vector(7 downto 0);
signal rx_dlm_word : std_logic_vector(7 downto 0);
+ signal tx_dlm_init_S : std_logic; --PL!
+ signal link_phase_S : std_logic; --PL!
--SODA
signal SOB_S : std_logic := '0';
RX_DLM => rx_dlm_i,
RX_DLM_WORD => rx_dlm_word,
TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
+ TX_DLM_WORD => tx_dlm_word,\r
+ TX_DLM_INIT => tx_dlm_init_S, --PL!\r
+ LINK_PHASE_OUT => link_phase_S, --PL!
--SFP Connection
SD_RXD_P_IN => SERDES_ADDON_RX(0),
SD_RXD_N_IN => SERDES_ADDON_RX(1),
RX_DLM_IN => rx_dlm_i,
TX_DLM_OUT => tx_dlm_i,
TX_DLM_WORD_OUT => tx_dlm_word,
-
+ TX_DLM_INIT_OUT => tx_dlm_init_S,
+ LINK_PHASE_IN => link_phase_S,
SODA_DATA_IN => soda_data_in,
SODA_DATA_OUT => soda_data_out,
SODA_ADDR_IN => soda_addr,
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
--- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
--- LED_YELLOW <= '1';
--- LED_GREEN <= not med_stat_op(9);
--- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
- LED_ORANGE <= soda_leds(0);
- LED_YELLOW <= soda_leds(1);
- LED_GREEN <= soda_leds(2);
- LED_RED <= soda_leds(3);
+ LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
+ LED_YELLOW <= soda_leds(0); --'1';
+ LED_GREEN <= not med_stat_op(9);
+ LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+-- LED_ORANGE <= soda_leds(0);
+-- LED_YELLOW <= soda_leds(1);
+-- LED_GREEN <= soda_leds(2);
+-- LED_RED <= soda_leds(3);
---------------------------------------------------------------------------
-- Test Connector
jspc29 / soda.git / commitdiff