added missing files

diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl
index a496b8c9fadb900ad38820a79d156d1ba2c93d24..a8cb49eea5d9572cdd8de67f2d929761f6968284 100755 (executable)
--- a/compile_frankfurt.pl
+++ b/compile_frankfurt.pl
@@ -13,10 +13,9 @@ use Data::Dumper;
 use warnings;
 use strict;
 
-#my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/';
-my $lattice_path = '/d/sugar/lattice/diamond/1.1';
-#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux';
-my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/';
+
+my $lattice_path = '/d/jspc29/lattice/diamond/1.4';
+my $synplify_path = '/d/jspc29/lattice/synplify/D-2010.03/';
 
 use FileHandle;
 

diff --git a/constraints_pexor.lpf b/constraints_pexor.lpf
index e51feffceb3a4c333b921590e6762a95d8e41283..d1769dc07f1ec7e6f7a6a7d8a49a56307ecc6337 100644 (file)
--- a/constraints_pexor.lpf
+++ b/constraints_pexor.lpf
@@ -5,6 +5,8 @@ BLOCK RD_DURING_WR_PATHS ;
 
 SYSCONFIG MCCLK_FREQ=33 ;
 
+GSR_NET NET "pll_locked";
+
 #########################################
 # Clock Constraints
 #########################################

diff --git a/design/cores/fifo_dc_64x512.lpc b/design/cores/fifo_dc_64x512.lpc
new file mode 100644 (file)
index 0000000..0ded239
--- /dev/null
+++ b/design/cores/fifo_dc_64x512.lpc
@@ -0,0 +1,48 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA115EP1
+PartName=LFSCM3GA115EP1-5FC1152C
+SpeedGrade=5
+Package=FCBGA1152
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.4
+ModuleName=fifo_dc_64x512
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/03/2011
+Time=15:28:29
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=1024
+RWidth=32
+WDepth=512
+WWidth=64
+regout=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=500
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0

diff --git a/design/cores/fifo_dc_64x512.vhd b/design/cores/fifo_dc_64x512.vhd
new file mode 100644 (file)
index 0000000..dc2f19d
--- /dev/null
+++ b/design/cores/fifo_dc_64x512.vhd
@@ -0,0 +1,225 @@
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module  Version: 5.4
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n fifo_dc_64x512 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 64 -rwidth 32 -no_enable -pe 10 -pf 500 -e 
+
+-- Fri Jun  3 15:28:29 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_dc_64x512 is
+    port (
+        Data: in  std_logic_vector(63 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; 
+        AlmostFull: out  std_logic);
+end fifo_dc_64x512;
+
+architecture Structure of fifo_dc_64x512 is
+
+    -- internal signal declarations
+    signal scuba_vhi: std_logic;
+    signal Empty_int: std_logic;
+    signal Full_int: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component FIFO16KA
+    -- synopsys translate_off
+        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
+                FULLPOINTER : in std_logic_vector(14 downto 0); 
+                AFPOINTER1 : in std_logic_vector(14 downto 0); 
+                AEPOINTER1 : in std_logic_vector(14 downto 0); 
+                AFPOINTER : in std_logic_vector(14 downto 0); 
+                AEPOINTER : in std_logic_vector(14 downto 0); 
+                CSDECODE_R : in std_logic_vector(1 downto 0); 
+                CSDECODE_W : in std_logic_vector(1 downto 0); 
+                RESETMODE : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+    -- synopsys translate_on
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            FULLI: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; EMPTYI: in  std_logic; 
+            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
+            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
+            RST: in  std_logic; RPRST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic; 
+            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
+            FF: out  std_logic);
+    end component;
+    attribute FULLPOINTER1 : string; 
+    attribute FULLPOINTER : string; 
+    attribute AFPOINTER1 : string; 
+    attribute AFPOINTER : string; 
+    attribute AEPOINTER1 : string; 
+    attribute AEPOINTER : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
+    attribute CSDECODE_R : string; 
+    attribute CSDECODE_W : string; 
+    attribute DATA_WIDTH_R : string; 
+    attribute DATA_WIDTH_W : string; 
+    attribute FULLPOINTER1 of fifo_dc_64x512_0_1 : label is "0b011111111000001";
+    attribute FULLPOINTER of fifo_dc_64x512_0_1 : label is "0b011111111100001";
+    attribute AFPOINTER1 of fifo_dc_64x512_0_1 : label is "0b011111001000001";
+    attribute AFPOINTER of fifo_dc_64x512_0_1 : label is "0b011111001100001";
+    attribute AEPOINTER1 of fifo_dc_64x512_0_1 : label is "0b000000010111111";
+    attribute AEPOINTER of fifo_dc_64x512_0_1 : label is "0b000000010101111";
+    attribute RESETMODE of fifo_dc_64x512_0_1 : label is "ASYNC";
+    attribute REGMODE of fifo_dc_64x512_0_1 : label is "NOREG";
+    attribute CSDECODE_R of fifo_dc_64x512_0_1 : label is "0b11";
+    attribute CSDECODE_W of fifo_dc_64x512_0_1 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo_dc_64x512_0_1 : label is "18";
+    attribute DATA_WIDTH_W of fifo_dc_64x512_0_1 : label is "36";
+    attribute FULLPOINTER1 of fifo_dc_64x512_1_0 : label is "0b000000000000000";
+    attribute FULLPOINTER of fifo_dc_64x512_1_0 : label is "0b111111111111111";
+    attribute AFPOINTER1 of fifo_dc_64x512_1_0 : label is "0b000000000000000";
+    attribute AFPOINTER of fifo_dc_64x512_1_0 : label is "0b111111111111111";
+    attribute AEPOINTER1 of fifo_dc_64x512_1_0 : label is "0b000000000000000";
+    attribute AEPOINTER of fifo_dc_64x512_1_0 : label is "0b111111111111111";
+    attribute RESETMODE of fifo_dc_64x512_1_0 : label is "ASYNC";
+    attribute REGMODE of fifo_dc_64x512_1_0 : label is "NOREG";
+    attribute CSDECODE_R of fifo_dc_64x512_1_0 : label is "0b11";
+    attribute CSDECODE_W of fifo_dc_64x512_1_0 : label is "0b11";
+    attribute DATA_WIDTH_R of fifo_dc_64x512_1_0 : label is "18";
+    attribute DATA_WIDTH_W of fifo_dc_64x512_1_0 : label is "36";
+    attribute syn_keep : boolean;
+
+begin
+    -- component instantiation statements
+    fifo_dc_64x512_0_1: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001", 
+        AFPOINTER1=> "011111001000001", AFPOINTER=> "011111001100001", 
+        AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  18, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(32), DI19=>Data(33), DI20=>Data(34), 
+            DI21=>Data(35), DI22=>Data(36), DI23=>Data(37), 
+            DI24=>Data(38), DI25=>Data(39), DI26=>Data(40), 
+            DI27=>Data(41), DI28=>Data(42), DI29=>Data(43), 
+            DI30=>Data(44), DI31=>Data(45), DI32=>Data(46), 
+            DI33=>Data(47), DI34=>Data(48), DI35=>Data(49), 
+            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
+            EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, 
+            WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
+            RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), 
+            DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), 
+            DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), 
+            DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), 
+            DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open, 
+            DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open, 
+            DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, 
+            DO32=>open, DO33=>open, DO34=>open, DO35=>open, 
+            EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull, 
+            FF=>Full_int);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo_dc_64x512_1_0: FIFO16KA
+        -- synopsys translate_off
+        generic map (FULLPOINTER1=> "000000000000000", FULLPOINTER=> "111111111111111", 
+        AFPOINTER1=> "000000000000000", AFPOINTER=> "111111111111111", 
+        AEPOINTER1=> "000000000000000", AEPOINTER=> "111111111111111", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
+        CSDECODE_W=> "11", DATA_WIDTH_R=>  18, DATA_WIDTH_W=>  36)
+        -- synopsys translate_on
+        port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20), 
+            DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24), 
+            DI7=>Data(25), DI8=>Data(26), DI9=>Data(27), DI10=>Data(28), 
+            DI11=>Data(29), DI12=>Data(30), DI13=>Data(31), 
+            DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, 
+            DI17=>scuba_vlo, DI18=>Data(50), DI19=>Data(51), 
+            DI20=>Data(52), DI21=>Data(53), DI22=>Data(54), 
+            DI23=>Data(55), DI24=>Data(56), DI25=>Data(57), 
+            DI26=>Data(58), DI27=>Data(59), DI28=>Data(60), 
+            DI29=>Data(61), DI30=>Data(62), DI31=>Data(63), 
+            DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, 
+            DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, 
+            CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>scuba_vhi, 
+            CSR1=>scuba_vhi, WE=>WrEn, RE=>RdEn, CLKW=>WrClock, 
+            CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(18), 
+            DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), 
+            DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), 
+            DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open, 
+            DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open, 
+            DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open, 
+            DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open, 
+            DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, 
+            DO35=>open, EF=>open, AEF=>open, AFF=>open, FF=>open);
+
+    Empty <= Empty_int;
+    Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_dc_64x512 is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/design/dma_core.vhd b/design/dma_core.vhd
index ba254a8588953f30d33598358d83557bd284846e..63e594b49408956498c5f9790f6e6af6843af493 100644 (file)
--- a/design/dma_core.vhd
+++ b/design/dma_core.vhd
@@ -20,10 +20,12 @@ entity dma_core is
     DMA_ADDR_WR_IN       : in  std_logic;
     DMA_CONTROL_IN       : in  std_logic_vector(31 downto 0); --0x702 write
         --0: activate
-        --1: reset dma handler (not implemented)
+        --1: reset dma handler 
     DMA_STATUS_OUT       : out std_logic_vector(31 downto 0); --0x702 read
         --0: active
         --1: buffer full - waiting for reactivation
+        --2: dma finished - set when active goes down, cleared with dma reset
+        --3: network time-out - set after 4 seconds without data, cleared with dma reset
         --31..8: data length in 32bit words
     DMA_CONFIG_IN        : in  std_logic_vector(31 downto 0); --0x703
         --9..0 max burst size
@@ -137,6 +139,7 @@ architecture dma_core_arch of dma_core is
   signal dma_start_address_i      : std_logic_vector(31 downto 0) := (others => '0');
   signal new_buffer_available     : std_logic := '0';
   signal dma_fifo_state           : std_logic_vector(3 downto 0) := (others => '0');
+  signal dma_finished             : std_logic;
 
   type dma_state_t is (INACTIVE, ACTIVE, WAIT_1, WAIT_2, WAIT_3, ENABLE, WORKING, DMA_RESET);
   signal current_dma_state : dma_state_t;
@@ -149,6 +152,8 @@ architecture dma_core_arch of dma_core is
   signal df_full_q          : std_logic;
   signal next_df_write_en   : std_logic;
 
+  signal timer : unsigned(31 downto 0);
+  
 begin
 
 
@@ -233,12 +238,13 @@ API_READ_OUT <= buf_API_READ_OUT;
             end if;
           when DMA_RESET =>
             reset_dma_fifo        <= '1';
-            DMA_STATUS_OUT(1)     <= '1';
+            DMA_STATUS_OUT(1)     <= '0';
             current_dma_state     <= INACTIVE;
         end case;
 
         if RESET_IN = '1' then
-          current_dma_state <= INACTIVE;
+          current_dma_state     <= INACTIVE;
+          DMA_STATUS_OUT(1)     <= '0';
         end if;
 
         if DMA_CONTROL_IN(1) = '1' then
@@ -391,11 +397,17 @@ PROC_COPY_DATA : process(CLK_IN)
 
           when LAST_WORD =>
             copy_state_bits <= "10";
-            tx_data_in               <= x"888888888";
-            tx_wr_en                 <= copy_length(0); --write padding
-            tx_fifo_padding          <= x"8";
-            tx_length_wr_en          <= '1';
-            copy_state               <= IDLE;
+            if copy_length = to_unsigned(2,10) then   --prevent burst size of 1
+              tx_data_in               <= x"099999999";
+              tx_wr_en                 <= '1';
+              copy_length              <= copy_length + to_unsigned(1,10);
+            else
+              tx_data_in               <= x"888888888";
+              tx_wr_en                 <= copy_length(0); --write padding
+              tx_fifo_padding          <= x"8";
+              tx_length_wr_en          <= '1';
+              copy_state               <= IDLE;
+            end if;
 
           when BUFFER_FULL_WAIT =>
             copy_state_bits          <= "11";
@@ -627,6 +639,17 @@ PROC_BUSY : process(CLK_IN)
     end if;
   end process;
 
+PROC_FINISHED : process
+  begin
+    wait until rising_edge(CLK_IN);
+    if reset_i = '1' or (reset_dma_fifo = '1' and finished_sys = '0') then  
+      dma_finished <= '0';
+    elsif finished_sys = '1' then
+      dma_finished <= '1';
+    end if;
+  end process;
+ 
+  
 --Buffer in RAM is full
 PROC_BUFFER_FULL : process(CLK_IN)
   begin
@@ -641,7 +664,11 @@ PROC_BUFFER_FULL : process(CLK_IN)
 
 
 DMA_STATUS_OUT(0)           <= busy;
-DMA_STATUS_OUT(7 downto 2)  <= (others => '0');
+DMA_STATUS_OUT(2)           <= dma_finished;
+DMA_STATUS_OUT(3)           <= timer(30);
+DMA_STATUS_OUT(7 downto 4)  <= (others => '0');
+
+
 PROC_STATUS_OUT : process(CLK_IN)
   begin
     if rising_edge(CLK_IN) then
@@ -649,6 +676,18 @@ PROC_STATUS_OUT : process(CLK_IN)
     end if;
   end process;
 
+PROC_TIMER : process
+  begin
+    wait until rising_edge(CLK_IN);
+    if reset_i = '1' or API_DATAREADY_IN = '1' then
+      timer <= (others => '0');
+    elsif timer(30) = '1' then
+      null;
+    elsif busy = '1' and API_DATAREADY_IN = '0' then
+      timer <= timer + 1;
+    end if;
+  end process;
+  
 -----------------------------------------------------------------------
 -- RX Path
 -----------------------------------------------------------------------
@@ -749,7 +788,7 @@ STATUS_REG_OUT(127 downto 96)<= std_logic_vector(current_address);
 
 
 STATUS_REG_OUT(131 downto 128) <= dma_fifo_state;
-STATUS_REG_OUT(132)            <= '0';
+STATUS_REG_OUT(132)            <= reset_i;
 STATUS_REG_OUT(133)            <= buffer_full;
 STATUS_REG_OUT(134)            <= reset_dma_fifo;
 STATUS_REG_OUT(135)            <= rden_dma_fifo;

diff --git a/design/tb_dma_core.vhd b/design/tb_dma_core.vhd
new file mode 100644 (file)
index 0000000..d2f3fe1
--- /dev/null
+++ b/design/tb_dma_core.vhd
@@ -0,0 +1,252 @@
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.pcie_components.all;
+use work.version.all;
+
+entity tb_dma_core is
+end entity;
+
+
+
+architecture tbarch of tb_dma_core is
+
+component dma_core is
+  port(
+    RESET_IN       : in  std_logic;
+    CLK_IN         : in  std_logic;
+    CLK_125_IN     : in  std_logic;
+
+    DMA_DATA_IN    : in  std_logic_vector(31 downto 0); --0x700
+    DMA_LENGTH_WR_IN     : in  std_logic;
+    DMA_ADDR_WR_IN     : in  std_logic;
+    DMA_CONTROL_IN       : in  std_logic_vector(31 downto 0); --0x702 write
+        --0: activate
+        --31..24: max burst size, 32 bit words
+    DMA_STATUS_OUT       : out std_logic_vector(31 downto 0); --0x702 read
+        --0: active
+        --1; buffer full - waiting
+        --31..8: data length in 32bit words
+    DMA_CONFIG_IN        : in  std_logic_vector(31 downto 0); --0x703
+        --7..0 max burst size
+
+    API_RUNNING_IN       : in  std_logic;
+    API_DATA_IN          : in  std_logic_vector(15 downto 0);
+    API_PACKET_NUM_IN    : in  std_logic_vector(2 downto 0);
+    API_TYP_IN           : in  std_logic_vector(2 downto 0);
+    API_DATAREADY_IN     : in  std_logic;
+    API_READ_OUT         : out std_logic;
+
+    REQUESTOR_ID_IN      : in  std_logic_vector(15 downto 0);
+
+    TX_ST_OUT            : out std_logic;                     --tx first word
+    TX_END_OUT           : out std_logic;                     --tx last word
+    TX_DWEN_OUT          : out std_logic;                     --tx use only upper 32 bit
+    TX_DATA_OUT          : out std_logic_vector(63 downto 0); --tx data out
+    TX_REQ_OUT           : out std_logic;                     --tx request out
+    TX_RDY_IN            : in  std_logic;                     --tx arbiter can read
+    TX_VAL_IN            : in  std_logic;                     --tx data is valid
+    TX_CA_PH_IN          : in  std_logic_vector(8 downto 0);  --header credit for write
+    TX_CA_PD_IN          : in  std_logic_vector(12 downto 0); --data credits in 32 bit words
+    TX_CA_NPH_IN         : in  std_logic_vector(8 downto 0);  --header credit for read
+
+    RX_CR_CPLH_OUT       : out std_logic;
+    RX_CR_CPLD_OUT       : out std_logic_vector(7 downto 0);
+    UNEXP_CMPL_OUT       : out std_logic;
+    RX_ST_IN             : in  std_logic;
+    RX_END_IN            : in  std_logic;
+    RX_DWEN_IN           : in  std_logic;
+    RX_DATA_IN           : in  std_logic_vector(63 downto 0);
+    DEBUG_FIFO_DATA_OUT  : out std_logic_vector(63 downto 0);
+    DEBUG_FIFO_EMPTY_OUT : out std_logic_vector(1 downto 0);
+    DEBUG_FIFO_READ_IN   : in  std_logic_vector(1 downto 0);
+
+    DEBUG_OUT            : out std_logic_vector(31 downto 0)
+
+    );
+end component;
+
+  signal clk : std_logic := '1';
+  signal clk_125 : std_logic := '1';
+  signal reset   : std_logic := '1';
+
+  signal dma_control : std_logic_vector(31 downto 0) := (others => '0');
+  signal dma_config  : std_logic_vector(31 downto 0) := x"00000010";
+  signal api_running : std_logic := '0';
+  signal api_data    : std_logic_vector(15 downto 0) := (others => '0');
+  signal api_dataready : std_logic := '0';
+  signal api_read      : std_logic := '0';
+  signal tx_rdy        : std_logic := '0';
+  signal tx_ca_ph      : std_logic_vector(8 downto 0) := "001000000";
+  signal tx_ca_pd      : std_logic_vector(12 downto 0) := "0000010000000";
+  signal tx_ca_nph     : std_logic_vector(8 downto 0) := "001000000";
+  signal tx_req        : std_logic := '0';
+
+  signal dma_data_i    : std_logic_vector(31 downto 0) := x"00000000";
+  signal dma_addr_wr_i : std_logic := '0';
+  signal dma_length_wr_i : std_logic := '0';
+  signal dma_status    : std_logic_vector(31 downto 0);
+
+  signal dbf_read      : std_logic_vector(1 downto 0);
+
+begin
+
+  reset <= '0' after 100 ns;
+  clk   <= not clk after 3.333 ns;
+  clk_125 <= not clk_125 after 4 ns;
+
+
+
+  THE_UT: dma_core
+    port map(
+      RESET_IN        => reset,
+      CLK_IN          => clk,
+      CLK_125_IN      => clk_125,
+
+      DMA_DATA_IN       => dma_data_i,
+      DMA_LENGTH_WR_IN  => dma_length_wr_i,
+      DMA_ADDR_WR_IN    => dma_addr_wr_i,
+      DMA_CONTROL_IN    => dma_control,
+      DMA_STATUS_OUT    => dma_status,
+      DMA_CONFIG_IN     => dma_config,
+
+      API_RUNNING_IN    => api_running,
+      API_DATA_IN       => api_data,
+      API_PACKET_NUM_IN => (others => '0'),
+      API_TYP_IN        => (others => '0'),
+      API_DATAREADY_IN  => api_dataready,
+      API_READ_OUT      => api_read,
+
+      REQUESTOR_ID_IN   => x"affe",
+
+      TX_ST_OUT         => open,
+      TX_END_OUT        => open,
+      TX_DWEN_OUT       => open,
+      TX_DATA_OUT       => open,
+      TX_REQ_OUT        => tx_req,
+      TX_RDY_IN         => tx_rdy,
+      TX_VAL_IN         => '1',
+      TX_CA_PH_IN       => tx_ca_ph,
+      TX_CA_PD_IN       => tx_ca_pd,
+      TX_CA_NPH_IN      => tx_ca_nph,
+
+      RX_CR_CPLH_OUT    => open,
+      RX_CR_CPLD_OUT    => open,
+      UNEXP_CMPL_OUT    => open,
+      RX_ST_IN          => '0',
+      RX_END_IN         => '0',
+      RX_DWEN_IN        => '0',
+      RX_DATA_IN        => (others => '0'),
+      DEBUG_FIFO_READ_IN=> dbf_read,
+      DEBUG_OUT         => open
+      );
+
+  process
+    begin
+      dbf_read <= "00";
+      wait for 6000 ns;
+      wait until rising_edge(clk);
+      dbf_read <= "01";
+      wait until rising_edge(clk);
+      dbf_read <= "00";
+      wait for 100 ns;
+      wait until rising_edge(clk);
+      dbf_read <= "01";
+      wait until rising_edge(clk);
+      dbf_read <= "00";
+      wait for 100 ns;
+      wait until rising_edge(clk);
+      dbf_read <= "01";
+      wait until rising_edge(clk);
+      dbf_read <= "00";
+      wait for 100 ns;
+      wait until rising_edge(clk);
+      dbf_read <= "01";
+      wait until rising_edge(clk);
+      dbf_read <= "00";
+      wait for 100 ns;
+    end process;
+
+  process
+    variable n : integer := 0;
+    begin
+      wait until api_running = '1';
+      wait until rising_edge(clk); wait for 1 ns;
+      wait for 50 ns;
+      
+      wait until rising_edge(clk); wait for 1 ns;
+      dma_data_i    <=  x"10000000";
+      dma_addr_wr_i <= '1';
+      wait until rising_edge(clk); wait for 1 ns;
+      dma_addr_wr_i <= '0';
+      wait until rising_edge(clk); wait for 1 ns;
+      dma_data_i    <= x"00000019";
+      dma_length_wr_i <= '1';
+      wait until rising_edge(clk); wait for 1 ns;
+      dma_length_wr_i <= '0';
+      wait until rising_edge(clk); wait for 1 ns;      
+      wait for 100 ns;
+      buffer_loop: while dma_status(0) = '1' loop
+        wait until dma_status(0) = '0' or dma_status(1) = '1';
+        if dma_status(0) = '1' then
+          wait for 100 ns;
+          wait until rising_edge(clk); wait for 1 ns;
+          dma_data_i    <=  std_logic_vector(to_unsigned(n,4)) & x"0000000";
+          dma_addr_wr_i <= '1';
+          wait until rising_edge(clk); wait for 1 ns;
+          dma_addr_wr_i <= '0';
+          wait until rising_edge(clk); wait for 1 ns;
+          dma_data_i    <= x"00000019";
+          dma_length_wr_i <= '1';
+          wait until rising_edge(clk); wait for 1 ns;
+          dma_length_wr_i <= '0';
+          wait until rising_edge(clk); wait for 1 ns;
+          n := n + 1;
+        end if;
+      end loop;  
+      wait for 50 ns;
+   end process;
+
+
+  process
+    variable n : integer := 0;
+    begin
+
+      wait for 1 us;
+      wait until rising_edge(clk); wait for 1 ns;
+      api_running <= '1';
+      wait for 100 ns;
+      wait until rising_edge(clk); wait for 1 ns;
+      write_loop : for i in 0 to (47*5) loop
+        api_dataready <= '1';
+        api_data      <= std_logic_vector(to_unsigned(i,8)) & std_logic_vector(to_unsigned(i,8));
+--         if i = 34 then       api_running   <= '0';  end if;
+        if api_read = '0' then wait until api_read = '1'; end if;
+--         wait until rising_edge(clk); wait for 1 ns;
+--         api_dataready <= '0';
+        wait until rising_edge(clk); wait for 1 ns;
+      end loop;
+      api_dataready <= '0';
+      wait for 50 ns; wait until rising_edge(clk); wait for 1 ns;
+      api_running   <= '0';
+      wait until rising_edge(clk); wait for 1 ns;
+      wait for 3 us;
+--       n := n + 3;
+     end process;
+
+  process
+    begin
+      wait until tx_req = '1';
+      wait for 50 ns;
+      wait until rising_edge(clk_125); wait for 1 ns;
+      tx_rdy <= '1';
+      wait until rising_edge(clk_125); wait for 1 ns;
+      tx_rdy <= '0';
+    end process;
+
+
+end architecture;
\ No newline at end of file

diff --git a/entities.txt b/entities.txt
new file mode 100644 (file)
index 0000000..7807535
--- /dev/null
+++ b/entities.txt
@@ -0,0 +1,29 @@
+pexor2pci_simpledma_sfp
+  UR_gen
+  ant_pexor
+  dma_adapter
+    dma_ca
+    dma_ctrl
+    dma_rx_fifo
+    dma_tx_fifo
+      tx_cpld_fifo
+      tx_fifo
+    dma_wbs
+  ip_crpr_arb
+  ip_rx_crpr
+  ip_tx_arbiter
+  pciexp2
+  pcs_sfp
+  sfp_control
+  simple_dma_core
+    simpledma_fifo
+  wb_arb
+  wb_tlc
+    wb_intf
+    wb_tlc_cpld
+    wb_tlc_cpld_fifo
+    wb_tlc_cr
+    wb_tlc_dec
+    wb_tlc_req_fifo
+  wbs_sfp_dpm
+    sfp_dpm
\ No newline at end of file

diff --git a/pexor.p2t b/pexor.p2t
index 2c0fe532b5db3d3d3909ca03b3c7c8d35b7d57bb..e1f3bc590a90983bba1f058ef96dc9626c376919 100644 (file)
--- a/pexor.p2t
+++ b/pexor.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 8
+-t 13
 -c 1
 -e 2
 -m nodelist.txt
@@ -18,4 +18,3 @@
 # -e 0
 #
 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
-

diff --git a/pexor.prj b/pexor.prj
index 523f55a9aad22a1a83304e76709c4746647ef854..04bc8ca8b5e6b31e973d8a6fc10b239ec522d3a2 100644 (file)
--- a/pexor.prj
+++ b/pexor.prj
@@ -163,7 +163,7 @@ set_option -fanout_limit 100
 set_option -disable_io_insertion 0
 set_option -retiming 0
 set_option -pipe 0
-# set_option -force_gsr auto
+#set_option -force_gsr 
 set_option -force_gsr false
 set_option -fixgatedclocks 3
 set_option -fixgeneratedclocks 3

diff --git a/pexor.vhd b/pexor.vhd
index d05cab846a74527f547d0bebc74b5f346b48d588..1f5b86bd536250dd9537759a70b93aa277a8a79b 100644 (file)
--- a/pexor.vhd
+++ b/pexor.vhd
@@ -48,8 +48,8 @@ entity pexor is
     --Bus\r
     ANT          : inout std_logic_vector(26 downto 1);\r
     --PCIe Control\r
-    PCIE_RX      : in    std_logic_vector(7 downto 0);\r
-    PCIE_TX      : out   std_logic_vector(7 downto 0);\r
+--     PCIE_RX      : in    std_logic_vector(7 downto 0);\r
+--     PCIE_TX      : out   std_logic_vector(7 downto 0);\r
     X1           : in    std_logic;\r
     X4           : in    std_logic;\r
     XC           : in    std_logic;\r
@@ -119,6 +119,7 @@ architecture pexor_arch of pexor is
   signal med_dataready_out       : std_logic_vector (NUM_LINKS-1 downto 0);\r
   signal med_read_out            : std_logic_vector (NUM_LINKS-1 downto 0);\r
   signal med_stat_op             : std_logic_vector (NUM_LINKS*16-1 downto 0);\r
+  signal buf_med_stat_op         : std_logic_vector (NUM_LINKS*16-1 downto 0);\r
   signal med_ctrl_op             : std_logic_vector (NUM_LINKS*16-1 downto 0);\r
   signal buf_med_ctrl_op         : std_logic_vector (NUM_LINKS*16-1 downto 0);\r
   signal med_stat_debug          : std_logic_vector (NUM_LINKS*64-1 downto 0);\r
@@ -135,10 +136,9 @@ architecture pexor_arch of pexor is
 \r
 \r
   signal debug_pci_core          : std_logic_vector(31 downto 0);\r
-  signal send_network_reset      : std_logic;\r
-  signal send_network_reset_falling : std_logic;\r
+       signal send_network_reset_internal : std_logic;\r
+  signal make_reset_internal     : std_logic;\r
   signal reset_i_trbnet          : std_logic;\r
-  signal send_network_reset_last : std_logic;\r
 \r
   signal res_cnt                 : unsigned(4 downto 0);\r
 \r
@@ -162,6 +162,16 @@ architecture pexor_arch of pexor is
   signal  rx_data_out            : std_logic_vector(63 downto 0);\r
   signal  requestor_id           : std_logic_vector(15 downto 0);\r
   signal  debug_endpoint         : std_logic_vector(31 downto 0);\r
+  signal  gsr_n : std_logic;\r
+  \r
+  attribute syn_preserve : boolean;\r
+  attribute syn_keep : boolean;\r
+\r
+  attribute syn_preserve of gsr_n : signal is true;\r
+  attribute syn_keep of gsr_n : signal is true;  \r
+  attribute syn_preserve of pll_locked : signal is true;\r
+  attribute syn_keep of pll_locked : signal is true;  \r
+\r
 \r
 begin\r
 \r
@@ -169,26 +179,31 @@ begin
 -- Clock & Reset state machine\r
 ---------------------------------------------------------------------------\r
   clk_en                 <= '1';\r
+  gsr_n <= pll_locked;\r
 \r
+--   gen_med_ctrl_op : for i in 0 to NUM_LINKS-1 generate\r
+--     med_ctrl_op(16*i+15 downto 16*i) <= (send_network_reset & "000000000000000") or buf_med_ctrl_op;\r
+--   end generate;\r
 \r
-  gen_med_ctrl_op : for i in 0 to NUM_LINKS-1 generate\r
-    med_ctrl_op(16*i+15 downto 16*i) <= send_network_reset & "000000000000000";\r
-  end generate;\r
+  med_ctrl_op <= buf_med_ctrl_op;\r
 \r
-\r
-  process(clk_150_i)\r
-    begin\r
-      if rising_edge(clk_150_i) then\r
-        send_network_reset_last <= send_network_reset;\r
-        send_network_reset_falling <= not send_network_reset and send_network_reset_last;\r
-      end if;\r
-    end process;\r
+--   process(clk_150_i)\r
+--     begin\r
+--       if rising_edge(clk_150_i) then\r
+--                             send_network_reset      <= send_network_reset_internal or med_stat_op(15); -- \r
+--         send_network_reset_last <= send_network_reset;\r
+--         send_network_reset_falling <= (not send_network_reset and send_network_reset_last) or med_stat_op(13); -- \r
+--       end if;\r
+--     end process;\r
 \r
 \r
   THE_RESET_PROC : process(CLK_100)\r
     begin\r
       if rising_edge(CLK_100) then\r
-        if res_cnt(4) = '0' then\r
+        if pll_locked = '0' then\r
+          reset_i <= '1';\r
+          res_cnt <= (others => '0');\r
+        elsif res_cnt(4) = '0' then\r
           res_cnt <= res_cnt + to_unsigned(1,1);\r
           reset_i <= '1';\r
         else\r
@@ -208,7 +223,7 @@ begin
 \r
   THE_RESET_HANDLER : trb_net_reset_handler\r
     generic map(\r
-      RESET_DELAY     => x"0EEE"\r
+      RESET_DELAY     => x"00EE"\r
       )\r
     port map(\r
       CLEAR_IN        => '0',            -- reset input (high active, async)\r
@@ -216,8 +231,8 @@ begin
       CLK_IN          => CLK_100,        -- raw master clock, NOT from PLL/DLL!\r
       SYSCLK_IN       => clk_150_i,      -- PLL/DLL remastered clock\r
       PLL_LOCKED_IN   => pll_locked,     -- master PLL lock signal (async)\r
-      RESET_IN        => '0',            -- general reset signal (SYSCLK)\r
-      TRB_RESET_IN    => send_network_reset_falling,            -- TRBnet reset signal (SYSCLK)\r
+      RESET_IN        => reset_i,        -- general reset signal (SYSCLK)\r
+      TRB_RESET_IN    => make_reset_internal,            -- TRBnet reset signal (SYSCLK)\r
       CLEAR_OUT       => reset_async,    -- async reset out, USE WITH CARE!\r
       RESET_OUT       => reset_i_trbnet,    -- synchronous reset out (SYSCLK)\r
       DEBUG_OUT       => open\r
@@ -259,7 +274,7 @@ begin
       SD_LOS_IN          => SFP1_LOS,  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
       SD_TXDIS_OUT       => SFP1_TX_DIS, -- SFP disable\r
       -- Status and control port\r
-      STAT_OP            => med_stat_op(15 downto 0),\r
+      STAT_OP            => buf_med_stat_op(15 downto 0),\r
       CTRL_OP            => med_ctrl_op(15 downto 0),\r
       STAT_DEBUG         => open,\r
       CTRL_DEBUG         => (others => '0')\r
@@ -316,7 +331,8 @@ med_stat_op(31 downto 16) <= x"000" & "0111";
       COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))\r
       )\r
     port map(\r
-      RESET              => reset_i_trbnet,\r
+      RESET              => reset_i,\r
+      RESET_TRBNET       => reset_i_trbnet,\r
       CLK                => clk_150_i,\r
       CLK_125_IN         => clk_125_i,\r
 \r
@@ -369,7 +385,8 @@ med_stat_op(31 downto 16) <= x"000" & "0111";
       MED_STAT_OP_IN     => med_stat_op,\r
       MED_CTRL_OP_OUT    => buf_med_ctrl_op,\r
 \r
-      SEND_RESET_OUT     => send_network_reset,\r
+      SEND_RESET_OUT     => send_network_reset_internal,\r
+      MAKE_RESET_OUT     => make_reset_internal,\r
       PROGRMN_OUT        => open,\r
       DEBUG_OUT          => debug_endpoint\r
       );\r
@@ -450,7 +467,7 @@ med_stat_op(31 downto 16) <= x"000" & "0111";
 ---------------------------------------------------------------------------\r
 -- LED & Debug\r
 ---------------------------------------------------------------------------\r
-  led(3)      <= not pll_locked;\r
+  led(3)      <= not pll_locked when rising_edge(CLK_100);\r
 \r
   led(0)      <= not med_stat_op(9);\r
   led(1)      <= not med_stat_op(10);\r
@@ -458,9 +475,27 @@ med_stat_op(31 downto 16) <= x"000" & "0111";
 \r
   led(4)      <= not med_stat_op(16+9);\r
   led(5)      <= not med_stat_op(16+10);\r
-  led(6)      <= not med_stat_op(16+11);\r
-\r
-  led(7)      <= not send_network_reset;\r
+  \r
+  led(6)      <= not make_reset_internal;\r
+  led(7)      <= not send_network_reset_internal;\r
+\r
+\r
+  test(0) <= bus_we;\r
+  test(1) <= bus_ack;\r
+  test(2) <= bus_stb;\r
+  test(3) <= reset_i;\r
+  test(4) <= reset_async;\r
+  test(5) <= reset_i_trbnet;\r
+  test(6) <= med_stat_op(13);\r
+  test(7) <= med_stat_op(14);\r
+  test(8) <= med_stat_op(15);\r
+  test(9) <= pll_locked when rising_edge(CLK_100);\r
+  test(10)<= rx_st_out;\r
+  test(11)<= send_network_reset_internal;\r
+  test(12)<= make_reset_internal;\r
+  test(13)<= '0';\r
+  test(14)<= '0';\r
+  test(15)<= clk_100_i;\r
 \r
 --  test(3 downto 0)     <= bus_din(3 downto 0);\r
 --  test(4)     <= bus_dout(0);\r
@@ -475,7 +510,7 @@ med_stat_op(31 downto 16) <= x"000" & "0111";
 --  test(9)     <= bus_dout(15);\r
 --  test(15 downto 10) <= debug_pci_core(21 downto 16);\r
 \r
-  test(31 downto 0) <= debug_endpoint(31 downto 0);\r
+  test(31 downto 16) <= debug_endpoint(31 downto 16);\r
 \r
 -- test(3 downto 0)   <= med_stat_op(7 downto 4); --fsm state\r
 -- test(5 downto 4)   <= med_stat_debug(46 downto 45); --tx_k\r

diff --git a/sim/pexor.mpf b/sim/pexor.mpf
new file mode 100644 (file)
index 0000000..5538e23
--- /dev/null
+++ b/sim/pexor.mpf
@@ -0,0 +1,1716 @@
+; Copyright 1991-2010 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+; to use Vital 1995 version of the standard
+; IEEE library must be mapped to the vital1995 library
+; one cannot use the vital1995 library directly because it assume that it
+; is the IEEE library.  If vital1995 and vital2000 are being mixed together then
+; ieee must be mapped to vital1995 and vital200 mapped to vital2000 
+; ieee = $MODEL_TECH/../vital1995
+; for compatiblity with previously the VITAL2000 maps to a seperate library from IEEE
+; if one should not reference vital from both the ieee library and the vital library becasue
+; the vital packages are effectively different.  If one needs to reference both libraies the
+; vital2000 and ieee MUST be mapped to the same library either $MODEL_TECH/../ieee
+; or $MODEL_TECH/../vital2000
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA  = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+scm = /d/sugar/lattice/diamond/1.1/ispfpga/vhdl/data/orca5/mti/work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+;   case statement static warnings
+;   warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on.  Refer to the comment for this in the [vlog] area. 
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/report/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0 
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M.  (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576 
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches. 
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+;    1 -- Turn off all optimizations that affect coverage reports.
+;    2 -- Allow optimizations that allow large performance improvements 
+;         by invoking sequential processes only when the data changes. 
+;         This may make major reductions in coverage counts.
+;    3 -- In addition, allow optimizations that may change expressions or 
+;         remove some statements. Allow constant propagation. Allow VHDL
+;         subprogram inlining and VHDL FF recognition. 
+;    4 -- In addition, allow optimizations that may remove major regions of 
+;         code by changing assignments to built-ins or removing unused
+;         signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with 
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+;    variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces 
+; "merge_instances" to a user specified default value and supersedes 
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces 
+; "get_inst_coverage" to a user specified default value and supersedes 
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages.  The behavior is identical to using the "-L" switch.
+; 
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch.  Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog.  White space
+; in extensions can be specified with a back-slash: "\ ".  Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and 
+; SystemVerilog keywords are ignored. 
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1).  The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/reports/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/reports/UCDB etc. This does not affect 
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions.  Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library.  Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom.  Default is off.
+; SccomVerbose = 1
+
+; sccom logfile.  Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library.  Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt.  Default is off. 
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on.  Refer to the comment for this in the [vlog] area. 
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/reports/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/reports/UCDB etc. This does not affect 
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically. 
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 16 us
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1 
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+;    -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1 
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1 
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; noqueue       Do not wait in the license queue when a license is not available
+; viewsim       Try for viewer license but accept simulator license(s) instead
+;               of queuing for viewer license (PE ONLY)
+; noviewer     Disable checkout of msimviewer and vsim-viewer license 
+;              features (PE ONLY)
+; noslvhdl     Disable checkout of qhsimvh and vsim license features
+; noslvlog     Disable checkout of qhsimvl and vsimvlog license features
+; nomix                Disable checkout of msimhdlmix and hdlmix license features
+; nolnl                Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly    Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license 
+;              features
+; lnlonly      Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+;              hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message. 
+; Or stop the simulator after SystemVerilog severity system task.
+; The severity of VHDL assertion or severity system task
+; should be higher or equal.
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+;      from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+;   level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
+; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name:  # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions. 
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1 
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next.  Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type).  Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly.  The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+; 
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+;  VPI_COMPATIBILITY_VERSION_1364v1995
+;  VPI_COMPATIBILITY_VERSION_1364v2001
+;  VPI_COMPATIBILITY_VERSION_1364v2005
+;  VPI_COMPATIBILITY_VERSION_1800v2005
+;  VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+;  VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+;  VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+;  VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+;  VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+;  VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during 
+; simulation.  If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during 
+; simulation.  If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file using system lockd locking mechanism.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.  
+; The size is giving in megabytes.  A value of 0 turns off the
+; WLF cache. 
+; WLFSimCacheSize allows a different cache size to be set for 
+; simulation WLF file independent of post-simulation WLF file 
+; viewing.  If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration. 
+;     (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step. 
+;     (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional 
+; prefix of 1, 10, or 100.  The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns.  However if Resolution 
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of 
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations.  If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit), 
+; sc_stop(), tf_dofinish(), and assertion failures. 
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask"   -- In batch mode, the vsim kernel will abruptly exit.  
+;            In GUI mode, a dialog box will pop up and ask for user confirmation 
+;            whether or not to quit the simulation.
+; "stop"  -- Cause the simulation to stay loaded in memory. This can make some 
+;            post-simulation tasks easier.
+; "exit"  -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages. 
+; Deferred assertion messages may be scheduled after the $finish in the same 
+; time step. Deferred assertions scheduled to print after the $finish are 
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode.  Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue  1 = Break  2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off. 
+; The default is -1 (unlimited). If the number of threads for an assertion go 
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default 
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the 
+; existing attempts keep on evaluating but no new attempts are started. This 
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off. 
+; The default is -1 (unlimited). If the number of threads for a cover go 
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default 
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the 
+; existing attempts keep on evaluating but no new attempts are started. This 
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed.  This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more 
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance.  Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Turn on/off all PSL/SVA cover directive enables.  Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log.  Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close). 
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then 
+; cross_num_print_missing is ignored for creating reports and displaying 
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin 
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and 
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648 
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648 
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives.  Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs.  Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects.  The list of shared objects should
+; be whitespace delimited.  This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator. 
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+;    "auto" - automatically select the best engine for the current
+;             constraint scenario
+;    "bdd"  - evaluate all constraint scenarios using the BDD solver engine
+;    "act"  - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: At this time, the "auto" setting is equivalent to the "bdd" setting.
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 1000000.  A value of 0 indicates no limit.
+; SolveACTMaxTests = 1000000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints.  This 
+; 'speculation' set is solved independently of the remaining constraints. 
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set).  If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+;    0 - no speculation
+;    1 - enable speculation that maintains LRM specified distribution
+;    2 - enable other speculation - may yield non-LRM distribution 
+; Currently, distribution constraints and solve-before constraints are 
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM 
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100. 
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+;    i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+;    n = disable bit interleaving for all constraints (BDD engine)
+;    r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This 
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated 
+; in favor shell level expansion.  Universal environment variable expansion 
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this 
+; deprecated behavior.  The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation. 
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+;  Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+;  Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+;  Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+;  Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+;  Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+;   suppress = 3009,CNNODP,3043,TFMPC
+;   suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages.  The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho].  They
+; also include the analogous file I/O tasks that write to STDOUT 
+; (i.e. $fwrite or $fdisplay).  The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted.  The default
+; is to have messages appear only in the transcript.  The other 
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or 
+; to both the transcript and the wlf file.  The valid values are
+;    tran  {transcript only (default)}
+;    wlf   {wlf file only}
+;    both  {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting.  The default is to 
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer).  The other settings are to send messages 
+; only to the transcript or only to the wlf file.  The valid 
+; values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 65
+Project_File_0 = /d/jspc22/trb/cvs/trbnet/trb_net16_dummy_fifo.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1223980059 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net16_sbuf.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295605920 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_2 = /d/jspc22/trb/cvs/pexor/version.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1307219663 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_3 = /d/jspc22/trb/cvs/trbnet/special/trb_net_bridge_pcie_apl.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296223754 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_4 = /d/jspc22/trb/cvs/trbnet/basics/signal_sync.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1252935466 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /d/jspc22/trb/cvs/trbnet/trb_net_priority_arbiter.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232454950 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_6 = /d/jspc22/trb/cvs/trbnet/lattice/scm/pll_in100_out50_250.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1294234243 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 43 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_7 = /d/jspc22/trb/cvs/trbnet/trb_net16_hub_logic.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285157319 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
+Project_File_8 = /d/jspc22/trb/cvs/trbnet/trb_net16_term_ibuf.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279025455 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 49 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_9 = /d/jspc22/trb/cvs/pexor/design/dma_core.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1307352126 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_10 = /d/jspc22/trb/cvs/trbnet/trb_net16_ibuf.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267482504 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_11 = /d/jspc22/trb/cvs/trbnet/basics/ram_16x16_dp.vhd
+Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291626330 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_12 = /d/jspc22/trb/cvs/pexor/pcie_components.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1307108983 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_13 = /d/jspc22/trb/cvs/trbnet/special/trb_net_reset_handler.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937284 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_14 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf3.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1260785641 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 29 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_15 = /d/jspc22/trb/cvs/trbnet/lattice/scm/fifo/fifo_19x16_obuf.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291813212 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_16 = /d/jspc22/trb/cvs/trbnet/trb_net16_iobuf.vhd
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1283787725 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_17 = /d/jspc22/trb/cvs/trbnet/trb_net16_regIO.vhd
+Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1294058561 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_18 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf5.vhd
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277480320 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 31 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_19 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd
+Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302596620 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_20 = /d/jspc22/trb/cvs/trbnet/basics/ram.vhd
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226059306 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_21 = /d/jspc22/trb/cvs/trbnet/special/trb_net_bridge_pcie_endpoint_hub.vhd
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1297681981 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
+Project_File_22 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
+Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285762496 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 33 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_23 = /d/jspc22/trb/cvs/trbnet/trb_net16_addresses.vhd
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291310548 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_24 = /d/jspc22/trb/cvs/trbnet/testbenches/tb_trb_net_bridge_pcie_endpoint_hub.vhd
+Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295951291 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_25 = /d/jspc22/trb/cvs/trbnet/lattice/scm/trb_net16_fifo_arch.vhd
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1292237357 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 46 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_26 = /d/jspc22/trb/cvs/trbnet/trb_net_dummy_fifo.vhd
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1223984953 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 21 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_27 = /d/jspc22/trb/cvs/trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd
+Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1292237184 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 42 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_28 = /d/jspc22/trb/cvs/trbnet/trb_net16_hub_func.vhd
+Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1306495358 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_29 = /d/jspc22/trb/cvs/trbnet/trb_net16_io_multiplexer.vhd
+Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286203168 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_30 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd
+Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302870046 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_31 = /d/jspc22/trb/cvs/trbnet/lattice/scm/fifo_32x512.vhd
+Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1303397047 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 59 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_32 = /d/jspc22/trb/cvs/trbnet/trb_net16_obuf.vhd
+Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302092613 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_33 = /d/jspc22/trb/cvs/trbnet/basics/delay_signal.vhd
+Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1283463237 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_34 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire_listener.vhd
+Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1265373351 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 23 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_35 = /d/jspc22/trb/cvs/pexor/design/cores/fifo_8x16_dualclock.vhd
+Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296722174 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_36 = /d/jspc22/trb/cvs/trbnet/lattice/scm/pll_in100_out100.vhd
+Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291997897 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 44 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_37 = /d/jspc22/trb/cvs/pexor/design/tb_dma_core.vhd
+Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1307352757 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 55 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_38 = /d/jspc22/trb/cvs/trbnet/trb_net16_term_buf.vhd
+Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259575068 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_39 = /d/jspc22/trb/cvs/trbnet/basics/pulse_sync.vhd
+Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1281340212 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_40 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf.vhd
+Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295604741 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_41 = /d/jspc22/trb/cvs/pexor/design/cores/fifo_16x512_dualclock.vhd
+Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1303918850 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 61 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_42 = /d/jspc22/trb/cvs/trbnet/trb_net_priority_encoder.vhd
+Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203082656 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_43 = /d/jspc22/trb/cvs/pexor/design/cores/fifo_8x512_dualclock.vhd
+Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296725421 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_44 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf2.vhd
+Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1260181690 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_45 = /d/jspc22/trb/cvs/trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd
+Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1293101550 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 47 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_46 = /d/jspc22/trb/cvs/trbnet/trb_net16_api_base.vhd
+Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295604664 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002
+Project_File_47 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf4.vhd
+Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1260782946 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 30 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_48 = /d/jspc22/trb/cvs/trbnet/basics/wide_adder_17x16.vhd
+Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1244220279 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_49 = /d/jspc22/trb/cvs/trbnet/lattice/scm/pll_in100_out150.vhd
+Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1294420796 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 45 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_50 = /d/jspc22/trb/cvs/trbnet/trb_net_sbuf6.vhd
+Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280407531 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 32 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_51 = /d/jspc22/trb/cvs/trbnet/trb_net16_hub_base.vhd
+Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1306495079 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_52 = /d/jspc22/trb/cvs/trbnet/trb_net_CRC.vhd
+Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1234800462 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_53 = /d/jspc22/trb/cvs/trbnet/basics/rom_16x16.vhd
+Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226059295 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_54 = /d/jspc22/trb/cvs/trbnet/basics/ram_dp_rw.vhd
+Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232468545 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 51 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_55 = /d/jspc22/trb/cvs/trbnet/basics/rom_16x8.vhd
+Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226059271 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_56 = /d/jspc22/trb/cvs/pexor/design/cores/fifo_dc_32x1024.vhd
+Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1307108786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_57 = /d/jspc22/trb/cvs/pexor/design/cores/fifo_32to64x512_dualclock.vhd
+Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304410807 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_58 = /d/jspc22/trb/cvs/trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd
+Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1293101383 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 41 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_59 = /d/jspc22/trb/cvs/trbnet/basics/pulse_stretch.vhd
+Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278959201 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_60 = /d/jspc22/trb/cvs/trbnet/trb_net16_term.vhd
+Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237890722 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_61 = /d/jspc22/trb/cvs/trbnet/trb_net_pattern_gen.vhd
+Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1212595232 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 24 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_62 = /d/jspc22/trb/cvs/trbnet/trb_net16_hub_ipu_logic.vhd
+Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302960855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_63 = /d/jspc22/trb/cvs/trbnet/trb_net16_obuf_nodata.vhd
+Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248935804 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_64 = /d/jspc22/trb/cvs/trbnet/trb_net16_regio_bus_handler.vhd
+Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1265304548 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick = 
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick = 
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick = 
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick = 
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick = 
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick = 
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick = 
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick = 
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick = 
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick = 
+XML_DoubleClick = Edit
+XML_CustomDoubleClick = 
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick = 
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick = 
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick = 
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick = 
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick = 
+Project_Major_Version = 10
+Project_Minor_Version = 0

diff --git a/vcode/UR_gen.v b/vcode/UR_gen.v
new file mode 100644 (file)
index 0000000..c8c61b4
--- /dev/null
+++ b/vcode/UR_gen.v
@@ -0,0 +1,145 @@
+// $Id: UR_gen.v,v 1.1 2013-04-12 14:52:03 hadeshyp Exp $\r
+\r
+// This module is the catch all for any TLP that is not supported by the other\r
+// clients.  \r
+// Currently this module will generate UR for MRdLk, IO, Cfg1, Cpl, and Memory reads other than BAR1\r
+\r
+\r
+`timescale 1ns / 100ps\r
+module UR_gen(rstn, clk,\r
+               rx_din, rx_sop, rx_eop, rx_dwen, rx_us, rx_bar_hit,\r
+               tx_rdy, tx_val, \r
+               tx_req, tx_dout, tx_sop, tx_eop, tx_dwen,                     \r
+               comp_id          \r
+);\r
+              \r
+  \r
+\r
+input         rstn;\r
+input         clk;\r
+input  [63:0] rx_din;\r
+input         rx_sop;\r
+input         rx_eop;\r
+input         rx_dwen;\r
+input         rx_us;\r
+input [6:0]   rx_bar_hit;\r
+input         tx_rdy;\r
+input         tx_val;\r
+output        tx_req;\r
+output [63:0] tx_dout;\r
+output        tx_sop;\r
+output        tx_eop;\r
+output        tx_dwen;\r
+input [15:0] comp_id; \r
+\r
+\r
+reg  [63:0] tx_dout;\r
+reg         tx_sop;\r
+reg         tx_eop;\r
+reg         tx_dwen;\r
+reg         tx_req;\r
+reg [2:0] sm;\r
+reg [23:0] req_id;\r
+reg [2:0] sts;\r
+\r
+\r
+\r
+always @(negedge rstn or posedge clk)\r
+begin\r
+  if (~rstn)\r
+  begin\r
+    tx_req <= 1'b0;\r
+    tx_sop <= 1'b0;\r
+    tx_eop <= 1'b0;\r
+    tx_dwen <= 1'b0;\r
+    tx_dout <= 64'd0;\r
+    sm <= 3'b000;\r
+    req_id <= 24'd0;\r
+    sts <= 3'b000;\r
+    \r
+  end\r
+  else\r
+  begin\r
+      \r
+    case (sm)\r
+    3'b000:  // Decode Type of Request\r
+    begin\r
+      if (rx_sop)\r
+      begin\r
+        req_id <= rx_din[31:8];\r
+      \r
+        if (rx_us) // IP core indicates CfgWr1, CfgRd1, MRdLk, CplLk, CplDLk, Msg (Vendor Defined) \r
+        begin\r
+          sm <= 3'b001;\r
+          sts <= 3'b001;\r
+        end          \r
+        else       \r
+        begin\r
+          casex(rx_din[63:56])\r
+          8'b00000010: begin sm<=3'b001; sts<=3'b001; end // IORd\r
+          8'b01000010: begin sm<=3'b001; sts<=3'b001; end // IOWr\r
+  //        8'b0111xxxx: begin sm<=3'b001; sts<=3'b001;end  //MsgD\r
+          8'b00000000:  // MRd\r
+          begin\r
+            if (rx_bar_hit[1] || rx_bar_hit[0])\r
+              sm <= 3'b000; // BAR0 or BAR1 read, do nothing\r
+            else\r
+            begin\r
+              sm <= 3'b001; // Send UR          \r
+              sts <= 3'b001;\r
+            end\r
+          end\r
+          default: sm <= 3'b000;\r
+          endcase\r
+        end\r
+      end\r
+    end\r
+    3'b001: // Send completion\r
+    begin      \r
+      if (tx_val)\r
+      begin\r
+        tx_req <= 1'b1;\r
+        sm <= 5'b010;\r
+      end    \r
+    end\r
+    3'b010: \r
+    begin\r
+      if (tx_val && tx_rdy)\r
+      begin\r
+        tx_sop <= 1'b1;\r
+        tx_dout <= {8'b00001010, 24'h000000, comp_id, sts, 13'd4};\r
+        tx_req <= 1'b0;\r
+        sm <= 5'b011;\r
+      end    \r
+    end\r
+    3'b011:\r
+    begin\r
+      if (tx_val && tx_rdy)\r
+      begin\r
+        tx_sop <= 1'b0;\r
+        tx_dout <= {req_id, 8'h00, 32'd0};\r
+        tx_eop <= 1'b1;\r
+        tx_dwen <= 1'b1;        \r
+        sm <= 3'b100; // Clear\r
+      end\r
+    end\r
+    3'b100: // clear\r
+    begin\r
+      if (tx_val)\r
+      begin\r
+        tx_sop <= 1'b0;\r
+        tx_dout <= 64'd0;\r
+        tx_eop <= 1'b0;\r
+        tx_dwen <= 1'b0;        \r
+        sm <= 3'b000;            \r
+      end\r
+    end           \r
+    endcase\r
+      \r
+    \r
+    \r
+  end // end clk\r
+end \r
+\r
+endmodule\r
+\r

diff --git a/vcode/ip_crpr_arb.v b/vcode/ip_crpr_arb.v
new file mode 100644 (file)
index 0000000..367dd19
--- /dev/null
+++ b/vcode/ip_crpr_arb.v
@@ -0,0 +1,154 @@
+// $Id: ip_crpr_arb.v,v 1.1 2013-04-12 14:52:03 hadeshyp Exp $\r
+\r
+module ip_crpr_arb(clk, rstn,               \r
+                  pd_cr_0, pd_num_0, ph_cr_0, npd_cr_0, nph_cr_0,\r
+                  pd_cr_1, pd_num_1, ph_cr_1, npd_cr_1, nph_cr_1,\r
+                  pd_cr, pd_num, ph_cr, npd_cr, nph_cr\r
+                  \r
+);\r
+\r
+input clk;\r
+input rstn;\r
+\r
+input pd_cr_0;\r
+input [7:0] pd_num_0;\r
+input ph_cr_0;\r
+input npd_cr_0;\r
+input nph_cr_0;\r
+\r
+input pd_cr_1;\r
+input [7:0] pd_num_1;\r
+input ph_cr_1;\r
+input npd_cr_1;\r
+input nph_cr_1;\r
+\r
+output pd_cr;\r
+output [7:0] pd_num;\r
+output ph_cr;\r
+output npd_cr;\r
+output nph_cr;\r
+\r
+reg pd_cr;\r
+reg [7:0] pd_num;\r
+reg ph_cr;\r
+reg npd_cr;\r
+reg nph_cr;\r
+\r
+reg pd_cr_1p;\r
+reg [7:0] pd_num_1p;\r
+reg ph_cr_1p;\r
+reg npd_cr_1p;\r
+reg nph_cr_1p;\r
+\r
+reg del_p1, del_np1;\r
+\r
+// This arbiter works on an assumption that there is at least 1 clock cycle of gap between credits\r
+// The arbiter will select the port that is active.  If both are active it will delay port1 and use \r
+// that data on the next clock cycle.  \r
+\r
+always @(posedge clk or negedge rstn)\r
+begin\r
+  if (~rstn)\r
+  begin\r
+    pd_cr <= 1'b0;\r
+    pd_num <= 8'd0;\r
+    ph_cr <= 1'b0;\r
+    npd_cr <= 1'b0;\r
+    nph_cr <= 1'b0;\r
+    pd_cr_1p <= 1'b0;\r
+    pd_num_1p <= 8'd0;\r
+    ph_cr_1p <= 1'b0;\r
+    npd_cr_1p <= 1'b0;\r
+    nph_cr_1p <= 1'b0;\r
+    del_p1 <= 1'b0;\r
+    del_np1 <= 1'b0;\r
+  end\r
+  else\r
+  begin\r
+    pd_cr_1p <=  pd_cr_1;\r
+    pd_num_1p <= pd_num_1;\r
+    ph_cr_1p <=  ph_cr_1;\r
+    npd_cr_1p <= npd_cr_1;\r
+    nph_cr_1p <= nph_cr_1;\r
+    \r
+    if (del_p1)\r
+    begin\r
+      ph_cr <= ph_cr_1p;\r
+      pd_cr <= pd_cr_1p;\r
+      pd_num <= pd_num_1p;\r
+      del_p1 <= 1'b0;      \r
+    end\r
+    else\r
+    begin    \r
+      case ({ph_cr_1, ph_cr_0})\r
+      2'b00:\r
+      begin\r
+        ph_cr <= 1'b0;\r
+        pd_cr <= 1'b0;\r
+        pd_num <= 8'd0;\r
+      end\r
+      2'b01:\r
+      begin\r
+        ph_cr <= ph_cr_0;\r
+        pd_cr <= pd_cr_0;\r
+        pd_num <= pd_num_0;\r
+        \r
+      end\r
+      2'b10:\r
+      begin\r
+        ph_cr <= ph_cr_1;\r
+        pd_cr <= pd_cr_1;   \r
+        pd_num <= pd_num_1; \r
+      end\r
+      2'b11:\r
+      begin\r
+        ph_cr <= ph_cr_0;\r
+        pd_cr <= pd_cr_0;\r
+        pd_num <= pd_num_0;\r
+        del_p1 <= 1'b1;\r
+      end\r
+      endcase\r
+    end\r
+  \r
+    if (del_np1)\r
+    begin\r
+      nph_cr <= nph_cr_1p;\r
+      npd_cr <= npd_cr_1p;\r
+      del_np1 <= 1'b0;      \r
+    end\r
+    else\r
+    begin    \r
+      case ({nph_cr_1, nph_cr_0})\r
+      2'b00:\r
+      begin\r
+        nph_cr <= 1'b0;\r
+        npd_cr <= 1'b0;\r
+      end\r
+      2'b01:\r
+      begin\r
+        nph_cr <= nph_cr_0;\r
+        npd_cr <= npd_cr_0;\r
+      end\r
+      2'b10:\r
+      begin\r
+        nph_cr <= nph_cr_1;\r
+        npd_cr <= npd_cr_1;    \r
+      end\r
+      2'b11:\r
+      begin\r
+        nph_cr <= nph_cr_0;\r
+        npd_cr <= npd_cr_0;\r
+        del_np1 <= 1'b1;\r
+      end\r
+      endcase\r
+    end \r
+  \r
+    \r
+  end // clk\r
+end\r
+\r
+\r
+endmodule\r
+\r
+\r
+  
\ No newline at end of file

diff --git a/vcode/ip_rx_crpr.v b/vcode/ip_rx_crpr.v
new file mode 100644 (file)
index 0000000..21fbd62
--- /dev/null
+++ b/vcode/ip_rx_crpr.v
@@ -0,0 +1,156 @@
+// $Id: ip_rx_crpr.v,v 1.1 2013-04-12 14:52:03 hadeshyp Exp $\r
+\r
+module ip_rx_crpr(clk, rstn,\r
+               rx_st, rx_end, rx_din, rx_dwen, rx_bar_hit,\r
+               pd_cr, pd_num, ph_cr, npd_cr, nph_cr\r
+);\r
+\r
+input clk;\r
+input rstn;\r
+\r
+input rx_st;\r
+input rx_end;\r
+input rx_dwen;\r
+input [63:0] rx_din;\r
+input [6:0] rx_bar_hit;\r
+\r
+output pd_cr;\r
+output [7:0] pd_num;\r
+output ph_cr;\r
+output npd_cr;\r
+output nph_cr;\r
+\r
+reg pd_cr;\r
+reg [7:0] pd_num;\r
+reg ph_cr;\r
+reg npd_cr;\r
+reg nph_cr;\r
+\r
+reg one_nph;\r
+reg one_ph;\r
+reg one_pd;\r
+reg one_npd;\r
+\r
+reg [1:0] sm;\r
+\r
+\r
+always @(posedge clk or negedge rstn)\r
+begin\r
+  if (~rstn)\r
+  begin\r
+    pd_cr <= 1'b0;\r
+    pd_num <= 8'd0;\r
+    ph_cr <= 1'b0;\r
+    npd_cr <= 1'b0;\r
+    nph_cr <= 1'b0;\r
+    one_ph <= 1'b0;\r
+    one_pd <= 1'b0;\r
+    one_nph <= 1'b0;\r
+    one_npd <= 1'b0;\r
+   \r
+    sm <= 2'b00;\r
+  end\r
+  else\r
+  begin\r
+  \r
+    case (sm)    \r
+    2'b00: // wait for TLP\r
+    begin  \r
+      // Decode Type of Request\r
+      if (rx_st)\r
+      begin    \r
+        casex (rx_din[63:56])\r
+        8'h00: // MRd to BAR other than 0 or 1\r
+        begin\r
+          if (~(rx_bar_hit[1] || rx_bar_hit[0]))\r
+            one_nph <= 1'b1;\r
+        end \r
+        8'h40: // MWr to BAR other than 0 or 1\r
+        begin\r
+          if (~(rx_bar_hit[1] || rx_bar_hit[0]))\r
+          begin            \r
+            one_ph <= 1'b1;\r
+            one_pd <= 1'b1;\r
+            pd_num <= rx_din[38:32]; // get length          \r
+          end\r
+        end\r
+        8'b00110xxx: // Msg\r
+        begin\r
+          one_ph <= 1'b1;\r
+        end      \r
+        8'b01110xxx: // MsgD\r
+        begin\r
+          one_ph <= 1'b1;\r
+          one_pd <= 1'b1;\r
+          pd_num <= rx_din[38:32]; // get length\r
+        end      \r
+        8'h44: // CfgWr0\r
+        begin\r
+          one_nph <= 1'b1;\r
+          one_npd <= 1'b1;\r
+        end      \r
+        8'h04: // CfgRd0\r
+        begin\r
+          one_nph <= 1'b1;\r
+        end              \r
+        8'h45: // CfgWr1\r
+        begin\r
+          one_nph <= 1'b1;\r
+          one_npd <= 1'b1;\r
+        end      \r
+        8'h05: // CfgRd1\r
+        begin\r
+          one_nph <= 1'b1;\r
+        end              \r
+        default:  \r
+        begin          \r
+        end\r
+        endcase    \r
+        \r
+        sm <= 2'b01;\r
+      end\r
+      else\r
+      begin\r
+        one_ph <= 1'b0;\r
+        one_pd <= 1'b0;\r
+        one_nph <= 1'b0;\r
+        one_npd <= 1'b0;\r
+      end\r
+      \r
+      ph_cr <= 1'b0;\r
+      pd_cr <= 1'b0;\r
+      nph_cr <= 1'b0;\r
+      npd_cr <= 1'b0;\r
+      \r
+    end\r
+    2'b01:  // process credits\r
+    begin\r
+      ph_cr <= one_ph;\r
+      one_ph <= 1'b0;\r
+      \r
+      nph_cr <= one_nph;\r
+      one_nph <= 1'b0;\r
+      \r
+      npd_cr <= one_npd;\r
+      one_npd <= 1'b0;\r
+      \r
+      pd_cr <= one_pd;      \r
+      one_pd <= 1'b0;\r
+      \r
+      \r
+      sm <= 2'b00;  \r
+          \r
+    end\r
+    default:\r
+    begin\r
+    end\r
+    endcase\r
+    \r
+  end // clk\r
+end\r
+\r
+\r
+endmodule\r
+\r
+\r
+  
\ No newline at end of file

diff --git a/vcode/ip_tx_arbiter.v b/vcode/ip_tx_arbiter.v
new file mode 100644 (file)
index 0000000..161ac16
--- /dev/null
+++ b/vcode/ip_tx_arbiter.v
@@ -0,0 +1,165 @@
+// $Id: ip_tx_arbiter.v,v 1.1 2013-04-12 14:52:03 hadeshyp Exp $\r
+\r
+module ip_tx_arbiter (clk, rstn, tx_val,\r
+                  tx_req_0, tx_din_0, tx_sop_0, tx_eop_0, tx_dwen_0,                 \r
+                  tx_req_1, tx_din_1, tx_sop_1, tx_eop_1, tx_dwen_1,\r
+                  tx_req_2, tx_din_2, tx_sop_2, tx_eop_2, tx_dwen_2,\r
+                  tx_req_3, tx_din_3, tx_sop_3, tx_eop_3, tx_dwen_3,\r
+                  tx_rdy_0, tx_rdy_1, tx_rdy_2, tx_rdy_3,\r
+                  tx_req, tx_dout, tx_sop, tx_eop, tx_dwen,\r
+                  tx_rdy                  \r
+);  \r
+\r
+input clk;\r
+input rstn;\r
+input tx_val;\r
+\r
+input tx_req_0;\r
+input [63:0] tx_din_0;\r
+input tx_sop_0;\r
+input tx_eop_0;\r
+input tx_dwen_0;\r
+output tx_rdy_0;\r
+\r
+input tx_req_1;\r
+input [63:0] tx_din_1;\r
+input tx_sop_1;\r
+input tx_eop_1;\r
+input tx_dwen_1;\r
+output tx_rdy_1;\r
+\r
+input tx_req_2;\r
+input [63:0] tx_din_2;\r
+input tx_sop_2;\r
+input tx_eop_2;\r
+input tx_dwen_2;\r
+output tx_rdy_2;\r
+\r
+input tx_req_3;\r
+input [63:0] tx_din_3;\r
+input tx_sop_3;\r
+input tx_eop_3;\r
+input tx_dwen_3;\r
+output tx_rdy_3;\r
+\r
+output tx_req;\r
+output [63:0] tx_dout;\r
+output tx_sop;\r
+output tx_eop;\r
+output tx_dwen;\r
+input tx_rdy;\r
+\r
+reg tx_req;\r
+reg [63:0] tx_dout;\r
+reg tx_sop;\r
+reg tx_eop;\r
+reg tx_dwen;\r
+reg tx_rdy_0;\r
+reg tx_rdy_1;\r
+reg tx_rdy_2;\r
+reg tx_rdy_3;\r
+\r
+reg [1:0] rr;\r
+reg tx_rdy_p;\r
+reg tx_rdy_p2;\r
+\r
+\r
+always @(rr or tx_rdy or \r
+         tx_req_0 or tx_din_0 or tx_sop_0 or tx_eop_0 or tx_dwen_0 or\r
+         tx_req_1 or tx_din_1 or tx_sop_1 or tx_eop_1 or tx_dwen_1 or\r
+         tx_req_2 or tx_din_2 or tx_sop_2 or tx_eop_2 or tx_dwen_2 or\r
+         tx_req_3 or tx_din_3 or tx_sop_3 or tx_eop_3 or tx_dwen_3  ) \r
+\r
+begin\r
+  \r
+   case (rr)\r
+   2'b00: // Service 0\r
+   begin\r
+     tx_req <= tx_req_0;\r
+     tx_dout <= tx_din_0;\r
+     tx_sop <= tx_sop_0;\r
+     tx_eop <= tx_eop_0;\r
+     tx_dwen <= tx_dwen_0;     \r
+     tx_rdy_0 <= tx_rdy;\r
+     tx_rdy_3 <= 1'b0;\r
+     tx_rdy_2 <= 1'b0;\r
+     tx_rdy_1 <= 1'b0;\r
+\r
+   end\r
+   2'b01: // Service 1\r
+   begin\r
+     tx_req <= tx_req_1;\r
+     tx_dout <= tx_din_1;\r
+     tx_sop <= tx_sop_1;\r
+     tx_eop <= tx_eop_1;\r
+     tx_dwen <= tx_dwen_1;     \r
+     tx_rdy_1 <= tx_rdy;\r
+     tx_rdy_3 <= 1'b0;\r
+     tx_rdy_2 <= 1'b0;\r
+     tx_rdy_0 <= 1'b0;\r
+\r
+   end\r
+   2'b10: // Service 2\r
+   begin\r
+     tx_req <= tx_req_2;\r
+     tx_dout <= tx_din_2;\r
+     tx_sop <= tx_sop_2;\r
+     tx_eop <= tx_eop_2;\r
+     tx_dwen <= tx_dwen_2;      \r
+     tx_rdy_2 <= tx_rdy;\r
+     tx_rdy_3 <= 1'b0;\r
+     tx_rdy_1 <= 1'b0;\r
+     tx_rdy_0 <= 1'b0;\r
+\r
+   end \r
+   2'b11: // Service 3\r
+   begin\r
+     tx_req <= tx_req_3;\r
+     tx_dout <= tx_din_3;\r
+     tx_sop <= tx_sop_3;\r
+     tx_eop <= tx_eop_3;\r
+     tx_dwen <= tx_dwen_3;      \r
+     tx_rdy_3 <= tx_rdy;\r
+     tx_rdy_2 <= 1'b0;\r
+     tx_rdy_1 <= 1'b0;\r
+     tx_rdy_0 <= 1'b0;\r
+\r
+   end \r
+   default:\r
+   begin\r
+   end\r
+   endcase\r
+\r
+end\r
+\r
+\r
+// mux control\r
+always @(posedge clk or negedge rstn)\r
+begin\r
+  if (~rstn)\r
+  begin\r
+    rr <= 2'b00;    \r
+    tx_rdy_p <= 1'b0;\r
+    tx_rdy_p2 <= 1'b0;\r
+  end\r
+  else\r
+  begin\r
+    tx_rdy_p <= tx_rdy; // use pipe of tx_rdy to account for getting the tx_end through\r
+    tx_rdy_p2 <= tx_rdy_p;\r
+  \r
+    if (tx_val && ~tx_rdy_p2 && ~tx_rdy_p && ~tx_rdy)\r
+    begin\r
+      if (tx_req_0 && ~tx_req)\r
+        rr <= 2'b00;\r
+      else if (tx_req_1 && ~tx_req)\r
+        rr <= 2'b01;\r
+      else if (tx_req_2 && ~tx_req)\r
+        rr <= 2'b10;\r
+      else if (tx_req_3 && ~tx_req)\r
+        rr <= 2'b11;\r
+    end\r
+  end\r
+end\r
+\r
+endmodule\r
+\r

diff --git a/vcode/pci_exp_ddefines.v b/vcode/pci_exp_ddefines.v
new file mode 100644 (file)
index 0000000..9619edb
--- /dev/null
+++ b/vcode/pci_exp_ddefines.v
@@ -0,0 +1,129 @@
+// =============================================================================\r
+//                           COPYRIGHT NOTICE\r
+// Copyright 2000-2001 (c) Lattice Semiconductor Corporation\r
+// ALL RIGHTS RESERVED\r
+// This confidential and proprietary software may be used only as authorised\r
+// by a licensing agreement from Lattice Semiconductor Corporation.\r
+// The entire notice above must be reproduced on all authorized copies and\r
+// copies may only be made to the extent permitted by a licensing agreement\r
+// from Lattice Semiconductor Corporation.\r
+//\r
+// Lattice Semiconductor Corporation    TEL : 1-800-Lattice (USA and Canada)\r
+// 5555 NE Moore Court                        408-826-6000 (other locations)\r
+// Hillsboro, OR 97124                  web  : http://www.latticesemi.com/\r
+// U.S.A                                email: techsupport@latticesemi.com\r
+// =============================================================================\r
+//                         FILE DETAILS\r
+// Project          : pci_exp\r
+// File             : pci_exp_dparams.v\r
+// Title            :\r
+// Dependencies     :\r
+// Description      : defines for all modules of the design.\r
+// =============================================================================\r
+//                        REVISION HISTORY\r
+// Version          : 1.0\r
+// Author(s)        : \r
+// Mod. Date        : Jan 31, 2006\r
+// Changes Made     : Initial Creation\r
+// =============================================================================\r
+\r
+//==============================================================================\r
+// Defines lane width \r
+// LW1 for X1\r
+// LW2 for X2\r
+// LW4 for X4\r
+//==============================================================================\r
+`define      LW4\r
+\r
+//==============================================================================\r
+// Defines if the component has a Down Stream Lane or an Upstream lane \r
+// When not defined the IP has a Up stream lane\r
+//==============================================================================\r
+//`define      DWN_STRM_LANE  \r
+\r
+//==============================================================================\r
+// Defines if the component has a Down Stream Port or an Upstream Port \r
+// When not defined the IP has a Up stream Port\r
+//==============================================================================\r
+//`define      DWN_STRM_PORT \r
+\r
+//==============================================================================\r
+// Defines the Component types. Enable the appropriate component type \r
+//`define      ROOT_COMP       \r
+//`define      SWITCH_COMP    \r
+//`define      ENDPOINT_COMP    \r
+//==============================================================================\r
+`define      ENDPOINT_COMP    \r
+\r
+//==============================================================================\r
+// Define if the CFG REG block is selected \r
+//`define      CFG_REG        -- Config registers present\r
+//==============================================================================\r
+`define      CFG_REG\r
+\r
+//==============================================================================\r
+// Generate the appropriate defines to select the the VC  channel \r
+// used in TXINTF block to enable VC\r
+// =============================================================================\r
+`ifdef VC1\r
+   `define EN_VC0\r
+`endif\r
+`ifdef VC2\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+`endif\r
+`ifdef VC3\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+`endif\r
+`ifdef VC4\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+   `define EN_VC3\r
+`endif\r
+`ifdef VC5\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+   `define EN_VC3\r
+   `define EN_VC4\r
+`endif\r
+`ifdef VC6\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+   `define EN_VC3\r
+   `define EN_VC4\r
+   `define EN_VC5\r
+`endif\r
+`ifdef VC7\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+   `define EN_VC3\r
+   `define EN_VC4\r
+   `define EN_VC5\r
+   `define EN_VC6\r
+`endif\r
+`ifdef VC8\r
+   `define CFG_VCC\r
+   `define EN_VC0\r
+   `define EN_VC1\r
+   `define EN_VC2\r
+   `define EN_VC3\r
+   `define EN_VC4\r
+   `define EN_VC5\r
+   `define EN_VC6\r
+   `define EN_VC7\r
+`endif\r
+// =============================================================================\r
+\r
+\r

diff --git a/vcode/pci_exp_params.v b/vcode/pci_exp_params.v
new file mode 100644 (file)
index 0000000..e05816c
--- /dev/null
+++ b/vcode/pci_exp_params.v
@@ -0,0 +1,73 @@
+`define        HW_EVAL\r
+`define        ENDPOINT_COMP\r
+//Use Hard LTSSM MACO Block\r
+`define LTSSM_MACO\r
+`define        SERDES_QUAD RA\r
+//System Bus for PCS access\r
+`define PCS_SYSBUS\r
+`define POL_COMP\r
+`define SKP_INS_CNT  10'd190\r
+\r
+// DLL Layer Defines\r
+//========================================\r
+`define        MAX_TLP_512\r
+//  Value of the Update Freq count\r
+`define UPDATE_FREQ_PH  7'd8\r
+`define UPDATE_FREQ_PD  11'd255\r
+`define UPDATE_FREQ_NPH 7'd8\r
+`define UPDATE_FREQ_NPD 11'd255\r
+`define UPDATE_TIMER  12'd4095\r
+\r
+// TRANSCATION Layer Defines\r
+//========================================\r
+//Init FC values for VC0\r
+`define   INIT_PH_FC_VC0 8'h00\r
+`define   INIT_PD_FC_VC0 12'h000\r
+`define   INIT_NPH_FC_VC0 8'h00\r
+`define   INIT_NPD_FC_VC0 12'h000\r
+// For Type0 Registers\r
+`define INIT_REG_000  32'h53031204\r
+`define INIT_REG_008  32'hff000000\r
+`define INIT_REG_00C  32'h00000000\r
+`define        EN_BAR0\r
+`define        EN_BAR1\r
+`define INIT_REG_010  32'hff000000\r
+`define INIT_REG_014  32'hff000000\r
+`define INIT_REG_018  32'h00000000\r
+`define INIT_REG_01C  32'h00000000\r
+`define INIT_REG_020  32'h00000000\r
+`define INIT_REG_024  32'h00000000\r
+`define INIT_REG_028  32'h00000000\r
+`define INIT_REG_02C  32'h53031204\r
+`define INIT_REG_030  32'h00000000\r
+`define INIT_REG_03C  32'h00000100\r
+`define INIT_REG_050  32'h00000000\r
+`define INIT_REG_054  32'h00000000\r
+// For PM Registers\r
+`define INIT_PM_DS_DATA_0  10'd0\r
+`define INIT_PM_DS_DATA_1  10'd0\r
+`define INIT_PM_DS_DATA_2  10'd0\r
+`define INIT_PM_DS_DATA_3  10'd0\r
+`define INIT_PM_DS_DATA_4  10'd0\r
+`define INIT_PM_DS_DATA_5  10'd0\r
+`define INIT_PM_DS_DATA_6  10'd0\r
+`define INIT_PM_DS_DATA_7  10'd0\r
+`define MSI\r
+// For MSI Registers\r
+`define INIT_REG_070  32'h00800000\r
+// For PCIE Registers\r
+`define INIT_REG_090  32'h00010000\r
+`define INIT_REG_094  32'b00000000000000000000000000000000\r
+`define INIT_REG_09C  32'b00000000000000000000000001000001\r
+`define INIT_REG_0A0  32'h00000000\r
+// For Device Serial no. Registers\r
+`define INIT_REG_104  32'h00000000\r
+`define INIT_REG_108  32'h00000000\r
+// For VCC Registers\r
+`define INIT_REG_10C  32'h00000000\r
+`define TERM_ALL_CFG 1'b1\r
+`define ACKNAK_LAT_TIME  14'd77\r
+`define        LPEVCC 3'b000\r
+`define        VC1\r
+`define        NUM_VC 1\r
+`define TLP_DEBUG 1'd0\r

diff --git a/vcode/pciexp2_bb.v b/vcode/pciexp2_bb.v
new file mode 100644 (file)
index 0000000..f587fd7
--- /dev/null
+++ b/vcode/pciexp2_bb.v
@@ -0,0 +1,168 @@
+//=============================================================================\r
+// Verilog module generated by IPExpress    08/21/2007    16:22:41\r
+// Filename: USERNAME_bb.v\r
+// Copyright(c) 2005 Lattice Semiconductor Corporation. All rights reserved.\r
+//=============================================================================\r
+\r
+/* WARNING - Changes to this file should be performed by re-running IPexpress\r
+or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+to inconsistent simulation and/or implemenation results */\r
+\r
+//---------------------------------------------------------------\r
+// USERNAME synthesis black box definition\r
+//---------------------------------------------------------------\r
+module pciexp2 (\r
+   // Clock & reset\r
+   input wire                rst_n,           // asynchronous system reset.\r
+   input wire                serdes_rst,      // Serdes reset\r
+   input wire                refclk_250,      // 250 Mhz reference Clock\r
+   input wire                clk_50,          // 50 Mhz SMI clock\r
+   input wire                flip_lanes,      // Switch lanes 3,2,1,0 -> 0,1,2,3\r
+\r
+   input wire                inta_n,\r
+   input wire  [7:0]         msi,\r
+   // Line side interface\r
+   input wire                hdinp_0,\r
+   input wire                hdinn_0,\r
+   input wire                hdinp_1,\r
+   input wire                hdinn_1,\r
+   input wire                hdinp_2,\r
+   input wire                hdinn_2,\r
+   input wire                hdinp_3,\r
+   input wire                hdinn_3,\r
+\r
+   output wire               hdoutp_0,\r
+   output wire               hdoutn_0,\r
+   output wire               hdoutp_1,\r
+   output wire               hdoutn_1,\r
+   output wire               hdoutp_2,\r
+   output wire               hdoutn_2,\r
+   output wire               hdoutp_3,\r
+   output wire               hdoutn_3,\r
+\r
+   input wire             force_lsm_active, //  Force LSM Status Active\r
+   input wire             force_rec_ei,     //  Force Received Electrical Idle\r
+   input wire             force_phy_status, //  Force PHY Connection Status\r
+   input wire             force_disable_scr,//  Force Disable Scrambler to PCS\r
+\r
+   input wire             hl_snd_beacon,    // HL req. to Send Beacon\r
+   input wire             hl_disable_scr,   // HL req. to Disable Scrambling bit in TS1/TS2\r
+   input wire             hl_gto_dis,       // HL req a jump to Disable\r
+   input wire             hl_gto_det,       // HL req a jump to detect\r
+   input wire             hl_gto_hrst,      // HL req a jump to Hot reset\r
+   input wire             hl_gto_l0stx,     // HL req a jump to TX L0s\r
+   input wire             hl_gto_l1,        // HL req a jump to L1\r
+   input wire             hl_gto_l2,        // HL req a jump to L2\r
+   input wire             hl_gto_l0stxfts,  // HL req a jump to L0s TX FTS\r
+   input wire [3:0]       hl_gto_lbk,       // HL req a jump to Loopback\r
+   input wire             hl_gto_rcvry,     // HL req a jump to recovery\r
+   input wire             hl_gto_cfg,       // HL req a jump to CFG\r
+   input wire             no_pcie_train,    // Disable the training process\r
+\r
+   // Power Management Interface\r
+   input wire  [1:0]      tx_dllp_val,      // Req for Sending PM/Vendor type DLLP\r
+   input wire  [2:0]      tx_pmtype,        // Power Management Type\r
+   input wire  [23:0]     tx_vsd_data,      // Vendor Type DLLP contents\r
+\r
+   // For VC Inputs\r
+   input wire             tx_req_vc0,          // VC0 Request from User\r
+   input wire [63:0]      tx_data_vc0,         // VC0 Input data from user logic\r
+   input wire             tx_st_vc0,           // VC0 start of pkt from user logic.\r
+   input wire             tx_end_vc0,          // VC0 End of pkt from user logic.\r
+   input wire             tx_nlfy_vc0,         // VC0 End of nullified pkt from user logic.\r
+   input wire             tx_dwen_vc0,         // VC0 Dword enable from user logic.\r
+   input wire             ph_buf_status_vc0,   // VC0 Indicate the Full/alm.Full status of the PH buffers\r
+   input wire             pd_buf_status_vc0,   // VC0 Indicate PD Buffer has got space less than Max Pkt size\r
+   input wire             nph_buf_status_vc0,  // VC0 For NPH\r
+   input wire             npd_buf_status_vc0,  // VC0 For NPD\r
+   input wire             ph_processed_vc0,    // VC0 TL has processed one TLP Header - PH Type\r
+   input wire             pd_processed_vc0,    // VC0 TL has processed one TLP Data - PD TYPE\r
+   input wire             nph_processed_vc0,   // VC0 For NPH\r
+   input wire             npd_processed_vc0,   // VC0 For NPD\r
+   input wire [7:0]       pd_num_vc0,          // VC0 For PD -- No. of Data processed\r
+   input wire [7:0]       npd_num_vc0,         // VC0 For PD\r
+\r
+\r
+   // From User logic\r
+   input wire                cmpln_tout ,     // Completion time out.\r
+   input wire                cmpltr_abort ,   // Completor abort.\r
+   input wire                unexp_cmpln ,    // Unexpexted completion.\r
+   input wire                ur_np_ext ,      // UR for NP type.\r
+   input wire                ur_p_ext ,       // UR for P type.\r
+   input wire                np_req_pend ,    // Non posted request is pending.\r
+   input wire                pme_status ,     // PME status to reg 044h.\r
+   input wire                rx_rst ,         //\r
+   input wire                prog_done ,      //\r
+\r
+   // System bus\r
+   input  wire [44:0]           sysbus_in,    // System bus inputs to PCS\r
+   output wire [16:0]           sysbus_out,   // PCS outputs to System bus\r
+\r
+   // Power Management/ Vendor specific DLLP\r
+   output wire            tx_dllp_sent,       // Requested PM DLLP is sent\r
+   output wire [2:0]      rxdp_pmd_type,      // PM DLLP type bits.\r
+   output wire [23:0]     rxdp_vsd_data ,     // Vendor specific DLLP data.\r
+   output wire [1:0]      rxdp_dllp_val,      // PM/Vendor specific DLLP valid.\r
+\r
+   output wire [3:0]         phy_cfgln,           // Indicates the Configured Lanes\r
+   output wire [2:0]         phy_cfgln_sum,       // Number of Configured lanes\r
+   output wire               phy_pol_compliance,  // Polling compliance\r
+   output wire               phy_realign_req,\r
+   output wire [3:0]         phy_ltssm_state,\r
+   output wire [2:0]         phy_ltssm_substate,\r
+   output wire [2:0]         phy_l0s_tx_state,\r
+   output wire [1:0]         phy_l1_state,\r
+   output wire [1:0]         phy_l2_state,\r
+   output wire               phy_mloopback,\r
+   output wire               phy_sloopback,\r
+   output wire               phy_snd_beacon,\r
+\r
+   // Extra\r
+   output wire               lsm_status_0,\r
+   output wire               lsm_status_1,\r
+   output wire               lsm_status_2,\r
+   output wire               lsm_status_3,\r
+   output wire               tx_val,          // Valid signal toggles during x2/x1 downgrade\r
+\r
+   output wire               tx_rdy_vc0,      // VC0 TX ready indicating signal\r
+   output wire [8:0]         tx_ca_ph_vc0,    // VC0 Available credit for Posted Type Headers\r
+   output wire [12:0]        tx_ca_pd_vc0,    // VC0 For Posted - Data\r
+   output wire [8:0]         tx_ca_nph_vc0,   // VC0 For Non-posted - Header\r
+   output wire [12:0]        tx_ca_npd_vc0,   // VC0 For Non-posted - Data\r
+   output wire [8:0]         tx_ca_cplh_vc0,  // VC0 For Completion - Header\r
+   output wire [12:0]        tx_ca_cpld_vc0,  // VC0 For Completion - Data\r
+   output wire               tx_ca_p_recheck_vc0, //\r
+   output wire               tx_ca_cpl_recheck_vc0, //\r
+   output wire [63:0]        rx_data_vc0,     // VC0 Receive data\r
+   output wire               rx_st_vc0,       // VC0 Receive data start\r
+   output wire               rx_end_vc0,      // VC0 Receive data end\r
+   output wire               rx_dwen_vc0,     // VC0 Dword enable\r
+   output wire               rx_us_req_vc0 ,  // VC0 unsupported req received\r
+   output wire               rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data\r
+   output wire [6:0]         rx_bar_hit ,     // Bar hit\r
+   output wire [2:0]         mm_enable ,     // Multiple message enable bits of Register\r
+   output wire               msi_enable ,    // MSI enable bit of Register\r
+\r
+   // From Config Registers\r
+   output wire [7:0]         bus_num ,        // Bus number\r
+   output wire [4:0]         dev_num ,        // Device number\r
+   output wire [2:0]         func_num ,       // Function number\r
+   output wire [1:0]         pm_power_state , // Power state bits of Register at 044h\r
+   output wire               pme_en ,         // PME_En at 044h\r
+   output wire [5:0]         cmd_reg_out ,    // Bits 10,8,6,2,1,0 From register 004h\r
+   output wire [14:0]        dev_cntl_out ,   // Divice control register at 060h\r
+   output wire [7:0]         lnk_cntl_out ,   // Link control register at 068h\r
+\r
+   // Datal Link Control SM Status\r
+   output wire               dl_inactive,     // Data Link Control SM is in INACTIVE state\r
+   output wire               dl_init,         // INIT state\r
+   output wire               dl_active,       // ACTIVE state\r
+   output wire               dl_up,           // Data Link Layer is UP\r
+\r
+   output wire               sys_clk_125      // 125 Mhz system clock for User logic\r
+\r
+  )\r
+/*synthesis syn_black_box black_box_pad_pin = "hdinp_0, hdinn_0, hdinp_1, hdinn_1, hdinp_2, hdinn_2, hdinp_3, hdinn_3, hdoutp_0, hdoutn_0, hdoutp_1, hdoutn_1, hdoutp_2, hdoutn_2, hdoutp_3, hdoutn_3" */\r
+/*synthesis black_box     black_box_pad     = "hdinp_0, hdinn_0, hdinp_1, hdinn_1, hdinp_2, hdinn_2, hdinp_3, hdinn_3, hdoutp_0, hdoutn_0, hdoutp_1, hdoutn_1, hdoutp_2, hdoutn_2, hdoutp_3, hdoutn_3" */\r
+;\r
+endmodule\r

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diff --git a/vcode/tlc_fifo.lpc b/vcode/tlc_fifo.lpc
new file mode 100644 (file)
index 0000000..58aebcd
--- /dev/null
+++ b/vcode/tlc_fifo.lpc
@@ -0,0 +1,48 @@
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA15EP1\r
+PartName=LFSCM3GA15EP1-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO_DC\r
+CoreRevision=5.1\r
+ModuleName=tlc_fifo\r
+SourceFormat=Verilog HDL\r
+ParameterFileVersion=1.0\r
+Date=04/02/2009\r
+Time=16:24:12\r
+\r
+[Parameters]\r
+Verilog=1\r
+VHDL=0\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Only\r
+RDepth=512\r
+RWidth=75\r
+WDepth=512\r
+WWidth=75\r
+regout=0\r
+CtrlByRdEn=0\r
+EmpFlg=1\r
+PeMode=Static - Single Threshold\r
+PeAssert=1\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Static - Single Threshold\r
+PfAssert=500\r
+PfDeassert=506\r
+Reset=Async\r
+RDataCount=0\r
+WDataCount=0\r
+EnECC=0\r

diff --git a/vcode/tlc_fifo.v b/vcode/tlc_fifo.v
new file mode 100644 (file)
index 0000000..7ce8fdd
--- /dev/null
+++ b/vcode/tlc_fifo.v
@@ -0,0 +1,214 @@
+/* Verilog netlist generated by SCUBA ispLever_v72_SP1_Build (24) */
+/* Module Version: 5.1 */
+/* F:\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n tlc_fifo -lang verilog -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 75 -rwidth 75 -no_enable -pe 1 -pf 500 -e  */
+/* Thu Apr 02 16:24:12 2009 */
+
+
+`timescale 1 ns / 1 ps
+module tlc_fifo (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
+    Empty, Full, AlmostEmpty, AlmostFull);
+    input wire [74:0] Data;
+    input wire WrClock;
+    input wire RdClock;
+    input wire WrEn;
+    input wire RdEn;
+    input wire Reset;
+    input wire RPReset;
+    output wire [74:0] Q;
+    output wire Empty;
+    output wire Full;
+    output wire AlmostEmpty;
+    output wire AlmostFull;
+
+    wire scuba_vhi;
+    wire Empty_int;
+    wire Full_int;
+    wire scuba_vlo;
+
+    // synopsys translate_off
+    defparam tlc_fifo_0_2.FULLPOINTER1 = 15'b011111111000001 ;
+    defparam tlc_fifo_0_2.FULLPOINTER = 15'b011111111100001 ;
+    defparam tlc_fifo_0_2.AFPOINTER1 = 15'b011111001000001 ;
+    defparam tlc_fifo_0_2.AFPOINTER = 15'b011111001100001 ;
+    defparam tlc_fifo_0_2.AEPOINTER1 = 15'b000000001011111 ;
+    defparam tlc_fifo_0_2.AEPOINTER = 15'b000000000111111 ;
+    defparam tlc_fifo_0_2.RESETMODE = "ASYNC" ;
+    defparam tlc_fifo_0_2.REGMODE = "NOREG" ;
+    defparam tlc_fifo_0_2.CSDECODE_R =  2'b11 ;
+    defparam tlc_fifo_0_2.CSDECODE_W =  2'b11 ;
+    defparam tlc_fifo_0_2.DATA_WIDTH_R = 36 ;
+    defparam tlc_fifo_0_2.DATA_WIDTH_W = 36 ;
+    // synopsys translate_on
+    FIFO16KA tlc_fifo_0_2 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), 
+        .DI3(Data[3]), .DI4(Data[4]), .DI5(Data[5]), .DI6(Data[6]), .DI7(Data[7]), 
+        .DI8(Data[8]), .DI9(Data[9]), .DI10(Data[10]), .DI11(Data[11]), 
+        .DI12(Data[12]), .DI13(Data[13]), .DI14(Data[14]), .DI15(Data[15]), 
+        .DI16(Data[16]), .DI17(Data[17]), .DI18(Data[18]), .DI19(Data[19]), 
+        .DI20(Data[20]), .DI21(Data[21]), .DI22(Data[22]), .DI23(Data[23]), 
+        .DI24(Data[24]), .DI25(Data[25]), .DI26(Data[26]), .DI27(Data[27]), 
+        .DI28(Data[28]), .DI29(Data[29]), .DI30(Data[30]), .DI31(Data[31]), 
+        .DI32(Data[32]), .DI33(Data[33]), .DI34(Data[34]), .DI35(Data[35]), 
+        .FULLI(Full_int), .CSW0(scuba_vhi), .CSW1(scuba_vhi), .EMPTYI(Empty_int), 
+        .CSR0(scuba_vhi), .CSR1(scuba_vhi), .WE(WrEn), .RE(RdEn), .CLKW(WrClock), 
+        .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), .DO0(Q[18]), .DO1(Q[19]), 
+        .DO2(Q[20]), .DO3(Q[21]), .DO4(Q[22]), .DO5(Q[23]), .DO6(Q[24]), 
+        .DO7(Q[25]), .DO8(Q[26]), .DO9(Q[27]), .DO10(Q[28]), .DO11(Q[29]), 
+        .DO12(Q[30]), .DO13(Q[31]), .DO14(Q[32]), .DO15(Q[33]), .DO16(Q[34]), 
+        .DO17(Q[35]), .DO18(Q[0]), .DO19(Q[1]), .DO20(Q[2]), .DO21(Q[3]), 
+        .DO22(Q[4]), .DO23(Q[5]), .DO24(Q[6]), .DO25(Q[7]), .DO26(Q[8]), 
+        .DO27(Q[9]), .DO28(Q[10]), .DO29(Q[11]), .DO30(Q[12]), .DO31(Q[13]), 
+        .DO32(Q[14]), .DO33(Q[15]), .DO34(Q[16]), .DO35(Q[17]), .EF(Empty_int), 
+        .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int))
+             /* synthesis FULLPOINTER1="0b011111111000001" */
+             /* synthesis FULLPOINTER="0b011111111100001" */
+             /* synthesis AFPOINTER1="0b011111001000001" */
+             /* synthesis AFPOINTER="0b011111001100001" */
+             /* synthesis AEPOINTER1="0b000000001011111" */
+             /* synthesis AEPOINTER="0b000000000111111" */
+             /* synthesis RESETMODE="ASYNC" */
+             /* synthesis REGMODE="NOREG" */
+             /* synthesis CSDECODE_R="0b11" */
+             /* synthesis CSDECODE_W="0b11" */
+             /* synthesis DATA_WIDTH_R="36" */
+             /* synthesis DATA_WIDTH_W="36" */;
+
+    // synopsys translate_off
+    defparam tlc_fifo_1_1.FULLPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_1_1.FULLPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_1_1.AFPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_1_1.AFPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_1_1.AEPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_1_1.AEPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_1_1.RESETMODE = "ASYNC" ;
+    defparam tlc_fifo_1_1.REGMODE = "NOREG" ;
+    defparam tlc_fifo_1_1.CSDECODE_R =  2'b11 ;
+    defparam tlc_fifo_1_1.CSDECODE_W =  2'b11 ;
+    defparam tlc_fifo_1_1.DATA_WIDTH_R = 36 ;
+    defparam tlc_fifo_1_1.DATA_WIDTH_W = 36 ;
+    // synopsys translate_on
+    FIFO16KA tlc_fifo_1_1 (.DI0(Data[36]), .DI1(Data[37]), .DI2(Data[38]), 
+        .DI3(Data[39]), .DI4(Data[40]), .DI5(Data[41]), .DI6(Data[42]), 
+        .DI7(Data[43]), .DI8(Data[44]), .DI9(Data[45]), .DI10(Data[46]), 
+        .DI11(Data[47]), .DI12(Data[48]), .DI13(Data[49]), .DI14(Data[50]), 
+        .DI15(Data[51]), .DI16(Data[52]), .DI17(Data[53]), .DI18(Data[54]), 
+        .DI19(Data[55]), .DI20(Data[56]), .DI21(Data[57]), .DI22(Data[58]), 
+        .DI23(Data[59]), .DI24(Data[60]), .DI25(Data[61]), .DI26(Data[62]), 
+        .DI27(Data[63]), .DI28(Data[64]), .DI29(Data[65]), .DI30(Data[66]), 
+        .DI31(Data[67]), .DI32(Data[68]), .DI33(Data[69]), .DI34(Data[70]), 
+        .DI35(Data[71]), .FULLI(Full_int), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
+        .EMPTYI(Empty_int), .CSR0(scuba_vhi), .CSR1(scuba_vhi), .WE(WrEn), 
+        .RE(RdEn), .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), 
+        .DO0(Q[54]), .DO1(Q[55]), .DO2(Q[56]), .DO3(Q[57]), .DO4(Q[58]), 
+        .DO5(Q[59]), .DO6(Q[60]), .DO7(Q[61]), .DO8(Q[62]), .DO9(Q[63]), 
+        .DO10(Q[64]), .DO11(Q[65]), .DO12(Q[66]), .DO13(Q[67]), .DO14(Q[68]), 
+        .DO15(Q[69]), .DO16(Q[70]), .DO17(Q[71]), .DO18(Q[36]), .DO19(Q[37]), 
+        .DO20(Q[38]), .DO21(Q[39]), .DO22(Q[40]), .DO23(Q[41]), .DO24(Q[42]), 
+        .DO25(Q[43]), .DO26(Q[44]), .DO27(Q[45]), .DO28(Q[46]), .DO29(Q[47]), 
+        .DO30(Q[48]), .DO31(Q[49]), .DO32(Q[50]), .DO33(Q[51]), .DO34(Q[52]), 
+        .DO35(Q[53]), .EF(), .AEF(), .AFF(), .FF())
+             /* synthesis FULLPOINTER1="0b000000000000000" */
+             /* synthesis FULLPOINTER="0b111111111111111" */
+             /* synthesis AFPOINTER1="0b000000000000000" */
+             /* synthesis AFPOINTER="0b111111111111111" */
+             /* synthesis AEPOINTER1="0b000000000000000" */
+             /* synthesis AEPOINTER="0b111111111111111" */
+             /* synthesis RESETMODE="ASYNC" */
+             /* synthesis REGMODE="NOREG" */
+             /* synthesis CSDECODE_R="0b11" */
+             /* synthesis CSDECODE_W="0b11" */
+             /* synthesis DATA_WIDTH_R="36" */
+             /* synthesis DATA_WIDTH_W="36" */;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    // synopsys translate_off
+    defparam tlc_fifo_2_0.FULLPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_2_0.FULLPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_2_0.AFPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_2_0.AFPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_2_0.AEPOINTER1 = 15'b000000000000000 ;
+    defparam tlc_fifo_2_0.AEPOINTER = 15'b111111111111111 ;
+    defparam tlc_fifo_2_0.RESETMODE = "ASYNC" ;
+    defparam tlc_fifo_2_0.REGMODE = "NOREG" ;
+    defparam tlc_fifo_2_0.CSDECODE_R =  2'b11 ;
+    defparam tlc_fifo_2_0.CSDECODE_W =  2'b11 ;
+    defparam tlc_fifo_2_0.DATA_WIDTH_R = 36 ;
+    defparam tlc_fifo_2_0.DATA_WIDTH_W = 36 ;
+    // synopsys translate_on
+    FIFO16KA tlc_fifo_2_0 (.DI0(Data[72]), .DI1(Data[73]), .DI2(Data[74]), 
+        .DI3(scuba_vlo), .DI4(scuba_vlo), .DI5(scuba_vlo), .DI6(scuba_vlo), 
+        .DI7(scuba_vlo), .DI8(scuba_vlo), .DI9(scuba_vlo), .DI10(scuba_vlo), 
+        .DI11(scuba_vlo), .DI12(scuba_vlo), .DI13(scuba_vlo), .DI14(scuba_vlo), 
+        .DI15(scuba_vlo), .DI16(scuba_vlo), .DI17(scuba_vlo), .DI18(scuba_vlo), 
+        .DI19(scuba_vlo), .DI20(scuba_vlo), .DI21(scuba_vlo), .DI22(scuba_vlo), 
+        .DI23(scuba_vlo), .DI24(scuba_vlo), .DI25(scuba_vlo), .DI26(scuba_vlo), 
+        .DI27(scuba_vlo), .DI28(scuba_vlo), .DI29(scuba_vlo), .DI30(scuba_vlo), 
+        .DI31(scuba_vlo), .DI32(scuba_vlo), .DI33(scuba_vlo), .DI34(scuba_vlo), 
+        .DI35(scuba_vlo), .FULLI(Full_int), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
+        .EMPTYI(Empty_int), .CSR0(scuba_vhi), .CSR1(scuba_vhi), .WE(WrEn), 
+        .RE(RdEn), .CLKW(WrClock), .CLKR(RdClock), .RST(Reset), .RPRST(RPReset), 
+        .DO0(), .DO1(), .DO2(), .DO3(), .DO4(), .DO5(), .DO6(), .DO7(), 
+        .DO8(), .DO9(), .DO10(), .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), 
+        .DO16(), .DO17(), .DO18(Q[72]), .DO19(Q[73]), .DO20(Q[74]), .DO21(), 
+        .DO22(), .DO23(), .DO24(), .DO25(), .DO26(), .DO27(), .DO28(), .DO29(), 
+        .DO30(), .DO31(), .DO32(), .DO33(), .DO34(), .DO35(), .EF(), .AEF(), 
+        .AFF(), .FF())
+             /* synthesis FULLPOINTER1="0b000000000000000" */
+             /* synthesis FULLPOINTER="0b111111111111111" */
+             /* synthesis AFPOINTER1="0b000000000000000" */
+             /* synthesis AFPOINTER="0b111111111111111" */
+             /* synthesis AEPOINTER1="0b000000000000000" */
+             /* synthesis AEPOINTER="0b111111111111111" */
+             /* synthesis RESETMODE="ASYNC" */
+             /* synthesis REGMODE="NOREG" */
+             /* synthesis CSDECODE_R="0b11" */
+             /* synthesis CSDECODE_W="0b11" */
+             /* synthesis DATA_WIDTH_R="36" */
+             /* synthesis DATA_WIDTH_W="36" */;
+
+    assign Empty = Empty_int;
+    assign Full = Full_int;
+
+
+    // exemplar begin
+    // exemplar attribute tlc_fifo_0_2 FULLPOINTER1 0b011111111000001
+    // exemplar attribute tlc_fifo_0_2 FULLPOINTER 0b011111111100001
+    // exemplar attribute tlc_fifo_0_2 AFPOINTER1 0b011111001000001
+    // exemplar attribute tlc_fifo_0_2 AFPOINTER 0b011111001100001
+    // exemplar attribute tlc_fifo_0_2 AEPOINTER1 0b000000001011111
+    // exemplar attribute tlc_fifo_0_2 AEPOINTER 0b000000000111111
+    // exemplar attribute tlc_fifo_0_2 RESETMODE ASYNC
+    // exemplar attribute tlc_fifo_0_2 REGMODE NOREG
+    // exemplar attribute tlc_fifo_0_2 CSDECODE_R 0b11
+    // exemplar attribute tlc_fifo_0_2 CSDECODE_W 0b11
+    // exemplar attribute tlc_fifo_0_2 DATA_WIDTH_R 36
+    // exemplar attribute tlc_fifo_0_2 DATA_WIDTH_W 36
+    // exemplar attribute tlc_fifo_1_1 FULLPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_1_1 FULLPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_1_1 AFPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_1_1 AFPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_1_1 AEPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_1_1 AEPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_1_1 RESETMODE ASYNC
+    // exemplar attribute tlc_fifo_1_1 REGMODE NOREG
+    // exemplar attribute tlc_fifo_1_1 CSDECODE_R 0b11
+    // exemplar attribute tlc_fifo_1_1 CSDECODE_W 0b11
+    // exemplar attribute tlc_fifo_1_1 DATA_WIDTH_R 36
+    // exemplar attribute tlc_fifo_1_1 DATA_WIDTH_W 36
+    // exemplar attribute tlc_fifo_2_0 FULLPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_2_0 FULLPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_2_0 AFPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_2_0 AFPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_2_0 AEPOINTER1 0b000000000000000
+    // exemplar attribute tlc_fifo_2_0 AEPOINTER 0b111111111111111
+    // exemplar attribute tlc_fifo_2_0 RESETMODE ASYNC
+    // exemplar attribute tlc_fifo_2_0 REGMODE NOREG
+    // exemplar attribute tlc_fifo_2_0 CSDECODE_R 0b11
+    // exemplar attribute tlc_fifo_2_0 CSDECODE_W 0b11
+    // exemplar attribute tlc_fifo_2_0 DATA_WIDTH_R 36
+    // exemplar attribute tlc_fifo_2_0 DATA_WIDTH_W 36
+    // exemplar end
+
+endmodule