next

diff --git a/GP_Addon/display.vhd b/GP_Addon/display.vhd
index 5389f30052dbf6e9dd0f806bd6c00690965011b3..d130716bfd887b053457a08a782e14a7ffaf94e3 100644 (file)
--- a/GP_Addon/display.vhd
+++ b/GP_Addon/display.vhd
@@ -6,8 +6,8 @@ use IEEE.NUMERIC_STD.all;
 use STD.TEXTIO.all;
 use IEEE.STD_LOGIC_TEXTIO.all;
 -- use work.support.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.all;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
 
 entity display is
   
@@ -34,6 +34,8 @@ architecture display of display is
   signal display_address_counter : std_logic_vector(4 downto 0);
   signal display_data : std_logic_vector(6 downto 0);
   signal write_once_counter : std_logic_vector(3 downto 0):=x"0";
+
+
 begin
   
     WAIT_ONE_SEC: process (CLK, RESET)

diff --git a/compile2b.pl b/compile2b.pl
index 6459168113071bc060b93b1fe1e310d79f2f145a..8424d22c0f52011b1ae610184ceec006f0720d33 100755 (executable)
--- a/compile2b.pl
+++ b/compile2b.pl
@@ -14,9 +14,9 @@ use strict;
 use warnings;
 
 
-$ENV{LM_LICENSE_FILE}="1709\@hadeb05";
-
+#$ENV{LM_LICENSE_FILE}="1709\@hadeb05";
 
+$ENV{LM_LICENSE_FILE}="27000\@lxcad01.gsi.de";
 
 my $PLD_DEVICE="xc4vlx40-10-ff1148";
 my $TOPNAME="trb_v2b_fpga";
@@ -68,6 +68,9 @@ $fh->close;
 #$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
 #$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
 #$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
+#$c="strace -f -o /dev/null /opt/synplicity/syn_c200903/fpga_c200903/bin/synplify_premier_dp  -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
+$c="strace -f -o /home/marek/temp /opt/synplicity/syn_c200903/fpga_c200903/bin/synplify_premier_dp  -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj";
+
 #$c=("( netcat  -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)&  /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj");
 my $r=execute($c, "do_not_exit" );
 
@@ -101,8 +104,8 @@ foreach (@a)
 
 
 #chdir "..";
-$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr";
-execute($c);
+#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr";
+#execute($c);
 #chdir "workdir";
 
 #
@@ -128,7 +131,8 @@ execute($c);
 #
 # Command line for genarate programming file (.bit)
 #
-
+$c="trce -intstyle ise -e 3 -s 10 -xml $TOPNAME $TOPNAME.ncd -o $TOPNAME.twr $TOPNAME.pcf -ucf $TOPNAME.ucf";
+execute($c);
 
 foreach (<$TOPNAME"."_pad.txt>) {
     @a=split (/\s*\|\s*/,$_);

diff --git a/etrax_interfacev2.vhd b/etrax_interfacev2.vhd
index db187bb8f8e21bd7812fe447925e9e77b9767b92..bee1ac377481030d8487bc9d38f84e582b34240d 100644 (file)
--- a/etrax_interfacev2.vhd
+++ b/etrax_interfacev2.vhd
@@ -12,20 +12,24 @@ entity etrax_interfacev2 is
   generic (
     ENABLE_DMA : positive;
     RW_SYSTEM : positive;
-    RW_REGISTERS_NUMBER : positive;
-    R_REGISTERS_NUMBER : positive
+    RW_REGISTERS_NUMBER : natural;
+    R_REGISTERS_NUMBER : natural;
+    TRBNET_ENABLE : natural
     );
   port (
     CLK                     : in    std_logic;
     RESET                   : in    std_logic;
     DATA_BUS                : in    std_logic_vector(31 downto 0);
     ETRAX_DATA_BUS_B        : inout std_logic_vector(16 downto 0);
-    ETRAX_DATA_BUS_B_17     : in std_logic;--_vector(16 downto 0);
-    ETRAX_DATA_BUS_C        : inout    std_logic_vector(17 downto 0);
-    ETRAX_DATA_BUS_E        : inout    std_logic_vector(9 downto 8);
+    ETRAX_DATA_BUS_B_17     : in    std_logic;--_vector(16 downto 0);
+    ETRAX_DATA_BUS_C        : inout std_logic_vector(17 downto 0);
+    ETRAX_DATA_BUS_E        : inout std_logic_vector(9 downto 8);
+    IPU_READY_IN            : in    std_logic;
+    IPU_DATAREADY_OUT       : out   std_logic;
+    IPU_DATA_OUT            : out   std_logic_vector(31 downto 0);
     DATA_VALID              : in    std_logic;
-    ETRAX_BUS_BUSY          : in   std_logic;
-    ETRAX_IS_READY_TO_READ  : out    std_logic;
+    ETRAX_BUS_BUSY          : in    std_logic;
+    ETRAX_IS_READY_TO_READ  : out   std_logic;
     TDC_TCK                 : out   std_logic;
     TDC_TDI                 : out   std_logic;
     TDC_TMS                 : out   std_logic;
@@ -33,14 +37,15 @@ entity etrax_interfacev2 is
     TDC_TDO                 : in    std_logic;
     TDC_RESET               : out   std_logic;
     EXTERNAL_ADDRESS        : out   std_logic_vector(31 downto 0);
-    EXTERNAL_DATA_OUT       : out std_logic_vector(31 downto 0);
-    EXTERNAL_DATA_IN        : in std_logic_vector(31 downto 0);
+    EXTERNAL_DATA_OUT       : out   std_logic_vector(31 downto 0);
+    EXTERNAL_DATA_IN        : in    std_logic_vector(31 downto 0);
     EXTERNAL_ACK            : out   std_logic;
     EXTERNAL_VALID          : in    std_logic;
     EXTERNAL_MODE           : out   std_logic_vector(15 downto 0);
     RW_REGISTER             : out   std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
     R_REGISTER              : in    std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
-    LVL2_VALID              : in    std_logic
+    LVL2_VALID              : in    std_logic;
+    TRB_LVL2_BUSY           : in    std_logic
   --  DEBUG_REGISTER_OO       : out   std_logic_vector(31 downto 0)
     );
 end etrax_interfacev2;
@@ -55,6 +60,17 @@ architecture etrax_interfacev2 of etrax_interfacev2 is
       pulse     : out std_logic);
   end component;
   
+  component up_down_counter
+    generic (
+      NUMBER_OF_BITS : positive);
+    port (
+      CLK       : in  std_logic;
+      RESET     : in  std_logic;
+      COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+      UP_IN     : in  std_logic;
+      DOWN_IN   : in  std_logic);
+  end component;
+  
   signal rw_operation_finished_pulse : std_logic;
   signal saved_rw_mode : std_logic_vector(15 downto 0):= (others => '0');
   signal saved_address : std_logic_vector (31 downto 0):= (others => '0');
@@ -84,7 +100,7 @@ architecture etrax_interfacev2 of etrax_interfacev2 is
   
 
   signal readout_lvl2_fifo :std_logic;
-
+  
   signal data_valid_start_pulse : std_logic;
   signal data_valid_end_pulse : std_logic;
   signal data_valid_not : std_logic;
@@ -93,6 +109,8 @@ architecture etrax_interfacev2 of etrax_interfacev2 is
   signal word16_counter : std_logic_vector(7 downto 0);
   signal write_to_dma_synch_synch : std_logic;
   signal reg_address : integer range 0 to 256 :=1;
+  signal data_valid_synch : std_logic;
+  signal how_many_data_was_sent : std_logic_vector(4 downto 0);
 begin
 
   
@@ -144,55 +162,61 @@ begin
   -- we should add one state to wait for the data from external device (valid
   -- pulse- > one long puls on the data bus !)
   ADDON_SYSTEM : if RW_SYSTEM = 2 generate
-    ETRAX_DATA_BUS_E(8) <= 'Z';
+    ETRAX_DATA_BUS_E(9) <= 'Z';
     STROBE_PULSER                 : edge_to_pulse
       port map (
         clock                                            => CLK,
         en_clk                                           => '1',
         signal_in                                        => ETRAX_DATA_BUS_E(9),--
         pulse                                            => etrax_strobe);
-
+    
     SAVE_ETRAX_DATA               : process (CLK, RESET)
       variable etrax_data_counter : integer := 0;
     begin
       if rising_edge(CLK)then
         if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
           etrax_data_counter                := 0;
-          data_from_etrax                    <= (others => '0');
-          ETRAX_DATA_BUS_E(8)                <= 'Z';
-          enable_transmition                  <= '1';
-          etrax_std_data_counter              <= x"00";
-        elsif etrax_strobe = '0' and etrax_std_data_counter < 81 then 
-          etrax_data_counter                := etrax_data_counter;
-          data_from_etrax                    <= (others => '0');
+          data_from_etrax                     <= (others => '0');
           ETRAX_DATA_BUS_E(8)                <= 'Z';
           enable_transmition                  <= '1';
           etrax_std_data_counter              <= x"00";
-            
         elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then  -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
           data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_E(8);
-          etrax_data_counter                 := etrax_data_counter + 1;
+          etrax_data_counter                  := etrax_data_counter + 1;
           ETRAX_DATA_BUS_E(8)                <= 'Z';
           enable_transmition                  <= '0';
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
         elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
           data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_E(8)                <= data_to_etrax(0);
-          etrax_data_counter                 := etrax_data_counter + 1;
+          etrax_data_counter                := etrax_data_counter + 1;
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
           enable_transmition                  <= '0';
         elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
-          data_from_etrax                    <= data_from_etrax;
-          ETRAX_DATA_BUS_E(8)                <= data_to_etrax( (etrax_data_counter-81) mod 32);
-          etrax_data_counter                 := etrax_data_counter + 1;
+          data_from_etrax                     <= data_from_etrax;
+          ETRAX_DATA_BUS_E(8)                <= data_to_etrax((etrax_data_counter-81) mod 32);--+reg_address*32
+          etrax_data_counter                := etrax_data_counter + 1;
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
           enable_transmition                  <= '0';
         end if;
       end if;
     end process SAVE_ETRAX_DATA;
+
   end generate ADDON_SYSTEM;
 
-  data_to_etrax <= saved_data_fpga when saved_rw_mode(7 downto 0) = x"00" else saved_external_data;
+  SYNC_DATA_TO_ETRAX : process (CLK, RESET)
+  begin  
+    if rising_edge(CLK) then  
+      if RESET = '1' then
+        data_to_etrax <= (others => '0');
+      elsif saved_rw_mode(7 downto 0) = x"00" then
+        data_to_etrax <= saved_data_fpga;
+      else
+        data_to_etrax <= saved_external_data;
+      end if;
+    end if;
+  end process SYNC_DATA_TO_ETRAX;
+
   RW_FINISHED_PULSER       : edge_to_pulse
     port map (
       clock     => CLK,
@@ -289,21 +313,21 @@ begin
           data_bus_reg <= (others => '0');
           write_to_dma_synch <= '0';
           write_to_dma_synch_synch <= '0';
+          data_valid_synch <= '0';
         else
           data_bus_reg <= DATA_BUS;
           write_to_dma_synch <= readout_lvl2_fifo;--write_to_dma;
-          write_to_dma_synch_synch <= write_to_dma_synch;
+          write_to_dma_synch_synch <= write_to_dma_synch and (DATA_VALID or (not(TRB_LVL2_BUSY)));
+          data_valid_synch <= DATA_VALID;
         end if;
       end if;
     end process REG_DATA_TO_ETRAXa;
---    ETRAX_DATA_BUS_B(7 downto 0) <= data_bus_reg(31 downto 24); 
-    ETRAX_DATA_BUS_B(6 downto 0) <= data_bus_reg(30 downto 24);  --!!!test
+    ETRAX_DATA_BUS_B(7 downto 0) <= data_bus_reg(31 downto 24); 
+--    ETRAX_DATA_BUS_B(6 downto 0) <= data_bus_reg(30 downto 24);  --!!!test
     ETRAX_DATA_BUS_B(15 downto 8) <= data_bus_reg(23 downto 16);
     ETRAX_DATA_BUS_C(15 downto 8) <= data_bus_reg(15 downto 8);
     ETRAX_DATA_BUS_C(7 downto 4) <= data_bus_reg(7 downto 4);
-
-
-    ETRAX_DATA_BUS_B(7) <= ETRAX_DATA_BUS_B_17;  --for test
+--    ETRAX_DATA_BUS_B(7) <= ETRAX_DATA_BUS_B_17;  --for test
 
     TDC_TMS                        <= ETRAX_DATA_BUS_C(1) when rw_register_i(0) = '1'  else '1';
     TDC_TCK                        <= ETRAX_DATA_BUS_C(2) when rw_register_i(0) = '1'  else '1';
@@ -312,14 +336,24 @@ begin
     ETRAX_DATA_BUS_C(1)            <= 'Z' when rw_register_i(0) = '1' else data_bus_reg(1);
     ETRAX_DATA_BUS_C(2)            <= 'Z' when rw_register_i(0) = '1' else data_bus_reg(2);
     ETRAX_DATA_BUS_C(3)            <= 'Z' when rw_register_i(0) = '1' else data_bus_reg(3);
+
+    COUNT_CORRECT_WORD_NUMBER: up_down_counter
+      generic map (
+          NUMBER_OF_BITS => 5)
+      port map (
+          CLK       => CLK,
+          RESET     => data_valid_start_pulse,
+          COUNT_OUT => how_many_data_was_sent,
+          UP_IN     => write_to_dma_synch_synch,
+          DOWN_IN   => '0');
     
     START_READOUT      : edge_to_pulse
       port map (
         clock     => CLK,
         en_clk    => '1',
-        signal_in => DATA_VALID,
+        signal_in =>  TRB_LVL2_BUSY,--DATA_VALID,
         pulse     => data_valid_start_pulse);
-    data_valid_not <= not DATA_VALID;
+    data_valid_not <= not TRB_LVL2_BUSY;
     
     END_READOUT      : edge_to_pulse
       port map (
@@ -344,8 +378,10 @@ begin
           word16_counter <= x"FF";
         elsif (data_valid_start_pulse = '1') or (etrax_busy_end = '1' and DATA_VALID = '1') then
           word16_counter <= x"00";
-        elsif word16_counter < x"1e" then
+        elsif (word16_counter < x"1e") and (DATA_VALID = '1' or TRB_LVL2_BUSY = '0') then
           word16_counter <= word16_counter + 1;
+        elsif (word16_counter < x"1e") and (DATA_VALID = '0' and TRB_LVL2_BUSY = '1') then
+          word16_counter(4 downto 0) <= how_many_data_was_sent(3 downto 0) & '0';  
         else
           word16_counter <= word16_counter;
         end if;
@@ -357,13 +393,16 @@ begin
       if rising_edge(CLK) then
         if RESET = '1' or data_valid_end_pulse = '1' or word16_counter = x"1e" then 
           readout_lvl2_fifo <= '0';
-        elsif word16_counter < x"1e" then
+        elsif word16_counter < x"1e" and (DATA_VALID = '1' or TRB_LVL2_BUSY = '0') then
           readout_lvl2_fifo <= word16_counter(0);
+        else
+          readout_lvl2_fifo <= '0';
         end if;
       end if;
     end process READOUT_LVL2_FIFO_PROC;
+    
 
-    etrax_is_ready_to_read_i <= (data_valid_start_pulse or readout_lvl2_fifo) and DATA_VALID;
+--    etrax_is_ready_to_read_i <= (data_valid_start_pulse or readout_lvl2_fifo) and DATA_VALID;
     ETRAX_IS_READY_TO_READ <= readout_lvl2_fifo;
     ETRAX_DATA_BUS_B(16) <= write_to_dma_synch_synch;--(not CLK) and (write_to_dma_synch_synch);
 
@@ -373,12 +412,22 @@ begin
 -- NO DMA
   WITHOUT_DMA_ETRAX_INTERFACE: if ENABLE_DMA = 2 generate
     
-    ETRAX_READY_PULSE      : edge_to_pulse
-      port map (
-      clock     => CLK,
-      en_clk    => '1',              
-      signal_in => ETRAX_DATA_BUS_B_17,
-      pulse     => etrax_is_ready_to_read_i);
+    WITH_TRBNET: if TRBNET_ENABLE = 1 generate
+      etrax_is_ready_to_read_i <= IPU_READY_IN;
+      ETRAX_DATA_BUS_B(16)          <= '0';
+    end generate WITH_TRBNET;
+    IPU_DATAREADY_OUT <= DATA_VALID and (not LVL2_VALID);
+    IPU_DATA_OUT <= data_bus_reg;
+    
+    WITHOUT_TRBNET: if TRBNET_ENABLE /= 1 generate
+      ETRAX_READY_PULSE      : edge_to_pulse
+        port map (
+          clock     => CLK,
+          en_clk    => '1',              
+          signal_in => ETRAX_DATA_BUS_B_17,
+          pulse     => etrax_is_ready_to_read_i);
+      ETRAX_DATA_BUS_B(16)          <= DATA_VALID and (not LVL2_VALID);
+    end generate WITHOUT_TRBNET;
 
   MAKE_PULSES: process (CLK, RESET)
   begin  
@@ -398,30 +447,32 @@ begin
       signal_in => counter_for_pulses(2),
       pulse     => lvl2_not_valid_pulse);
 
+
+  
   ETRAX_IS_READY_TO_READ <= DATA_VALID and ((etrax_is_ready_to_read_i and (not LVL2_VALID)) or (lvl2_not_valid_pulse  and LVL2_VALID));  
 
   TDC_TMS                       <= ETRAX_DATA_BUS_C(1) when rw_register_i(0) = '1' else '1';
   TDC_TCK                       <= ETRAX_DATA_BUS_C(2) when rw_register_i(0) = '1' else '1';
   TDC_TDI                       <= ETRAX_DATA_BUS_C(3) when rw_register_i(0) = '1' else '1';
-  ETRAX_DATA_BUS_C(0)           <= TDC_TDO             when rw_register_i(0) = '1' else DATA_BUS(16);
-  ETRAX_DATA_BUS_C(1)           <= 'Z'                 when rw_register_i(0) = '1' else DATA_BUS(17);
-  ETRAX_DATA_BUS_C(2)           <= 'Z'                 when rw_register_i(0) = '1' else DATA_BUS(18);
-  ETRAX_DATA_BUS_C(3)           <= 'Z'                 when rw_register_i(0) = '1' else DATA_BUS(19);
-  ETRAX_DATA_BUS_C(15 downto 4) <= DATA_BUS(31 downto 20);
-  ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
-  ETRAX_DATA_BUS_B(16)          <= DATA_VALID and (not LVL2_VALID);
-  
+  ETRAX_DATA_BUS_C(0)           <= TDC_TDO             when rw_register_i(0) = '1' else data_bus_reg(16);
+  ETRAX_DATA_BUS_C(1)           <= 'Z'                 when rw_register_i(0) = '1' else data_bus_reg(17);
+  ETRAX_DATA_BUS_C(2)           <= 'Z'                 when rw_register_i(0) = '1' else data_bus_reg(18);
+  ETRAX_DATA_BUS_C(3)           <= 'Z'                 when rw_register_i(0) = '1' else data_bus_reg(19);
+  ETRAX_DATA_BUS_C(15 downto 4) <= data_bus_reg(31 downto 20);
+  ETRAX_DATA_BUS_B(15 downto 0) <= data_bus_reg(15 downto 0);
 
-  REG_DATA_TO_ETRAX: process (CLK, RESET)
-  begin  
-    if rising_edge(CLK) then
-      if RESET = '1' then       
-        data_bus_reg <= (others => '0');
-      else
-        data_bus_reg <= DATA_BUS;
+
+  REG_DATA_TO_ETRAXb:process (CLK, RESET)
+    begin  
+      if rising_edge(CLK) then
+        if RESET = '1' then       
+          data_bus_reg <= (others => '0');
+        else
+          data_bus_reg <= DATA_BUS;
+        end if;
       end if;
-    end if;
-  end process REG_DATA_TO_ETRAX;
+    end process REG_DATA_TO_ETRAXb;
+
 end generate WITHOUT_DMA_ETRAX_INTERFACE;
 
 end etrax_interfacev2;

diff --git a/simulation.pl b/simulation.pl
index 45756815505967bbff48d1753b8feeb4af6cf7cb..87dd3d6e3b3837a71a87681ccfbe223e7850bc5c 100755 (executable)
--- a/simulation.pl
+++ b/simulation.pl
@@ -23,11 +23,15 @@ $c="cp trb_v2b_fpga.vhd trb_v2b_fpga_cts.vhd";
 system($c);
 $c="cp trb_v2b_fpga.vhd trb_v2b_fpga_mdc_or_shower.vhd";
 system($c);
+$c="cp ~/trbnet/trb_net16_med_tlk.vhd .";
+system($c);
+
 my $fh = new FileHandle("< trb_v2b_fpga_cts.vhd");
 my $fh1 = new FileHandle("> temp_perl.vhd");
 my $exchange_a ="trb_v2b_fpga";
 my $exchange_to_a = "trb_v2b_fpga_cts";
 my $exchange_to_b = "trb_v2b_fpga_mdc_or_shower";
+my $exchange_to_c = "trb_v2b_fpga_endpoint";
 my $exchange_b = "--*no sim";
 my $temptext;
 
@@ -94,5 +98,39 @@ $fh7 -> close;
 $c="cp temp_perl.vhd flexi_PCS_channel_synch.vhd";
 system($c);
 
+my $fh8 = new FileHandle("< trb_net16_med_tlk.vhd");
+my $fh9 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh8>)
+{
+    $temptext = $_;
+    $temptext  =~ s/--sim--//;
+    if($temptext =~ /--no_sim--/)
+    {
+       $temptext  = "--".$temptext;
+    }
+    print {$fh9} $temptext;
+}
+$fh8 -> close;
+$fh9 -> close;
+$c="cp temp_perl.vhd trb_net16_med_tlk.vhd";
+system($c);
+
+$c="cp trb_v2b_fpga.vhd trb_v2b_fpga_endpoint.vhd";
+system($c);
+my $fh10 = new FileHandle("< trb_v2b_fpga_endpoint.vhd");
+my $fh11 = new FileHandle("> temp_perl.vhd");
 
+while(<$fh10>)
+{
+    $temptext = $_;
+    $temptext  =~ s/TRBNET_ENABLE        : integer range 0 to 3   :=/TRBNET_ENABLE        : integer range 0 to 3   :=1;--/;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 5   :=/TRBV2_TYPE           : integer range 0 to 5   :=0;--/;
+    $temptext  =~ s/$exchange_a/$exchange_to_c/g;
+    print {$fh11} $temptext;
+}
+$fh10 -> close;
+$fh11 -> close;
+$c="cp temp_perl.vhd trb_v2b_fpga_endpoint.vhd";
+system($c);
 

diff --git a/tdc_interface.vhd b/tdc_interface.vhd
index bbaccbdb599a47248a01cf7dccce977503481da0..2b4073c7cb586046cf91e315a1f582c2c26eb47d 100755 (executable)
--- a/tdc_interface.vhd
+++ b/tdc_interface.vhd
@@ -73,7 +73,7 @@ entity tdc_interface is
     TRIGGER_WITHOUT_HADES    : in std_logic;
     TRIGGER_WITH_GEN_EN      : in std_logic;
     TRIGGER_WITH_GEN         : in std_logic;
-    TRB_ID                   : in std_logic_vector
+    TRB_ID                   : in std_logic_vector(31 downto 0)
     );
 end tdc_interface;
 architecture tdc_interface of tdc_interface is
@@ -151,7 +151,7 @@ architecture tdc_interface of tdc_interface is
     (IDLE ,DELAY_1,DELAY_2);
   signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
   type LVL1_START_FSM is
-      (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG);
+      (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG,WAIT1,WAIT2,WAIT3,WAIT4);
   signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
   type LVL2_START_FSM is
     (IDLE, READOUT_WORD1, READOUT_WORD2 ,READOUT_WORD3 ,SAVE_EVENT_SIZE ,SEND_DATA1, WAIT_FOR_BUSY_END, EB_WORD_0,EB_WORD_1,EB_WORD_2,EB_WORD_3);
@@ -239,7 +239,6 @@ begin
       TDC_REGISTER_01(30 downto 27) <= (others => '0');
       TDC_REGISTER_01(31)           <= etrax_is_busy_i;
       TDC_REGISTER_02(31 downto 0)  <= LVL2_TAG & lvl1_buffer_out(23 downto 0);  --lvl1_fifo_out;
-      --    TDC_REGISTER_03(31 downto 0) <= lvl1_fifo_out;
       TDC_REGISTER_03(31 downto 0)  <= x"0"& LVL1_CODE & LVL1_TAG & x"0" & lvl1_code_i & lvl1_tag_minus1;
       TDC_REGISTER_04(31 downto 0)  <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
     end if;
@@ -250,22 +249,21 @@ begin
   C_TDC_POWERUP        <= '1';
   D_TDC_POWERUP        <= '1';
 
---   SYNC_TDC_DATA : process (TDC_CLK, RESET)
---   begin  -- process SYNC_TDC_DATA
---     if rising_edge(TDC_CLK) then
---       if RESET = '1' then               -- asynchronous reset (active low)
---         tdc_ready      <= '0';
---         lvl1_buffer_in <= (others => '0');
---         GET_TDC_DATA   <= '1';
---       else
-        tdc_ready      <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
-        lvl1_buffer_in <= TDC_DATA_IN;
-        GET_TDC_DATA   <= '1';
---       end if;
---     end if;
---   end process SYNC_TDC_DATA;
-    
-   lvl1_buffer_wr_en <= tdc_ready;
+   SYNC_TDC_DATA : process (TDC_CLK, RESET)
+   begin  -- process SYNC_TDC_DATA
+     if rising_edge(TDC_CLK) then
+       if RESET = '1' then               -- asynchronous reset (active low)
+         tdc_ready      <= '0';
+         lvl1_buffer_in <= (others => '0');
+        else
+          tdc_ready      <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
+          lvl1_buffer_in <= TDC_DATA_IN;
+       end if;
+     end if;
+   end process SYNC_TDC_DATA;
+  
+  GET_TDC_DATA   <= '1';    
+  lvl1_buffer_wr_en <= tdc_ready;
 
   
 --    tdc_ready       <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;       
@@ -492,10 +490,19 @@ begin
         lvl1_buffer_rd_en_fsm <= '0';
         lvl1_busy_i_fsm <= '1';
         if  RECEIVED_TDC_TOKEN = '1' then
-          LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_1;
+          LVL1_START_fsm_nextstate   <= WAIT1;--SAVE_ADD_DATA_1;
         else
-          LVL1_START_fsm_nextstate   <= WAIT_FOR_TOKEN;
+          LVL1_START_fsm_nextstate   <=         WAIT_FOR_TOKEN;
         end if;
+       when WAIT1 =>
+        LVL1_START_fsm_nextstate   <= WAIT2;
+      when WAIT2 =>
+        LVL1_START_fsm_nextstate   <= WAIT3;
+      when WAIT3 =>
+        LVL1_START_fsm_nextstate   <= WAIT4;
+      when WAIT4 =>
+        LVL1_START_fsm_nextstate   <= SAVE_ADD_DATA_1   ;
+        
       when SAVE_ADD_DATA_1 =>
         trigger_register_00_i(5 downto 2) <= x"7";
         lvl1_tdc_trigg_i_fsm         <= '0';
@@ -669,13 +676,37 @@ begin
        end if;
      end if;
    end process TRIGGER_COUNTER_PROC;
- --  words_in_event <= x"0001" + HOW_MANY_ADD_DATA + 2 + lvl1_buffer_counter;
-   lvl1_tag_minus1 <= trigger_counter when TRIGGER_WITH_GEN_EN = '1' else LVL1_TAG - 1;
-   lvl1_code_i <= x"1" when  TRIGGER_WITH_GEN_EN = '1'else LVL1_CODE;
---   first_header  <= x"0" & LVL1_CODE & lvl1_tag_minus1 &  words_in_event;
---   second_header <= x"030000" & HOW_MANY_ADD_DATA;
-   first_header  <= x"0" & lvl1_code_i & lvl1_tag_minus1 &  words_in_event;
-   second_header <= TDC_REGISTER_05(15 downto 8) & x"0000" & HOW_MANY_ADD_DATA;
+
+  SAVE_CODE_AND_TAG : process (CLK, RESET)
+  begin  
+    if rising_edge(CLK) then  
+      if RESET = '1' then
+        lvl1_tag_minus1 <= (others => '0');
+        lvl1_code_i <= (others => '0'); 
+      elsif TRIGGER_WITH_GEN_EN = '1' then
+        lvl1_tag_minus1 <= trigger_counter;
+        lvl1_code_i <= x"1";
+      else
+        lvl1_tag_minus1 <= LVL1_TAG - 1;
+        lvl1_code_i <= LVL1_CODE;
+      end if;
+    end if;
+  end process SAVE_CODE_AND_TAG;
+
+  
+  SYNC_SIGNALS : process (CLK, RESET)
+  begin  
+    if rising_edge(CLK) then  
+      if RESET = '1' then
+        first_header  <= (others => '0');
+        second_header <= (others => '0');
+      else
+        first_header  <= x"0" & lvl1_code_i & lvl1_tag_minus1 &  words_in_event;
+        second_header <= TDC_REGISTER_05(15 downto 8) & x"0000" & HOW_MANY_ADD_DATA;
+      end if;
+    end if;
+  end process SYNC_SIGNALS;
+  
   -----------------------------------------------------------------------------
   ----------------------------------------------------------------------------
   -- LVL2 logic (only CLK domain)
@@ -751,6 +782,7 @@ begin
      TDC_DATA_OUT <= lvl1_fifo_out; 
      case (LVL2_START_fsm_currentstate) is
        when IDLE =>
+         TDC_DATA_OUT <= (others => '0');
          lvl2_busy_i <= '0';
          lvl2_debug (2 downto 0) <= "001";
          lvl1_fifo_rd_en_fsm <= '0';--lvl1_fifo_rd_en_empty_pulse;--'0';
@@ -986,7 +1018,7 @@ begin
 
    --  lvl1_memory_busy_i <= '1' when lvl1_fifo_counter(13) = '1' else '0';
    lvl1_memory_busy_i <= '1' when lvl1_fifo_busy_counter(13) = '1' and lvl1_fifo_busy_counter(12) = '1'else '0';   
-  REGITERING_SIGNALS: process (CLK, RESET)
+  REGISTERING_SIGNALS: process (CLK, RESET)
   begin 
     if rising_edge(CLK) then  -- rising clock edge
       if RESET = '1' then  
@@ -995,7 +1027,7 @@ begin
         LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i;  --here
       end if;
     end if;
-  end process REGITERING_SIGNALS;
+  end process REGISTERING_SIGNALS;
   
 end tdc_interface;
 

diff --git a/trb_v2b_fpga.stapl b/trb_v2b_fpga.stapl
index f516b34df510ed7bab046517672a9f120ded35d9..9b809887084d8c46bb9ddfe7deb8bc67b58dbd45 100644 (file)
--- a/trb_v2b_fpga.stapl
+++ b/trb_v2b_fpga.stapl
@@ -1,5 +1,5 @@
 NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2009/05/28";
+NOTE "DATE" "2009/07/24";
 NOTE "STAPL_VERSION" "JESD71";
 NOTE "ALG_VERSION" "1";
 NOTE "DEVICE" "UNSPECIFIED";
@@ -1258,1258 +1258,6519 @@ IF (!X) THEN GOTO F;
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  ;
 ' // Loading device with a `jstart` instruction. 
 IRSCAN 10, $03cc
  ;
-D = 12;
+' // INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
+' // INFO :  increased to ensure correct operation of generated System Ace files.
+D = 1200;
 WAIT D CYCLES;
 ' //Loading device with 'bypass' instruction.
 IRSCAN 10, $03ff
@@ -4182,7 +7847,9 @@ POSTDR 0 ;
 ' // Loading device with a `jstart` instruction. 
 IRSCAN 10, $03cc
  ;
-D = 12;
+' // INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
+' // INFO :  increased to ensure correct operation of generated System Ace files.
+D = 1200;
 WAIT D CYCLES;
 ' //Checking done pin status.
 ' //Loading device with 'Bypass' instruction.
@@ -4231,4 +7898,4 @@ IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
 IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
 ENDPROC;
 
-CRC B812;
+CRC A7B6;

diff --git a/trb_v2b_fpga.ucf b/trb_v2b_fpga.ucf
index 41c361842ea9e888e7467a11b62550ca7b6f5410..4adff0f2c8c71fbb1051ad592e27f30795bea176 100644 (file)
--- a/trb_v2b_fpga.ucf
+++ b/trb_v2b_fpga.ucf
@@ -4,69 +4,73 @@
    NET  ADDON_TO_TRB_CLKINN      LOC ="G16";
    NET  ADDON_TO_TRB_CLKINP      LOC ="G17";
    NET "ADDON_TO_TRB_CLKINP" TNM_NET = ADDON_TO_TRB_CLKINP;
-#   TIMESPEC TS_ADDON_TO_TRB_CLKINP =PERIOD "ADDON_TO_TRB_CLKINP" 9 ns; # ADDON_CONSTRAINTS
-   NET  ADO_LV<0>        LOC ="AC9";
-   NET  ADO_LV<1>        LOC ="AC8";
-   NET  ADO_LV<2>        LOC ="AG3";
-   NET  ADO_LV<3>        LOC ="AF3";
-   NET  ADO_LV<4>        LOC ="AF6";
-   NET  ADO_LV<5>        LOC ="AE6";
-   NET  ADO_LV<6>        LOC ="AF5";
-   NET  ADO_LV<7>        LOC ="AF4";
-   NET  ADO_LV<8>        LOC ="AL1";
-   NET  ADO_LV<9>        LOC ="AK1";
-   NET  ADO_LV<10>       LOC ="AJ2";
-   NET  ADO_LV<11>       LOC ="AJ1";
-   NET  ADO_LV<12>       LOC ="AB6";
-   NET  ADO_LV<13>       LOC ="AB5";
-   NET  ADO_LV<14>       LOC ="AC3";
-   NET  ADO_LV<15>       LOC ="AC2";
-   NET  ADO_LV<16>       LOC ="Y11";
-   NET  ADO_LV<17>       LOC ="AA11";
-   NET  ADO_LV<18>       LOC ="AD2";
-   NET  ADO_LV<19>       LOC ="AD1";
-   NET  ADO_LV<20>       LOC ="Y14";
-   NET  ADO_LV<21>       LOC ="AA13";
-   NET  ADO_LV<22>       LOC ="AC5";
-   NET  ADO_LV<23>       LOC ="AC4";
-   NET  ADO_LV<24>       LOC ="AF1";
-   NET  ADO_LV<25>       LOC ="AE1";
-   NET  ADO_LV<26>       LOC ="AE3";
-   NET  ADO_LV<27>       LOC ="AE2";
-   NET  ADO_LV<28>       LOC ="AD6";
-   NET  ADO_LV<29>       LOC ="AD5";
-   NET  ADO_LV<30>       LOC ="AC7";
-   NET  ADO_LV<31>       LOC ="AB8";
-   NET  ADO_LV<32>       LOC ="Y16";
-   NET  ADO_LV<33>       LOC ="AA15";
-   NET  ADO_LV<34>       LOC ="AE4";
-   NET  ADO_LV<35>       LOC ="AD4";
-   NET  ADO_LV<36>       LOC ="AH3";
-   NET  ADO_LV<37>       LOC ="AH2";
-   NET  ADO_LV<38>       LOC ="AG2";
-   NET  ADO_LV<39>       LOC ="AG1";
-   NET  ADO_LV<40>       LOC ="AK3";
-   NET  ADO_LV<41>       LOC ="AK2";
-   NET  ADO_LV<42>       LOC ="AF8";
-   NET  ADO_LV<43>       LOC ="AE8";
-   NET  ADO_LV<44>       LOC ="AH5";
-   NET  ADO_LV<45>       LOC ="AH4";
-   NET  ADO_LV<46>       LOC ="AB13";
-   NET  ADO_LV<47>       LOC ="AB12";
-   NET  ADO_LV<48>       LOC ="AM2";
-   NET  ADO_LV<49>       LOC ="AM1";
-   NET  ADO_LV<50>       LOC ="AG8";
-   NET  ADO_LV<51>       LOC ="AG7";
-##   NET  ADO_LV<52>     LOC ="AM3";
-##   NET  ADO_LV<53>     LOC ="AL3";
-##   NET  ADO_LV<54>     LOC ="AK22";
-##   NET  ADO_LV<55>     LOC ="AK23";
-##   NET  ADO_LV<56>     LOC ="AL28";
-##   NET  ADO_LV<57>     LOC ="AL29";
-##   NET  ADO_LV<58>     LOC ="AP25";
-##  NET  ADO_LV<59>      LOC ="AP26";
-##  NET  ADO_LV<60>      LOC ="AJ27";
-##  NET  ADO_LV<61>      LOC ="AH27";
+#   TIMESPEC TS_ADDON_TO_TRB_CLKINP =PERIOD "ADDON_TO_TRB_CLKINP" 9 ns; #
+  # ADDON_CONSTRAINTS
+#################LVDS lines names are diiferent then in schematics 0 - 51 - in
+  # 52 - 61 LVDS out
+   NET  ADO_LVDS_IN<0>   LOC ="AC9";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<1>   LOC ="AC8";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<2>   LOC ="AG3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<3>   LOC ="AF3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<4>   LOC ="AF6";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<5>   LOC ="AE6";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<6>   LOC ="AF5";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<7>   LOC ="AF4";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<8>   LOC ="AL1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<9>   LOC ="AK1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<10>          LOC ="AJ2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<11>          LOC ="AJ1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<12>          LOC ="AB6";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<13>          LOC ="AB5";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<14>          LOC ="AC3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<15>          LOC ="AC2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<16>          LOC ="Y11";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<17>          LOC ="AA11";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<18>          LOC ="AD2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<19>          LOC ="AD1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<20>          LOC ="Y14";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<21>          LOC ="AA13";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<22>          LOC ="AC5";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<23>          LOC ="AC4";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<24>          LOC ="AF1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<25>          LOC ="AE1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<26>          LOC ="AE3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<27>          LOC ="AE2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<28>          LOC ="AD6";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<29>          LOC ="AD5";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<30>          LOC ="AC7";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<31>          LOC ="AB8";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<32>          LOC ="Y16";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<33>          LOC ="AA15";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<34>          LOC ="AE4";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<35>          LOC ="AD4";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<36>          LOC ="AH3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<37>          LOC ="AH2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<38>          LOC ="AG2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<39>          LOC ="AG1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<40>          LOC ="AK3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<41>          LOC ="AK2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<42>          LOC ="AF8";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<43>          LOC ="AE8";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<44>          LOC ="AH5";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<45>          LOC ="AH4";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<46>          LOC ="AB13";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<47>          LOC ="AB12";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<48>          LOC ="AM2";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<49>          LOC ="AM1";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<50>          LOC ="AG8";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_IN<51>          LOC ="AG7";#| IOSTANDARD="LVDS_25";
+
+   NET  ADO_LVDS_OUT<0>          LOC ="AM3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<1>          LOC ="AL3";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<2>          LOC ="AK22";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<3>          LOC ="AK23";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<4>          LOC ="AL28";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<5>          LOC ="AL29";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<6>          LOC ="AP25";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<7>          LOC ="AP26";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<8>          LOC ="AJ27";#| IOSTANDARD="LVDS_25";
+   NET  ADO_LVDS_OUT<9>          LOC ="AH27";#| IOSTANDARD="LVDS_25";
 #   NET  ADO_TTL         LOC ="AL11"| IOSTANDARD = "LVTTL";
    NET  ADO_TTL<0>       LOC ="AL11"| IOSTANDARD = "LVTTL";
    NET  ADO_TTL<1>       LOC ="AL10"| IOSTANDARD = "LVTTL";
@@ -131,7 +135,7 @@
    NET  A_TDC_EV_RESET   LOC ="AK24";
    NET  A_TDC_EV_RESETB          LOC ="AJ24";
    NET  A_TDC_POWERUP    LOC ="H8"| IOSTANDARD = "LVTTL";
-   NET  A_TEMP   LOC ="B7"| IOSTANDARD = "LVTTL";
+   NET  TEMP_SENS<0>     LOC ="B7"| IOSTANDARD = "LVTTL";
    NET  A_TEST1B         LOC ="N7";
    NET  A_TEST2B         LOC ="L4";
    NET  A_TEST1          LOC ="M7";
@@ -154,7 +158,7 @@
    NET  B_TDC_EV_RESET   LOC ="AG23";
    NET  B_TDC_EV_RESETB          LOC ="AF24";
    NET  B_TDC_POWERUP    LOC ="H7"| IOSTANDARD = "LVTTL";
-   NET  B_TEMP   LOC ="A10"| IOSTANDARD = "LVTTL";
+   NET  TEMP_SENS<1>     LOC ="A10"| IOSTANDARD = "LVTTL";
    NET  B_TEST2B         LOC ="L9";
    NET  B_TEST1B         LOC ="E4";
    NET  B_TEST1          LOC ="D4";
@@ -177,7 +181,7 @@
    NET  C_TDC_EV_RESET   LOC ="AP27";
    NET  C_TDC_EV_RESETB          LOC ="AN27";
    NET  C_TDC_POWERUP    LOC ="K8"| IOSTANDARD = "LVTTL";
-   NET  C_TEMP   LOC ="A9"| IOSTANDARD = "LVTTL";
+   NET  TEMP_SENS<2>     LOC ="A9"| IOSTANDARD = "LVTTL";
    NET  C_TEST2B         LOC ="N12";
    NET  C_TEST1B         LOC ="D2";
    NET  C_TEST1          LOC ="C2";
@@ -347,7 +351,7 @@
    NET  D_TDC_EV_RESET   LOC ="L8";
    NET  D_TDC_EV_RESETB          LOC ="M8";
    NET  D_TDC_POWERUP    LOC ="J7"| IOSTANDARD = "LVTTL";
-   NET  D_TEMP   LOC ="C14"| IOSTANDARD = "LVTTL";
+   NET  TEMP_SENS<3>     LOC ="C14"| IOSTANDARD = "LVTTL";
    NET  D_TEST1B         LOC ="M1";
    NET  D_TEST2B         LOC ="P5";
    NET  D_TEST1          LOC ="L1";
@@ -477,8 +481,11 @@
    NET  RESET_VIRT       LOC ="AF16"| IOSTANDARD = "LVTTL";
    NET  SFP_LOS          LOC ="M27"| IOSTANDARD = "LVTTL";
  # NET  SFP_MOD<0>       LOC ="R23"| IOSTANDARD = "LVTTL";
- # NET  SFP_MOD<1>       LOC ="K32"| IOSTANDARD = "LVTTL";
- # NET  SFP_MOD<2>       LOC ="K33"| IOSTANDARD = "LVTTL";
+#  NET  SFP_MOD<1>       LOC ="K32"| IOSTANDARD = "LVTTL";
+#  NET  SFP_MOD<2>       LOC ="K33"| IOSTANDARD = "LVTTL";
+#names not like in the schematics !
+  NET  SCL       LOC ="K32"| IOSTANDARD = "LVTTL";
+  NET  SDA       LOC ="K33"| IOSTANDARD = "LVTTL";
  # NET  SFP_RATE_SEL     LOC ="P27"| IOSTANDARD = "LVTTL";
    NET  SFP_TX_DIS       LOC ="N27"| IOSTANDARD = "LVTTL";
    NET  SFP_TX_FAULT     LOC ="J32"| IOSTANDARD = "LVTTL";
@@ -570,8 +577,8 @@
    NET  VIRT_TDO         LOC ="N30"| IOSTANDARD = "LVTTL";
    NET  VIRT_TMS         LOC ="J34"| IOSTANDARD = "LVTTL";
    NET  VIRT_TRST        LOC ="N29"| IOSTANDARD = "LVTTL";
-   NET  VIR_TRIG         LOC ="E3";
-   NET  VIR_TRIGB        LOC ="E2";
+   NET  VIR_TRIG         LOC ="E3"| IOSTANDARD="LVDS_25";
+   NET  VIR_TRIGB        LOC ="E2"| IOSTANDARD="LVDS_25";
 #   NET  VSD_A<0>        LOC ="F23"| IOSTANDARD = "LVTTL";
 #   NET  VSD_A<1>        LOC ="E23"| IOSTANDARD = "LVTTL";
 #   NET  VSD_A<2>        LOC ="D26"| IOSTANDARD = "LVTTL";
@@ -639,7 +646,7 @@
  NET "VIRT_CLK" TNM_NET =VIRT_CLK;
  TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
  NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
-#  TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 25 ns;
+ TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 22 ns;
 
  NET "CLK" TNM_NET=CLK;
  TIMESPEC TS_CLK =PERIOD "CLK" 9 ns;
@@ -732,14 +739,17 @@ TIMEGRP "ETRAX_NET_GROUP" OFFSET = OUT 12 ns AFTER "VIRT_CLK" HIGH;
 
 # TIMEGRP "TDC_NET_GROUP" OFFSET = IN 11 ns AFTER "REF_TDC_CLK" HIGH;
 
- TIMESPEC "TS_TDC_NET_FFS" = FROM TDC_NET_GROUP TO RAMS 5;
+ TIMEGRP "TDC_NET_GROUP" OFFSET = IN 10 ns BEFORE "REF_TDC_CLK" HIGH;
 
  NET "TOKEN_OUT" OFFSET = OUT 12.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "A_TRIGGER" OFFSET = OUT 11.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "B_TRIGGER" OFFSET = OUT 11.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "C_TRIGGER" OFFSET = OUT 11.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "D_TRIGGER" OFFSET = OUT 11.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
-
+ NET "ADO_TTL<1>" OFFSET = OUT 11.3 ns AFTER "REF_TDC_CLK" HIGH;
+ NET "ADO_TTL<7>" OFFSET = OUT 12.3 ns AFTER "REF_TDC_CLK" HIGH;
+ NET "ADO_TTL<12>" OFFSET = OUT 0 ns AFTER "REF_TDC_CLK" HIGH;
+ 
  NET "A_TDC_BU_RESET" OFFSET = OUT 12.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "A_TDC_EV_RESET" OFFSET = OUT 12.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS
  NET "B_TDC_BU_RESET" OFFSET = OUT 12.3 ns AFTER "REF_TDC_CLK" HIGH; #TDC_COINSTRAINTS

diff --git a/trb_v2b_fpga.vhd b/trb_v2b_fpga.vhd
index 1bf86bd9f68d4bc2fb9132623d593d7ac2301442..7e5790f7cc640d6b962f73ce82d9e8424e77da80 100644 (file)
--- a/trb_v2b_fpga.vhd
+++ b/trb_v2b_fpga.vhd
@@ -1,67 +1,69 @@
 library IEEE;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
 library UNISIM;
 use UNISIM.VCOMPONENTS.all;
-library ieee;
+
 library work;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
 use work.all;
---use work.version.all;
+use work.version.all;
 use work.trb_net_std.all;
 
 entity trb_v2b_fpga is
   generic (
-    RW_SYSTEM            : integer range 1 to 2 := 1;  --1 -trb, 2 -addon with portE 10 9 as rw
-    TRBV2_TYPE           : integer range 0 to 5 := 0;
+    RW_SYSTEM            : integer range 1 to 2   := 1;  --1 -trb, 2 -addon with portE 10 9 as rw
+    TRBV2_TYPE           : integer range 0 to 5   := 5;
                                         -- 0 - trbv2 + RPC or TOF or FWALL or Start or Veto,
                                         -- 1 - MDC,
                                         -- 2 - SHOWER,
                                         -- 3 - RICH
                                         -- 4 - CTS+VULOM
                                         -- 5 - CTS only, lvl2 is automatic
-    TRBNET_ENABLE        : integer range 0 to 3 := 0;  -- 0 - disable,
-                                                       -- 1 - end point
-                                                       -- 2 - cts
-                                                       -- 3 slow ctrl
-    DTU_ENABLE           : integer range 0 to 2 := 0;  -- 0 - disable, 1 - old
-                                                       -- HADES bus, 2 - opt
-                                                       -- without trbnet
-    CTU_ENABLE           : integer range 0 to 1 := 0;
-    HADES_OLD_BUS_ENABLE : integer range 0 to 1 := 0;
-    DSP_INT_ENABLE       : integer range 0 to 1 := 0;  -- dsp interface enable
-    SDRAM_INT_ENABLE     : integer range 0 to 1 := 0;  -- sdram interface enable
-    SCALERS_ENABLE       : integer range 0 to 1 := 0;
-    RW_REGISTERS_NUMBER  : integer range 0 to 40 := 5;  --32 bit registers
-                                                        --accesed by trbnet or
-                                                        --etrax (read/write) -
-                                                        --control
-    R_REGISTERS_NUMBER   : integer range 0 to 40 := 15; --only read - status
-    ENABLE_DMA           : integer range 1 to 2 := 1;  --1- DMA , 2 - no DMA
-    NUMBER_OFF_ADD_DATA  : integer range 0 to 255 := 8 
-   );
+    TRBNET_ENABLE        : integer range 0 to 3   := 2;  -- 0 - disable,
+                                        -- 1 - end point
+                                        -- 2 - cts
+                                        -- 3 - slow ctrl
+    DTU_ENABLE           : integer range 0 to 2   := 0;  -- 0 - disable, 1 - old
+                                        -- HADES bus, 2 - opt
+                                        -- without trbnet
+    CTU_ENABLE           : integer range 0 to 1   := 0;
+    HADES_OLD_BUS_ENABLE : integer range 0 to 1   := 0;
+    DSP_INT_ENABLE       : integer range 0 to 1   := 0;  -- dsp interface enable
+    SDRAM_INT_ENABLE     : integer range 0 to 1   := 0;  -- sdram interface enable
+    SCALERS_ENABLE       : integer range 0 to 1   := 0;
+    RW_REGISTERS_NUMBER  : integer range 0 to 40  := 8;  --32 bit registers
+                                        --accesed by trbnet or
+                                        --etrax (read/write) -
+                                        --control
+    R_REGISTERS_NUMBER   : integer range 0 to 40  := 22; --only read  - status
+    ENABLE_DMA           : integer range 1 to 2   := 2;  --1- DMA , 2 - no DMA
+    NUMBER_OFF_ADD_DATA  : integer range 0 to 255 := 8;
+    REGIO_NUM_STAT_REGS  : integer range 0 to 255 := 2;
+    REGIO_NUM_CTRL_REGS : integer range  0 to 255 := 3
+    );
   port (
     -------------------------------------------------------------------------
     -- GENERAL 
     -------------------------------------------------------------------------
-    VIRT_CLK        : in  std_logic;
-    VIRT_CLKB       : in  std_logic;
-    RESET_VIRT      : in  std_logic;
-    DBAD            : out std_logic;    --diode 
-    DGOOD           : out std_logic;    --diode
-    DINT            : out std_logic;    --diode
-    DWAIT           : out std_logic;    --diode
-    A_RESERVED      : in  std_logic;    --TDC connector 75,76(line 3 from end)
-    A_TEMP          : in  std_logic;    -- |
-    B_RESERVED      : in  std_logic;    -- |
-    B_TEMP          : in  std_logic;    -- V
-    C_RESERVED      : in  std_logic;
-    C_TEMP          : in  std_logic;
-    D_RESERVED      : in  std_logic;
-    D_TEMP          : in  std_logic;
-    VIR_TRIG        : in  std_logic;    --fast trigger 
-    VIR_TRIGB       : in  std_logic;
+    VIRT_CLK   : in    std_logic;
+    VIRT_CLKB  : in    std_logic;
+    RESET_VIRT : in    std_logic;
+    DBAD       : out   std_logic;       --diode 
+    DGOOD      : out   std_logic;       --diode
+    DINT       : out   std_logic;       --diode
+    DWAIT      : out   std_logic;       --diode
+    A_RESERVED : in    std_logic;       --TDC connector 75,76(line 3 from end)
+    TEMP_SENS  : inout std_logic_vector(3 downto 0);  -- on the schematics
+                                        -- A_TEMP,B_TEMP ...
+
+    B_RESERVED : in std_logic;
+    C_RESERVED : in std_logic;
+    D_RESERVED : in std_logic;
+    VIR_TRIG   : in std_logic;          --fast trigger 
+    VIR_TRIGB  : in std_logic;
     -------------------------------------------------------------------------
     -- TDC connections
     -------------------------------------------------------------------------
@@ -273,7 +275,9 @@ entity trb_v2b_fpga is
     --  SFP_MOD<0>        LOC = R23;
     --  SFP_MOD<1>        LOC = K32;
     --  SFP_MOD<2>        LOC = K33;
-    --  SFP_RATE_SEL      : out std_logic; 
+    --  SFP_RATE_SEL      : out std_logic;
+      SCL               : inout std_logic;
+      SDA               : inout std_logic;
       SFP_TX_DIS        : out std_logic;
       SFP_TX_FAULT      : in std_logic;
       
@@ -282,7 +286,8 @@ entity trb_v2b_fpga is
     -------------------------------------------------------------------------
      ADDON_TO_TRB_CLKINN       : in std_logic;
      ADDON_TO_TRB_CLKINP       : in std_logic;
-     ADO_LV                    : in std_logic_vector(51 downto 0);  --lvds signal
+     ADO_LVDS_IN                 : in std_logic_vector(51 downto 0);  --lvds signal
+     ADO_LVDS_OUT                : out std_logic_vector(9 downto 0);  --lvds signal
      ADO_TTL                   : inout std_logic_vector(46 downto 0);
  --     ADO_TTL                   : inout std_logic_vector(15 downto 0);
 --      ADO_TTL                   : in std_logic;
@@ -299,165 +304,143 @@ entity trb_v2b_fpga is
   
     end trb_v2b_fpga;
 architecture trb_v2b_fpga of trb_v2b_fpga is
-
-
-  component trb_net16_endpoint_hades_full
+  component Sfp_Interface
     generic (
-      USE_CHANNEL               : channel_config_t;
-      IBUF_DEPTH                : channel_config_t;
-      FIFO_TO_INT_DEPTH         : channel_config_t;
-      FIFO_TO_APL_DEPTH         : channel_config_t;
-      IBUF_SECURE_MODE          : channel_config_t;
-      API_SECURE_MODE_TO_APL    : channel_config_t;
-      API_SECURE_MODE_TO_INT    : channel_config_t;
-      OBUF_DATA_COUNT_WIDTH     : integer range 0 to 7;
-      INIT_CAN_SEND_DATA        : channel_config_t;
-      REPLY_CAN_SEND_DATA       : channel_config_t;
-      REPLY_CAN_RECEIVE_DATA    : channel_config_t;
-      USE_CHECKSUM              : channel_config_t;
-      APL_WRITE_ALL_WORDS       : channel_config_t;
-      BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
-      REGIO_NUM_STAT_REGS       : integer range 0 to 6;
-      REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
-      REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
-      REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
-      REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
-      REGIO_USE_DAT_PORT        : integer range 0 to 1;
-      REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
-      REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
-      REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
-      REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
-      REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
-      REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
-      REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
-      REGIO_USE_1WIRE_INTERFACE : integer);
+      TEMP_START_ADD   : std_logic_vector(7 downto 0);
+      TEMP_STOP_ADD    : std_logic_vector(7 downto 0);
+      OP_PWR_START_ADD : std_logic_vector(7 downto 0);
+      OP_PWR_STOP_ADD  : std_logic_vector(7 downto 0);
+      DEVICE_ADD       : std_logic_vector(7 downto 0);
+      I2C_SPEED        : std_logic_vector(7 downto 0));
     port (
-      CLK                       : in    std_logic;
-      RESET                     : in    std_logic;
-      CLK_EN                    : in    std_logic;
-      MED_DATAREADY_OUT         : out   std_logic;
-      MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_IN               : in    std_logic;
-      MED_DATAREADY_IN          : in    std_logic;
-      MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_OUT              : out   std_logic;
-      MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
-      MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
-      LVL1_TRG_TYPE_OUT         : out   std_logic_vector(3 downto 0);
-      LVL1_TRG_RECEIVED_OUT     : out   std_logic;
-      LVL1_TRG_NUMBER_OUT       : out   std_logic_vector(15 downto 0);
-      LVL1_TRG_CODE_OUT         : out   std_logic_vector(7 downto 0);
-      LVL1_TRG_INFORMATION_OUT  : out   std_logic_vector(7 downto 0);
-      LVL1_ERROR_PATTERN_IN     : in    std_logic_vector(31 downto 0)                            := x"00000000";
-      LVL1_TRG_RELEASE_IN       : in    std_logic                                                := '0';
-      IPU_NUMBER_OUT            : out   std_logic_vector (15 downto 0);
-      IPU_INFORMATION_OUT       : out   std_logic_vector (7 downto 0);
-      IPU_START_READOUT_OUT     : out   std_logic;
-      IPU_DATA_IN               : in    std_logic_vector (31 downto 0);
-      IPU_DATAREADY_IN          : in    std_logic;
-      IPU_READOUT_FINISHED_IN   : in    std_logic;
-      IPU_READ_OUT              : out   std_logic;
-      IPU_LENGTH_IN             : in    std_logic_vector (15 downto 0);
-      IPU_ERROR_PATTERN_IN      : in    std_logic_vector (31 downto 0);
-      REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
-      REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-      REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-      REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-      REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
-      REGIO_READ_ENABLE_OUT     : out   std_logic;
-      REGIO_WRITE_ENABLE_OUT    : out   std_logic;
-      REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
-      REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
-      REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
-      REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
-      REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
-      REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
-      REGIO_TIMEOUT_OUT         : out   std_logic;
-      REGIO_IDRAM_DATA_IN       : in    std_logic_vector(15 downto 0)                            := (others => '0');
-      REGIO_IDRAM_DATA_OUT      : out   std_logic_vector(15 downto 0);
-      REGIO_IDRAM_ADDR_IN       : in    std_logic_vector(2 downto 0)                             := "000";
-      REGIO_IDRAM_WR_IN         : in    std_logic                                                := '0';
-      REGIO_ONEWIRE_INOUT       : inout std_logic;
-      REGIO_EXT_REG_DATA_IN     : in    std_logic_vector(31 downto 0)                            := (others => '0');
-      REGIO_EXT_REG_DATA_OUT    : out   std_logic_vector(31 downto 0);
-      REGIO_EXT_REG_WRITE_IN    : in    std_logic                                                := '0';
-      REGIO_EXT_REG_ADDR_IN     : in    std_logic_vector(7 downto 0)                             := (others => '0');
-      STAT_DEBUG_IPU            : out   std_logic_vector (31 downto 0);
-      STAT_DEBUG_1              : out   std_logic_vector (31 downto 0);
-      STAT_DEBUG_2              : out   std_logic_vector (31 downto 0);
-      MED_STAT_OP               : out   std_logic_vector (15 downto 0);
-      CTRL_MPLEX                : in    std_logic_vector (31 downto 0);
-      IOBUF_CTRL_GEN            : in    std_logic_vector (4*32-1 downto 0);
-      STAT_ONEWIRE              : out   std_logic_vector (31 downto 0);
-      STAT_ADDR_DEBUG           : out   std_logic_vector (15 downto 0));
+      CLK_IN           : in    std_logic;
+      RST_IN           : in    std_logic;
+      EN_SFP_INTERFACE : in    std_logic;
+      TEMP_DATA_OUT    : out   std_logic_vector(15 downto 0);
+      OPT_DATA_OUT     : out   std_logic_vector(15 downto 0);
+      SCL              : inout std_logic;
+      SDA              : inout std_logic;
+      BIT_CTRL_DEBUG   : out   std_logic_vector(23 downto 0);
+      BYTE_CTRL_DEBUG  : out   std_logic_vector(15 downto 0));
   end component;
-
-
   
-  component trb_net16_endpoint_0_trg_1_api
+  component cts
     generic (
-      API_TYPE                : integer range 0 to 1 := c_API_PASSIVE;
-      IBUF_DEPTH              : integer range 0 to 6 := 6;--c_FIFO_BRAM;
-      FIFO_TO_INT_DEPTH       : integer range 0 to 6 := 6;--c_FIFO_SMALL;
-      FIFO_TO_APL_DEPTH       : integer range 0 to 6 := 0;--c_FIFO_SMALL;
-      SBUF_VERSION            : integer range 0 to 1 := c_SBUF_FULL;
-      IBUF_SECURE_MODE        : integer range 0 to 1 := c_SECURE_MODE;
-      API_SECURE_MODE_TO_APL  : integer range 0 to 1 := c_NON_SECURE_MODE;
-      API_SECURE_MODE_TO_INT  : integer range 0 to 1 := c_SECURE_MODE;
-      OBUF_DATA_COUNT_WIDTH   : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
-      INIT_CAN_SEND_DATA      : integer range 0 to 1 := c_NO;
-      REPLY_CAN_SEND_DATA     : integer range 0 to 1 := c_YES;
-      USE_CHECKSUM            : integer range 0 to 1 := c_YES;
-      DAT_CHANNEL             : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL
-      );
+      TRBNET_ENABLE : natural);
     port (
-      CLK                      : in  std_logic;
-      RESET                    : in  std_logic;
-      CLK_EN                   : in  std_logic;
-      MED_DATAREADY_OUT        : out std_logic;
-        MED_DATA_OUT             : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-        MED_PACKET_NUM_OUT       : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-        MED_READ_IN              : in  std_logic;
-        MED_DATAREADY_IN         : in  std_logic;
-        MED_DATA_IN              : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-        MED_PACKET_NUM_IN        : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-        MED_READ_OUT             : out std_logic;
-        MED_ERROR_IN             : in  std_logic_vector (2 downto 0);
-        MED_STAT_OP              : in  std_logic_vector (15 downto 0);
-        MED_CTRL_OP              : out std_logic_vector (15 downto 0);
-        APL_DATA_IN              : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-        APL_PACKET_NUM_IN        : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-        APL_DATAREADY_IN         : in  std_logic;
-        APL_READ_OUT             : out std_logic;
-        APL_SHORT_TRANSFER_IN    : in  std_logic;
-        APL_DTYPE_IN             : in  std_logic_vector (3 downto 0);
-        APL_ERROR_PATTERN_IN     : in  std_logic_vector (31 downto 0);
-        APL_SEND_IN              : in  std_logic;
-        APL_TARGET_ADDRESS_IN    : in  std_logic_vector (15 downto 0);
-        APL_DATA_OUT             : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-        APL_PACKET_NUM_OUT       : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-        APL_TYP_OUT              : out std_logic_vector (2 downto 0);
-        APL_DATAREADY_OUT        : out std_logic;
-        APL_READ_IN              : in  std_logic;
-        APL_RUN_OUT              : out std_logic;
-        APL_MY_ADDRESS_IN        : in  std_logic_vector (15 downto 0);
-        APL_SEQNR_OUT            : out std_logic_vector (7 downto 0);
-        STAT_GEN                 : out std_logic_vector (31 downto 0);
-        STAT_LOCKED              : out std_logic_vector (31 downto 0);
-        STAT_INIT_BUFFER         : out std_logic_vector (31 downto 0);
-        STAT_REPLY_BUFFER        : out std_logic_vector (31 downto 0);
-        STAT_api_control_signals : out std_logic_vector(31 downto 0);
-        STAT_MPLEX               : out std_logic_vector(31 downto 0);
-        CTRL_GEN                 : in  std_logic_vector (31 downto 0);
-        CTRL_LOCKED              : in  std_logic_vector (31 downto 0);
-        STAT_CTRL_INIT_BUFFER    : in  std_logic_vector (31 downto 0);
-        STAT_CTRL_REPLY_BUFFER   : in  std_logic_vector (31 downto 0);
-        MPLEX_CTRL               : in  std_logic_vector (31 downto 0);
-        API_STAT_FIFO_TO_INT     : out std_logic_vector(31 downto 0);
-        API_STAT_FIFO_TO_APL     : out std_logic_vector(31 downto 0));
-    end component;
+      RESET                      : in  std_logic;
+      CLK                        : in  std_logic;
+      CLK40_IN                   : in  std_logic;
+      LVL1_LVDS_TRIGGER_IN       : in  std_logic_vector(4 downto 0);
+      LVL1_TTL_TRIGGER_IN        : in  std_logic_vector(4 downto 0);
+      LVL1_FAST_TRIGG_IN         : in  std_logic;
+      LVL1_TIMING_TRIGGER_OUT    : out std_logic;
+      LVL1_APV_TRIGGER_OUT       : out std_logic;
+      LVL1_VULOM_TRIGGER_IN      : in  std_logic;
+      LVL1_VULOM_TRIGGER_CODE_IN : in  std_logic_vector(3 downto 0);
+      LVL1_VULOM_TRIGGER_TAG_IN  : in  std_logic_vector(15 downto 0);
+      LVL1_VULOM_BUSY_IN         : in  std_logic;
+      LVL1_LOCAL_BUSY            : in  std_logic;
+      LVL1_TRBNET_BUSY           : in  std_logic;
+      LVL1_CTS_BUSY_OUT          : out std_logic;
+      LVL1_TRIGGER_OUT           : out std_logic;
+      LVL1_TRIGGER_CODE_OUT      : out std_logic_vector(3 downto 0);
+      LVL1_TRIGGER_TAG_OUT       : out std_logic_vector(15 downto 0);
+      LVL1_RND_NUMBER_OUT        : out std_logic_vector(7 downto 0);
+      LVL2_LVDS_TRIGGER_IN       : in  std_logic;
+      LVL2_LVDS_TRIGGER_CODE_IN  : in  std_logic_vector(3 downto 0);
+      LVL2_LVDS_TRIGGER_TAG_IN   : in  std_logic_vector(15 downto 0);
+      LVL2_LOCAL_TRIGGER_IN      : in  std_logic;
+      LVL2_LOCAL_TRIGGER_CODE_IN : in  std_logic_vector(3 downto 0);
+      LVL2_LOCAL_TRIGGER_TAG_IN  : in  std_logic_vector(15 downto 0);
+      LVL2_LOCAL_BUSY            : in  std_logic;
+      LVL2_TRBNET_BUSY           : in  std_logic;
+      LVL2_CTS_BUSY_OUT          : out std_logic;
+      LVL2_TRIGGER_OUT           : out std_logic;
+      LVL2_TRIGGER_CODE_OUT      : out std_logic_vector(3 downto 0);
+      LVL2_TRIGGER_TAG_OUT       : out std_logic_vector(15 downto 0);
+      LVL2_RND_NUMBER_OUT        : out std_logic_vector(7 downto 0);
+      CTS_STASUS_0UT_0           : out std_logic_vector(31 downto 0);
+      CTS_STASUS_0UT_1           : out std_logic_vector(31 downto 0);
+      CTS_STASUS_0UT_2           : out std_logic_vector(31 downto 0);
+      CTS_CTRL_IN_0              : in  std_logic_vector(31 downto 0);
+      CTS_CTRL_IN_1              : in  std_logic_vector(31 downto 0));
+  end component;
+
+  component tdc_interfacev2
+    generic (
+      ENABLE_DMA          : natural;
+      NUMBER_OFF_ADD_DATA : natural);
+    port (
+      CLK                    : in  std_logic;
+      TDC_CLK                : in  std_logic;
+      RESET                  : in  std_logic;
+      TDC_DATA_IN            : in  std_logic_vector (31 downto 0);
+      START_TDC_READOUT      : in  std_logic;
+      A_TDC_READY            : in  std_logic;
+      B_TDC_READY            : in  std_logic;
+      C_TDC_READY            : in  std_logic;
+      D_TDC_READY            : in  std_logic;
+      A_TDC_ERROR            : in  std_logic;
+      B_TDC_ERROR            : in  std_logic;
+      C_TDC_ERROR            : in  std_logic;
+      D_TDC_ERROR            : in  std_logic;
+      SEND_TDC_TOKEN         : out std_logic;
+      RECEIVED_TDC_TOKEN     : in  std_logic;
+      GET_TDC_DATA           : out std_logic;
+      LVL2_READOUT_COMPLETED : out std_logic;
+      LVL1_TAG               : in  std_logic_vector(15 downto 0);
+      LVL1_RND_CODE          : in  std_logic_vector(7 downto 0);
+      LVL1_CODE              : in  std_logic_vector(3 downto 0);
+      LVL2_TAG               : in  std_logic_vector(7 downto 0);
+      HOW_MANY_ADD_DATA      : in  std_logic_vector(7 downto 0);
+      ADDITIONAL_DATA        : in  std_logic_vector(NUMBER_OFF_ADD_DATA*32-1 downto 0);
+      LVL2_TRIGGER           : in  std_logic;
+      TDC_DATA_OUT           : out std_logic_vector (31 downto 0);
+      TDC_DATA_VALID         : out std_logic;
+      ETRAX_IS_READY_TO_READ : in  std_logic;
+      ETRAX_IS_BUSY          : in  std_logic;
+      LVL1_BUSY              : out std_logic;
+      LVL2_BUSY              : out std_logic;
+      TDC_REGISTER_00        : out std_logic_vector(31 downto 0);
+      TDC_REGISTER_01        : out std_logic_vector(31 downto 0);
+      TDC_REGISTER_02        : out std_logic_vector(31 downto 0);
+      TDC_REGISTER_03        : out std_logic_vector(31 downto 0);
+      TDC_REGISTER_04        : out std_logic_vector(31 downto 0);
+      TDC_REGISTER_05        : in  std_logic_vector(31 downto 0);
+      BUNCH_RESET            : out std_logic;
+      EVENT_RESET            : out std_logic;
+      DELAY_TRIGGER          : in  std_logic_vector(7 downto 0);
+      DELAY_TOKEN            : in  std_logic_vector(7 downto 0);
+      TDC_START              : out std_logic;
+      TRIGGER_WITH_GEN_EN    : in  std_logic;
+      TRIGGER_WITH_GEN       : in  std_logic;
+      TRB_ID                 : in  std_logic_vector(31 downto 0);
+      LVL1_FINISHED          : out std_logic;
+      LVL2_FINISHED          : out std_logic;
+      TRBNET_HEADER_BUILD    : in  std_logic
+      );
+  end component;
+  
+
+ component trb_net_onewire is
+    generic(
+      USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
+      CLK_PERIOD : integer := 10  --clk period in ns
+      );
+    port(
+      CLK      : in std_logic;
+      RESET    : in std_logic;
+      --connection to 1-wire interface
+      ONEWIRE  : inout std_logic;
+      --connection to id ram, according to memory map in TrbNetRegIO
+      DATA_OUT : out std_logic_vector(15 downto 0);
+      ADDR_OUT : out std_logic_vector(2 downto 0);
+      WRITE_OUT: out std_logic;
+      TEMP_OUT : out std_logic_vector(11 downto 0);
+      STAT     : out std_logic_vector(31 downto 0)
+      );
+  end component;
   
   component vulom_interface
     generic (
@@ -490,70 +473,15 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       LVL1_TRIGGER_CODE   : out std_logic_vector(3 downto 0);
       LVL1_TRIGGER_TAG    : out std_logic_vector(7 downto 0)
       );
-  end component;
-  
-  component tdc_interface
-    generic (
-      ENABLE_DMA : positive;
-      NUMBER_OFF_ADD_DATA : positive
-      );
-    port (
-      CLK                      : in  std_logic;
-      TDC_CLK                  : in  std_logic;
-      RESET                    : in  std_logic;
-      TDC_DATA_IN              : in  std_logic_vector (31 downto 0);
-      START_TDC_READOUT        : in  std_logic;
-      A_TDC_READY              : in  std_logic;
-      B_TDC_READY              : in  std_logic;
-      C_TDC_READY              : in  std_logic;
-      D_TDC_READY              : in  std_logic;
-      A_TDC_ERROR              : in  std_logic;
-      B_TDC_ERROR              : in  std_logic;
-      C_TDC_ERROR              : in  std_logic;
-      D_TDC_ERROR              : in  std_logic;
-      A_TDC_POWERUP            : out std_logic;   
-      B_TDC_POWERUP            : out std_logic;
-      C_TDC_POWERUP            : out std_logic;
-      D_TDC_POWERUP            : out std_logic;
-      SEND_TDC_TOKEN           : out std_logic;
-      RECEIVED_TDC_TOKEN       : in  std_logic;
-      GET_TDC_DATA             : out std_logic;
-      LVL2_READOUT_COMPLETED    : out std_logic;
-      LVL1_TAG                 : in  std_logic_vector(7 downto 0);
-      LVL1_CODE                : in  std_logic_vector(3 downto 0);
-      LVL2_TAG                 : in  std_logic_vector(7 downto 0);
-      HOW_MANY_ADD_DATA        : in  std_logic_vector(7 downto 0);
-      ADDITIONAL_DATA          : in std_logic_vector(NUMBER_OFF_ADD_DATA*32-1 downto 0);
-      LVL2_TRIGGER             : in  std_logic;--_vector(1 downto 0);
-      TDC_DATA_OUT             : out std_logic_vector(31 downto 0);
-      TDC_DATA_VALID           : out std_logic;
-      ETRAX_IS_READY_TO_READ   : in  std_logic;
-      ETRAX_IS_BUSY            : in  std_logic;
-      LVL1_BUSY                : out std_logic;
-      LVL2_BUSY                : out std_logic;
-      TDC_REGISTER_00          : out std_logic_vector(31 downto 0);
-      TDC_REGISTER_01          : out std_logic_vector(31 downto 0);
-      TDC_REGISTER_02          : out std_logic_vector(31 downto 0);
-      TDC_REGISTER_03          : out std_logic_vector(31 downto 0);
-      TDC_REGISTER_04          : out std_logic_vector(31 downto 0);
-      TDC_REGISTER_05          : in  std_logic_vector(31 downto 0);
-      BUNCH_RESET              : out std_logic;
-      EVENT_RESET              : out std_logic;
-      DELAY_TRIGGER            : in  std_logic_vector(7 downto 0);
-      TDC_START                : out std_logic;
-      TRIGGER_WITHOUT_HADES    : in  std_logic;
-      TRIGGER_WITH_GEN_EN      : in std_logic;
-      TRIGGER_WITH_GEN         : in std_logic;
-      TRB_ID                   : in std_logic_vector(31 downto 0)
-      );
-  end component;
+  end component;  
   
   component etrax_interfacev2
     generic (
-      ENABLE_DMA : positive;
-      RW_SYSTEM : positive;
-      RW_REGISTERS_NUMBER : positive;
-      R_REGISTERS_NUMBER : positive
+      ENABLE_DMA : natural;
+      RW_SYSTEM : natural;
+      RW_REGISTERS_NUMBER : natural;
+      R_REGISTERS_NUMBER : natural;
+      TRBNET_ENABLE : natural
       );
     port (
       CLK                     : in    std_logic;
@@ -580,41 +508,11 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       EXTERNAL_MODE           : out   std_logic_vector(15 downto 0);
       RW_REGISTER             : out   std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
       R_REGISTER              : in    std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
-      LVL2_VALID              : in    std_logic
+      LVL2_VALID              : in    std_logic;
+      TRB_LVL2_BUSY           : in    std_logic
       );
     end component;
-  
-  component trb_net16_med_tlk
-    port (
-      RESET              : in  std_logic;
-      CLK                : in  std_logic;
-      TLK_CLK            : in  std_logic;
-      TLK_ENABLE         : out std_logic;
-      TLK_LCKREFN        : out std_logic;
-      TLK_LOOPEN         : out std_logic;
-      TLK_PRBSEN         : out std_logic;
-      TLK_RXD            : in  std_logic_vector(15 downto 0);
-      TLK_RX_CLK         : in  std_logic;
-      TLK_RX_DV          : in  std_logic;
-      TLK_RX_ER          : in  std_logic;
-      TLK_TXD            : out std_logic_vector(15 downto 0);
-      TLK_TX_EN          : out std_logic;
-      TLK_TX_ER          : out std_logic;
-      SFP_LOS            : in  std_logic;
-      SFP_TX_DIS         : out std_logic;
-      MED_DATAREADY_IN   : in  std_logic;
-      MED_READ_IN        : in  std_logic;
-      MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_DATAREADY_OUT  : out std_logic;
-      MED_READ_OUT       : out std_logic;
-      MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      STAT               : out std_logic_vector (63 downto 0);
-      STAT_MONITOR       : out std_logic_vector ( 100 downto 0);
-      STAT_OP            : out std_logic_vector (15 downto 0);
-      CTRL_OP            : in  std_logic_vector (15 downto 0));
-  end component;
+
   
   component dsp_interface
     port (
@@ -786,12 +684,12 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
     port (
       CLKIN_N_IN        : in  std_logic;
       CLKIN_P_IN        : in  std_logic;
-      RST_IN          : in  std_logic;
-      CLKDV_OUT       : out std_logic;
+      RST_IN            : in  std_logic;
+      CLKDV_OUT         : out std_logic;
       CLKIN_IBUFGDS_OUT : out std_logic;
-      CLK0_OUT        : out std_logic;
-      CLK2X_OUT       : out std_logic;
-      LOCKED_OUT      : out std_logic);
+      CLK0_OUT          : out std_logic;
+      CLK2X_OUT         : out std_logic;
+      LOCKED_OUT        : out std_logic);
   end component;
 
   component media_interface
@@ -830,6 +728,229 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       SFP_OUT_P          : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0)
       );
   end component;
+-------------------------------------------------------------------------------
+-- components for trbnet - cts
+-------------------------------------------------------------------------------
+   component trb_net16_endpoint_hades_cts
+     generic (
+       USE_CHANNEL               : channel_config_t;
+       IBUF_DEPTH                : channel_config_t;
+       FIFO_TO_INT_DEPTH         : channel_config_t;
+       FIFO_TO_APL_DEPTH         : channel_config_t;
+       INIT_CAN_SEND_DATA        : channel_config_t;
+       REPLY_CAN_SEND_DATA       : channel_config_t;
+       REPLY_CAN_RECEIVE_DATA    : channel_config_t;
+       USE_CHECKSUM              : channel_config_t;
+       APL_WRITE_ALL_WORDS       : channel_config_t;
+       BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
+       REGIO_NUM_STAT_REGS       : integer range 0 to 6;
+       REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
+       REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
+       REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
+       REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
+       REGIO_USE_DAT_PORT        : integer range 0 to 1;
+       REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
+       REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
+       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
+       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
+       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
+       REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
+       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
+       REGIO_USE_1WIRE_INTERFACE : integer;
+       CLOCK_FREQUENCY           : integer range 1 to 200);
+     port (
+       CLK                       : in    std_logic;
+       RESET                     : in    std_logic;
+       CLK_EN                    : in    std_logic;
+       MED_DATAREADY_OUT         : out   std_logic;
+       MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       MED_READ_IN               : in    std_logic;
+       MED_DATAREADY_IN          : in    std_logic;
+       MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       MED_READ_OUT              : out   std_logic;
+       MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
+       MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
+       TRG_SEND_IN               : in    std_logic;
+       TRG_TYPE_IN               : in    std_logic_vector (3 downto 0);
+       TRG_NUMBER_IN             : in    std_logic_vector (15 downto 0);
+       TRG_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
+       TRG_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
+       TRG_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
+       TRG_BUSY_OUT              : out   std_logic;
+       IPU_SEND_IN               : in    std_logic;
+       IPU_TYPE_IN               : in    std_logic_vector (3 downto 0);
+       IPU_NUMBER_IN             : in    std_logic_vector (15 downto 0);
+       IPU_INFORMATION_IN        : in    std_logic_vector (7 downto 0);
+       IPU_RND_CODE_IN           : in    std_logic_vector (7 downto 0);
+       IPU_DATA_OUT              : out   std_logic_vector (31 downto 0);
+       IPU_DATAREADY_OUT         : out   std_logic;
+       IPU_READ_IN               : in    std_logic;
+       IPU_STATUS_BITS_OUT       : out   std_logic_vector (31 downto 0);
+       IPU_BUSY_OUT              : out   std_logic;
+       REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+       REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+       REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+       REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+       REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
+       REGIO_READ_ENABLE_OUT     : out   std_logic;
+       REGIO_WRITE_ENABLE_OUT    : out   std_logic;
+       REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
+       REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
+       REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
+       REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
+       REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
+       REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
+       REGIO_TIMEOUT_OUT         : out   std_logic;
+       REGIO_ONEWIRE_INOUT       : inout std_logic;
+       REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
+       REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
+       TRIGGER_MONITOR_IN        : in    std_logic;
+       GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
+       LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
+       TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
+       TIMER_US_TICK_OUT         : out   std_logic;
+       STAT_DEBUG_1              : out   std_logic_vector(31 downto 0);
+       STAT_DEBUG_2              : out   std_logic_vector(31 downto 0));
+   end component;
+
+--   -----------------------------------------------------------------------------
+--   -- components for trbnet - hades end point
+--   -----------------------------------------------------------------------------
+
+   component trb_net16_endpoint_hades_full
+     generic (
+       USE_CHANNEL               : channel_config_t;
+       IBUF_DEPTH                : channel_config_t;
+       FIFO_TO_INT_DEPTH         : channel_config_t;
+       FIFO_TO_APL_DEPTH         : channel_config_t;
+       IBUF_SECURE_MODE          : channel_config_t;
+       API_SECURE_MODE_TO_APL    : channel_config_t;
+       API_SECURE_MODE_TO_INT    : channel_config_t;
+       OBUF_DATA_COUNT_WIDTH     : integer range 0 to 7;
+       INIT_CAN_SEND_DATA        : channel_config_t;
+       REPLY_CAN_SEND_DATA       : channel_config_t;
+       REPLY_CAN_RECEIVE_DATA    : channel_config_t;
+       USE_CHECKSUM              : channel_config_t;
+       APL_WRITE_ALL_WORDS       : channel_config_t;
+       BROADCAST_BITMASK         : std_logic_vector(7 downto 0);
+       REGIO_NUM_STAT_REGS       : integer range 0 to 6;
+       REGIO_NUM_CTRL_REGS       : integer range 0 to 6;
+       REGIO_INIT_CTRL_REGS      : std_logic_vector(2**(3)*32-1 downto 0);
+       REGIO_USED_CTRL_REGS      : std_logic_vector(2**(3)-1 downto 0);
+       REGIO_USED_CTRL_BITMASK   : std_logic_vector(2**(3)*32-1 downto 0);
+       REGIO_USE_DAT_PORT        : integer range 0 to 1;
+       REGIO_INIT_ADDRESS        : std_logic_vector(15 downto 0);
+       REGIO_INIT_UNIQUE_ID      : std_logic_vector(63 downto 0);
+       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0);
+       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0);
+       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0);
+       REGIO_COMPILE_VERSION     : std_logic_vector(15 downto 0);
+       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0);
+       REGIO_USE_1WIRE_INTERFACE : integer;
+       CLOCK_FREQUENCY           : integer range 1 to 200);
+     port (
+       CLK                       : in    std_logic;
+       RESET                     : in    std_logic;
+       CLK_EN                    : in    std_logic;
+       MED_DATAREADY_OUT         : out   std_logic;
+       MED_DATA_OUT              : out   std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_OUT        : out   std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       MED_READ_IN               : in    std_logic;
+       MED_DATAREADY_IN          : in    std_logic;
+       MED_DATA_IN               : in    std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_IN         : in    std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       MED_READ_OUT              : out   std_logic;
+       MED_STAT_OP_IN            : in    std_logic_vector(15 downto 0);
+       MED_CTRL_OP_OUT           : out   std_logic_vector(15 downto 0);
+       LVL1_TRG_TYPE_OUT         : out   std_logic_vector(3 downto 0);
+       LVL1_TRG_RECEIVED_OUT     : out   std_logic;
+       LVL1_TRG_NUMBER_OUT       : out   std_logic_vector(15 downto 0);
+       LVL1_TRG_CODE_OUT         : out   std_logic_vector(7 downto 0);
+       LVL1_TRG_INFORMATION_OUT  : out   std_logic_vector(7 downto 0);
+       LVL1_ERROR_PATTERN_IN     : in    std_logic_vector(31 downto 0)                            := x"00000000";
+       LVL1_TRG_RELEASE_IN       : in    std_logic                                                := '0';
+       IPU_NUMBER_OUT            : out   std_logic_vector (15 downto 0);
+       IPU_INFORMATION_OUT       : out   std_logic_vector (7 downto 0);
+       IPU_START_READOUT_OUT     : out   std_logic;
+       IPU_DATA_IN               : in    std_logic_vector (31 downto 0);
+       IPU_DATAREADY_IN          : in    std_logic;
+       IPU_READOUT_FINISHED_IN   : in    std_logic;
+       IPU_READ_OUT              : out   std_logic;
+       IPU_LENGTH_IN             : in    std_logic_vector (15 downto 0);
+       IPU_ERROR_PATTERN_IN      : in    std_logic_vector (31 downto 0);
+       REGIO_COMMON_STAT_REG_IN  : in    std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+       REGIO_COMMON_CTRL_REG_OUT : out   std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+       REGIO_REGISTERS_IN        : in    std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+       REGIO_REGISTERS_OUT       : out   std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+       REGIO_ADDR_OUT            : out   std_logic_vector(16-1 downto 0);
+       REGIO_READ_ENABLE_OUT     : out   std_logic;
+       REGIO_WRITE_ENABLE_OUT    : out   std_logic;
+       REGIO_DATA_OUT            : out   std_logic_vector(32-1 downto 0);
+       REGIO_DATA_IN             : in    std_logic_vector(32-1 downto 0)                          := (others => '0');
+       REGIO_DATAREADY_IN        : in    std_logic                                                := '0';
+       REGIO_NO_MORE_DATA_IN     : in    std_logic                                                := '0';
+       REGIO_WRITE_ACK_IN        : in    std_logic                                                := '0';
+       REGIO_UNKNOWN_ADDR_IN     : in    std_logic                                                := '0';
+       REGIO_TIMEOUT_OUT         : out   std_logic;
+       REGIO_IDRAM_DATA_IN       : in    std_logic_vector(15 downto 0)                            := (others => '0');
+       REGIO_IDRAM_DATA_OUT      : out   std_logic_vector(15 downto 0);
+       REGIO_IDRAM_ADDR_IN       : in    std_logic_vector(2 downto 0)                             := "000";
+       REGIO_IDRAM_WR_IN         : in    std_logic                                                := '0';
+       REGIO_ONEWIRE_INOUT       : inout std_logic;
+       REGIO_ONEWIRE_MONITOR_IN  : in    std_logic;
+       REGIO_ONEWIRE_MONITOR_OUT : out   std_logic;
+       TRIGGER_MONITOR_IN        : in    std_logic;
+       GLOBAL_TIME_OUT           : out   std_logic_vector(31 downto 0);
+       LOCAL_TIME_OUT            : out   std_logic_vector(7 downto 0);
+       TIME_SINCE_LAST_TRG_OUT   : out   std_logic_vector(31 downto 0);
+       TIMER_US_TICK_OUT         : out   std_logic;
+       STAT_DEBUG_IPU            : out   std_logic_vector (31 downto 0);
+       STAT_DEBUG_1              : out   std_logic_vector (31 downto 0);
+       STAT_DEBUG_2              : out   std_logic_vector (31 downto 0);
+       MED_STAT_OP               : out   std_logic_vector (15 downto 0);
+       CTRL_MPLEX                : in    std_logic_vector (31 downto 0);
+       IOBUF_CTRL_GEN            : in    std_logic_vector (4*32-1 downto 0);
+       STAT_ONEWIRE              : out   std_logic_vector (31 downto 0);
+       STAT_ADDR_DEBUG           : out   std_logic_vector (15 downto 0));
+   end component;
+
+--   -----------------------------------------------------------------------------
+--   -- components from trbnet - media ineterface
+--   -----------------------------------------------------------------------------
+    
+   component trb_net16_med_tlk
+     port (
+       RESET              : in  std_logic;
+       CLK                : in  std_logic;
+       TLK_CLK            : in  std_logic;
+       TLK_ENABLE         : out std_logic;
+       TLK_LCKREFN        : out std_logic;
+       TLK_LOOPEN         : out std_logic;
+       TLK_PRBSEN         : out std_logic;
+       TLK_RXD            : in  std_logic_vector(15 downto 0);
+       TLK_RX_CLK         : in  std_logic;
+       TLK_RX_DV          : in  std_logic;
+       TLK_RX_ER          : in  std_logic;
+       TLK_TXD            : out std_logic_vector(15 downto 0);
+       TLK_TX_EN          : out std_logic;
+       TLK_TX_ER          : out std_logic;
+       SFP_LOS            : in  std_logic;
+       SFP_TX_DIS         : out std_logic;
+       MED_DATAREADY_IN   : in  std_logic;
+       MED_READ_IN        : in  std_logic;
+       MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       MED_DATAREADY_OUT  : out std_logic;
+       MED_READ_OUT       : out std_logic;
+       MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+       MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+       STAT               : out std_logic_vector (63 downto 0);
+       STAT_MONITOR       : out std_logic_vector ( 100 downto 0);
+       STAT_OP            : out std_logic_vector (15 downto 0);
+       CTRL_OP            : in  std_logic_vector (15 downto 0));
+   end component;
   
   -----------------------------------------------------------------------------
   -- SFP optical power and temperature --component !!!
@@ -845,80 +966,76 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
 -------------------------------------------------------------------------------
 -- SIGNALS
 -------------------------------------------------------------------------------
-  constant  VERSION_NUMBER_TIME  : integer := 4;--VERSION_NUMBER_TIME;  --interface
-  constant HOW_MANY_CHANNELS : integer := 1;
+--  constant VaaaaaaaaaERSION_NUMBER_TIME : integer := 1245150983;  --interface
+  constant HOW_MANY_CHANNELS   : integer := 1;
   
   --clk
-  signal clk_lvds       : std_logic;
-  signal addon_clk : std_logic;
-  signal clk :std_logic;
-  signal clk50 : std_logic;
-  signal clk200 : std_logic;
-  signal locked_out : std_logic;
-  attribute period: string;
-  attribute period of clk : signal is "10 ns";
+  signal                           clk_lvds   : std_logic;
+  signal                           addon_clk  : std_logic;
+  signal                           clk        : std_logic;
+  signal                           clk50      : std_logic;
+  signal                           clk200     : std_logic;
+  signal                           locked_out : std_logic;
+  attribute period                            : string;
+  attribute period of clk                     : signal is "10 ns";
   
   --reset
   signal global_reset_counter : std_logic_vector(3 downto 0) := x"0";
   signal reset_i              : std_logic :='0';
 
   --TDC
-  signal tdc_clk                  : std_logic;
-  signal tdc_clk_i                : std_logic;
-  signal tdc_data_in_i            : std_logic_vector(31 downto 0);
-  signal a_data_ready_i           : std_logic;
-  signal b_data_ready_i           : std_logic;
-  signal c_data_ready_i           : std_logic;
-  signal d_data_ready_i           : std_logic;
-  signal a_trigg                  : std_logic;
-  signal b_trigg                  : std_logic;
-  signal c_trigg                  : std_logic;
-  signal d_trigg                  : std_logic;
-  signal reference_signal         : std_logic;
-  signal tdc_readout_completed_i  : std_logic;
-  signal tdc_data_out_i           : std_logic_vector(31 downto 0);
-  signal tdc_data_valid_i         : std_logic;
-  signal lvl2_readout_completed_i : std_logic;
-  signal tdc_register_00_i        : std_logic_vector(31 downto 0);
-  signal tdc_register_01_i        : std_logic_vector(31 downto 0);
-  signal tdc_register_02_i        : std_logic_vector(31 downto 0);
-  signal tdc_register_03_i        : std_logic_vector(31 downto 0);
-  signal tdc_register_04_i        : std_logic_vector(31 downto 0);
-  signal tdc_register_05_i        : std_logic_vector(31 downto 0);
-  signal bunch_reset_i            : std_logic;
-  signal event_reset_i            : std_logic;
-  signal trigger_to_tdc_i         : std_logic;
-  signal token_out_i              : std_logic;
-  signal token_out_long_a         : std_logic;
-  signal token_out_long_b         : std_logic;
-  signal fast_ref_trigger         : std_logic;
-  signal fast_ref_trigger_synch   : std_logic;
-  signal fast_ref_trigger_pulse   : std_logic;
-  signal fast_ref_trigger_pulse_synch   : std_logic;
-  signal token_in_i               : std_logic;
-  signal not_hades_trigger        : std_logic;
-  signal trigger_miss_match       : std_logic;
-  signal additional_data_i          : std_logic_vector(NUMBER_OFF_ADD_DATA*32-1 downto 0);
-  signal NUMBER_OFF_ADD_DATA_RANGE : integer := 0;
-  signal self_trigg : std_logic;
-
-  --count rate
-  signal one_second_cntr : std_logic_vector(27 downto 0);
-  signal event_end_pulse : std_logic;
-  signal one_second_reset : std_logic;
-  signal event_rate_cntr : std_logic_vector(19 downto 0);
-  signal saved_event_rate : std_logic_vector(19 downto 0);
+  signal tdc_clk                      : std_logic;
+  signal tdc_clk_i                    : std_logic;
+  signal tdc_data_in_i                : std_logic_vector(31 downto 0);
+  signal a_data_ready_i               : std_logic;
+  signal b_data_ready_i               : std_logic;
+  signal c_data_ready_i               : std_logic;
+  signal d_data_ready_i               : std_logic;
+  signal a_trigg                      : std_logic;
+  signal b_trigg                      : std_logic;
+  signal c_trigg                      : std_logic;
+  signal d_trigg                      : std_logic;
+  signal reference_signal             : std_logic;
+  signal tdc_readout_completed_i      : std_logic;
+  signal tdc_data_out_i               : std_logic_vector(31 downto 0);
+  signal tdc_data_valid_i             : std_logic;
+  signal lvl2_readout_completed_i     : std_logic;
+  signal tdc_register_00_i            : std_logic_vector(31 downto 0);
+  signal tdc_register_01_i            : std_logic_vector(31 downto 0);
+  signal tdc_register_02_i            : std_logic_vector(31 downto 0);
+  signal tdc_register_03_i            : std_logic_vector(31 downto 0);
+  signal tdc_register_04_i            : std_logic_vector(31 downto 0);
+  signal tdc_register_05_i            : std_logic_vector(31 downto 0);
+  signal bunch_reset_i                : std_logic;
+  signal event_reset_i                : std_logic;
+  signal trigger_to_tdc_i             : std_logic;
+  signal token_out_i                  : std_logic;
+  signal token_out_long_a             : std_logic;
+  signal token_out_long_b             : std_logic;
+  signal fast_ref_trigger             : std_logic;
+  signal fast_ref_trigger_synch       : std_logic;
+  signal fast_ref_trigger_pulse       : std_logic;
+  signal fast_ref_trigger_pulse_synch : std_logic;
+  signal token_in_i                   : std_logic;
+  signal not_hades_trigger            : std_logic;
+  signal trigger_miss_match           : std_logic;
+  signal additional_data_i            : std_logic_vector(NUMBER_OFF_ADD_DATA*32-1 downto 0);
+  signal NUMBER_OFF_ADD_DATA_RANGE    : integer := 0;
+  signal self_trigg                   : std_logic;
+  signal lvl1_finished_i              : std_logic;
+  signal lvl2_finished_i              : std_logic;
+  
   
   --common signals for triggers 
   signal lvl1_busy_i         : std_logic;
   signal lvl2_busy_i         : std_logic;
   signal lvl1_trigger_code_i : std_logic_vector(3 downto 0);
-  signal lvl1_trigger_tag_i  : std_logic_vector(7 downto 0);
+  signal lvl1_trigger_tag_i  : std_logic_vector(15 downto 0);
   signal lvl2_trigger_i      : std_logic;
   signal lvl2_trigger_synch  : std_logic;
   signal lvl1_trigger_i      : std_logic;
   signal lvl2_trigger_code_i : std_logic_vector(3 downto 0) := x"0";
-  signal lvl2_trigger_tag_i  : std_logic_vector(7 downto 0) := x"00";
+  signal lvl2_trigger_tag_i  : std_logic_vector(15 downto 0) := x"0000";
   
   --etrax 
   signal etrax_bus_busy_i         : std_logic;  --should go to busy logic !? 
@@ -938,23 +1055,29 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal fpga_register_0d_i       : std_logic_vector(31 downto 0);
   signal fpga_register_0e_i       : std_logic_vector(31 downto 0);
   signal fpga_register_0f_i       : std_logic_vector(31 downto 0);
-  signal r_register_i  : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
-  signal rw_register_i  : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
-  
+--  signal r_register_i             : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+--  signal rw_register_i            : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+  type r_register_array is array(0 to R_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+  signal r_register_i : r_register_array;
+  type rw_register_array is array(0 to RW_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+  signal rw_register_i : rw_register_array;
+  signal fs_pc_i : std_logic_vector(17 downto 0);
+  signal fs_pb_i : std_logic_vector(16 downto 0);
+  signal fs_pb_17i : std_logic;
   -- tlk
   signal tlk_rx_clk_r      : std_logic_vector(3 downto 0);
   signal tlk_clk_r         : std_logic_vector(0 downto 0);
   signal tlk_register_00_i : std_logic_vector(31 downto 0);
   signal tlk_register_01_i : std_logic_vector(31 downto 0);
-  signal cv_i : std_logic_vector(7 downto 0);
-  signal rx_k_i : std_logic_vector(7 downto 0);
-  signal tx_k_i : std_logic_vector(7 downto 0);
-  signal media_status_i : std_logic_vector(15 downto 0);
-  signal media_control_i : std_logic_vector(15 downto 0);
-  signal link_debug_i : std_logic_vector(31 downto 0);
-  signal sfp_los_vect : std_logic_vector(0 downto 0);
-  signal tlk_rxd_i : std_logic_vector(63 downto 0);
-  signal tlk_txd_i : std_logic_vector(63 downto 0);
+  signal cv_i              : std_logic_vector(7 downto 0);
+  signal rx_k_i            : std_logic_vector(7 downto 0);
+  signal tx_k_i            : std_logic_vector(7 downto 0);
+  signal media_status_i    : std_logic_vector(15 downto 0);
+  signal media_control_i   : std_logic_vector(15 downto 0);
+  signal link_debug_i      : std_logic_vector(31 downto 0);
+  signal sfp_los_vect      : std_logic_vector(0 downto 0);
+  signal tlk_rxd_i         : std_logic_vector(63 downto 0);
+  signal tlk_txd_i         : std_logic_vector(63 downto 0);
 
   
   --rw external interaface
@@ -1004,202 +1127,173 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal lvl2_ctu_status_i : std_logic_vector(31 downto 0);
   
   --dtu
-  signal dtu_debug_00_i : std_logic_vector(31 downto 0);
-  signal busy_or_error : std_logic;
-  signal safe_mode_only_one_ref : std_logic;
+  signal dtu_debug_00_i            : std_logic_vector(31 downto 0);
+  signal busy_or_error             : std_logic;
   signal optical_tdc_trigger_reg_1 : std_logic;
   signal optical_tdc_trigger_reg_2 : std_logic;
   signal optical_tdc_trigger_reg_3 : std_logic;
-  signal optical_tdc_trigger : std_logic;
+  signal optical_tdc_trigger       : std_logic;
   
   --other
-  signal check_pulse      : std_logic;
-  signal check_counter    : std_logic_vector(16 downto 0);
-  signal lvds_add_on_data : std_logic_vector(31 downto 0);
+  signal check_pulse        : std_logic;
+  signal check_counter      : std_logic_vector(16 downto 0);
+  signal lvds_add_on_data   : std_logic_vector(31 downto 0);
+  signal ado_lv_out_i   : std_logic_vector(4 downto 0);
+  
   signal self_trigg_counter : std_logic_vector(7 downto 0);
- --api
-  signal med_dataready_out_i     : std_logic;
+  signal r_register_vector             : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+  signal rw_register_vector            : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+  type temp_sens_array is array (3 downto 0) of std_logic_vector(11 downto 0);
+  signal temp_sens_i : temp_sens_array;
+  type temp_sens_status_array is array (3 downto 0) of std_logic_vector(31 downto 0);
+  signal temp_sens_status_i : temp_sens_status_array;
+  
+ -- media interface
+  signal med_dataready_out_i     : std_logic_vector(0 downto 0);
   signal med_data_OUT_i          : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal MED_PACKET_NUM_OUT_i    : std_logic_vector (HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
-  signal MED_READ_IN_i           : std_logic_vector(0 downto 0);
-  signal MED_DATAREADY_IN_i      : std_logic_vector(0 downto 0);
-  signal MED_DATA_IN_i           : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal med_error_out_i         : std_logic_vector(2 downto 0);
-  signal MED_READ_OUT_i          : std_logic;
-  signal MED_ERROR_IN_i          : std_logic_vector (2 downto 0);
-  signal MED_STAT_OP_i           : std_logic_vector (15 downto 0);
-  signal MED_CTRL_OP_i           : std_logic_vector (15 downto 0);
-  signal APL_DATA_IN_i           : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal APL_PACKET_NUM_IN_i     : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-  signal APL_DATAREADY_IN_i      : std_logic;
-  signal APL_READ_OUT_i          : std_logic;
-  signal APL_SHORT_TRANSFER_IN_i : std_logic;
-  signal APL_DTYPE_IN_i          : std_logic_vector (3 downto 0);
-  signal APL_ERROR_PATTERN_IN_i  : std_logic_vector (31 downto 0);
-  signal APL_SEND_IN_i           : std_logic;
-  signal APL_TARGET_ADDRESS_IN_i : std_logic_vector (15 downto 0);
-  signal APL_DATA_OUT_i          : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-  signal APL_PACKET_NUM_OUT_i    : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-  signal APL_TYP_OUT_i           : std_logic_vector (2 downto 0);
-  signal APL_DATAREADY_OUT_i     : std_logic;
-  signal APL_READ_IN_i           : std_logic;
-
-  signal apl_run_out_i              : std_logic;
-  signal apl_seqnr_out_i            : std_logic_vector(7 downto 0);
-  signal stat_i                     : std_logic_vector(63 downto 0);
-  signal stat_op_i                  : std_logic_vector(15 downto 0);
-  signal ctrl_op_i                  : std_logic_vector(15 downto 0);
-  signal STAT_GEN_i                 : std_logic_vector (31 downto 0);
-  signal STAT_LOCKED_i              : std_logic_vector (31 downto 0);
-  signal STAT_INIT_BUFFER_i         : std_logic_vector (31 downto 0);
-  signal STAT_REPLY_BUFFER_i        : std_logic_vector (31 downto 0);
-  signal STAT_api_control_signals_i : std_logic_vector(31 downto 0);
-  signal STAT_MPLEX_i               : std_logic_vector(31 downto 0);
-  signal CTRL_GEN_i                 : std_logic_vector (31 downto 0);
-  signal CTRL_LOCKED_i              : std_logic_vector (31 downto 0);
-  signal STAT_CTRL_INIT_BUFFER_i    : std_logic_vector (31 downto 0);
-  signal STAT_CTRL_REPLY_BUFFER_i   : std_logic_vector (31 downto 0);
-  signal MPLEX_CTRL_i               : std_logic_vector (31 downto 0);
-  signal API_STAT_FIFO_TO_INT_i     : std_logic_vector(31 downto 0);
-  signal API_STAT_FIFO_TO_APL_i     : std_logic_vector(31 downto 0);
+  signal med_packet_num_out_i    : std_logic_vector (HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+  signal med_read_in_i           : std_logic_vector(0 downto 0);
+  signal med_dataready_in_i      : std_logic_vector(0 downto 0);
+  signal med_data_in_i           : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+  signal med_read_out_i          : std_logic_vector(0 downto 0);
+  signal med_stat_op_in_i           : std_logic_vector (15 downto 0);
+  signal med_ctrl_op_out_i           : std_logic_vector (15 downto 0);
   signal med_packet_num_in_i        : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- 
-
-  --media
-  
-  
-  --trbnet
-  
---   signal clk_i                       : std_logic;
---   signal reset_i                     : std_logic;
---   signal clk_en_i                    : std_logic;
---   signal med_dataready_out_i         : std_logic;
---   signal med_data_out_i              : std_logic_vector (c_DATA_WIDTH-1 downto 0);
---   signal med_packet_num_out_i        : std_logic_vector (c_NUM_WIDTH-1 downto 0);
---   signal med_read_in_i               : std_logic;
---   signal med_dataready_in_i          : std_logic;
---   signal med_data_in_i               : std_logic_vector (c_DATA_WIDTH-1 downto 0);
---   signal med_packet_num_in_i         : std_logic_vector (c_NUM_WIDTH-1 downto 0);
---   signal med_read_out_i              : std_logic;
---   signal med_stat_op_in_i            : std_logic_vector(15 downto 0);
---   signal med_ctrl_op_out_i           : std_logic_vector(15 downto 0);
---   signal lvl1_trg_type_out_i         : std_logic_vector(3 downto 0);
---   signal lvl1_trg_received_out_i     : std_logic;
---   signal lvl1_trg_number_out_i       : std_logic_vector(15 downto 0);
---   signal lvl1_trg_code_out_i         : std_logic_vector(7 downto 0);
---   signal lvl1_trg_information_out_i  : std_logic_vector(7 downto 0);
---   signal lvl1_error_pattern_in_i     : std_logic_vector(31 downto 0)                            := x"00000000";
---   signal lvl1_trg_release_in_i       : std_logic                                                := '0';
---   signal ipu_number_out_i            : std_logic_vector (15 downto 0);
---   signal ipu_information_out_i       : std_logic_vector (7 downto 0);
---   signal ipu_start_readout_out_i     : std_logic;
---   signal ipu_data_in_i               : std_logic_vector (31 downto 0);
---   signal ipu_dataready_in_i          : std_logic;
---   signal ipu_readout_finished_in_i   : std_logic;
---   signal ipu_read_out_i              : std_logic;
---   signal ipu_length_in_i             : std_logic_vector (15 downto 0);
---   signal ipu_error_pattern_in_i      : std_logic_vector (31 downto 0);
---   signal regio_common_stat_reg_in_i  : std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
---   signal regio_common_ctrl_reg_out_i : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
---   signal regio_registers_in_i        : std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
---   signal regio_registers_out_i       : std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
---   signal regio_addr_out_i            : std_logic_vector(16-1 downto 0);
---   signal regio_read_enable_out_i     : std_logic;
---   signal regio_write_enable_out_i    : std_logic;
---   signal regio_data_out_i            : std_logic_vector(32-1 downto 0);
---   signal regio_data_in_i             : std_logic_vector(32-1 downto 0)                          := (others => '0');
---   signal regio_dataready_in_i        : std_logic                                                := '0';
---   signal regio_no_more_data_in_i     : std_logic                                                := '0';
---   signal regio_write_ack_in_i        : std_logic                                                := '0';
---   signal regio_unknown_addr_in_i     : std_logic                                                := '0';
---   signal regio_timeout_out_i         : std_logic;
---   signal regio_idram_data_in_i       : std_logic_vector(15 downto 0)                            := (others => '0');
---   signal regio_idram_data_out_i      : std_logic_vector(15 downto 0);
---   signal regio_idram_addr_in_i       : std_logic_vector(2 downto 0)                             := "000";
---   signal regio_idram_wr_in_i         : std_logic                                                := '0';
---   signal regio_onewire_inout_i       : std_logic;
---   signal regio_ext_reg_data_in_i     : std_logic_vector(31 downto 0)                            := (others => '0');
---   signal regio_ext_reg_data_out_i    : std_logic_vector(31 downto 0);
---   signal regio_ext_reg_write_in_i    : std_logic                                                := '0';
---   signal regio_ext_reg_addr_in_i     : std_logic_vector(7 downto 0)                             := (others => '0');
---   signal stat_debug_ipu_i            : std_logic_vector (31 downto 0);
---   signal stat_debug_1_i              : std_logic_vector (31 downto 0);
---   signal stat_debug_2_i              : std_logic_vector (31 downto 0);
---   signal med_stat_op_i               : std_logic_vector (15 downto 0);
---   signal ctrl_mplex_i                : std_logic_vector (31 downto 0);
---   signal iobuf_ctrl_gen_i            : std_logic_vector (4*32-1 downto 0);
---   signal stat_onewire_i              : std_logic_vector (31 downto 0);
---   signal stat_addr_debug_i           : std_logic_vector (15 downto 0);
   
-
+  --trbnet -cts
+  signal not_ipu_dataready_out_i : std_logic;
+  signal ipu_dataready_out_end_pulse : std_logic;
+      --lvl1
+   signal trg_send_in_i               : std_logic;
+   signal trg_type_in_i               : std_logic_vector (3 downto 0);
+   signal trg_number_in_i             : std_logic_vector (15 downto 0);
+   signal trg_information_in_i        : std_logic_vector (7 downto 0);
+   signal trg_status_bits_out_i       : std_logic_vector (31 downto 0);
+      --lvl2
+   signal trg_busy_out_i              : std_logic:='0';
+   signal ipu_send_in_i               : std_logic;
+   signal ipu_type_in_i               : std_logic_vector (3 downto 0);
+   signal ipu_number_in_i             : std_logic_vector (15 downto 0);
+   signal ipu_information_in_i        : std_logic_vector (7 downto 0);
+   signal ipu_data_out_i              : std_logic_vector (31 downto 0);
+   signal ipu_dataready_out_i         : std_logic;
+   signal ipu_read_in_i               : std_logic;
+   signal ipu_status_bits_out_i       : std_logic_vector (31 downto 0);
+   signal ipu_busy_out_i              : std_logic:='0';
+
+      --reg io
+   signal regio_common_stat_reg_in_i  : std_logic_vector(std_COMSTATREG*32-1 downto 0)           := (others => '0');
+   signal regio_common_ctrl_reg_out_i : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+--   constant REGIO_NUM_STAT_REGS : integer := R_REGISTERS_NUMBER;
+--   constant REGIO_NUM_CTRL_REGS : integer := RW_REGISTERS_NUMBER;
+   signal regio_registers_in_i        : std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+   signal regio_registers_out_i       : std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+   signal regio_addr_out_i            : std_logic_vector(16-1 downto 0);
+   signal regio_read_enable_out_i     : std_logic;
+   signal regio_write_enable_out_i    : std_logic;
+   signal regio_data_out_i            : std_logic_vector(32-1 downto 0);
+   signal regio_data_in_i             : std_logic_vector(32-1 downto 0)                          := (others => '0');
+   signal regio_dataready_in_i        : std_logic                                                := '0';
+   signal regio_no_more_data_in_i     : std_logic                                                := '0';
+   signal regio_write_ack_in_i        : std_logic                                                := '0';
+   signal regio_unknown_addr_in_i     : std_logic                                                := '0';
+   signal regio_timeout_out_i         : std_logic;
+   signal regio_onewire_inout_i       : std_logic;
+   signal regio_onewire_monitor_out_i : std_logic;
+   signal regio_onewire_monitor_in_i  : std_logic;
+   
+--trbnet endpoint
+   signal trigger_monitor_in_i        : std_logic;
+   signal global_time_out_i           : std_logic_vector(31 downto 0);
+   signal local_time_out_i            : std_logic_vector(7 downto 0);
+   signal time_since_last_trg_out_i   : std_logic_vector(31 downto 0);
+   signal timer_us_tick_out_i         : std_logic;
+   signal stat_debug_1_i              : std_logic_vector(31 downto 0);
+   signal stat_debug_2_i              : std_logic_vector(31 downto 0);
+   signal regio_idram_data_in_i       : std_logic_vector(15 downto 0)                            := (others => '0');
+   signal regio_idram_data_out_i      : std_logic_vector(15 downto 0);
+   signal regio_idram_addr_in_i       : std_logic_vector(2 downto 0)                             := "000";
+   signal regio_idram_wr_in_i         : std_logic                                                := '0';
+   signal stat_debug_ipu_i            : std_logic_vector (31 downto 0);
+   signal ipu_read_out_i              : std_logic                                                := '0';
+   signal ipu_dataready_in_i          : std_logic;
+   signal lvl2_trigger_i_pulse        : std_logic;
+   signal cntr_for_dummy_header       : std_logic_vector(1 downto 0) := "00";
+   signal ipu_data_in_i : std_logic_vector(31 downto 0);
   --vulom
-  signal vulom_event : std_logic_vector(31 downto 0);
-  signal vulom_event_valid : std_logic;
-  signal vulom_readout_start : std_logic;
-  signal vulom_readout_end : std_logic;
-  signal vulom_busy : std_logic;
-  signal vulom_lvl1_trigger_i : std_logic;
+  signal vulom_event               : std_logic_vector(31 downto 0);
+  signal vulom_event_valid         : std_logic;
+  signal vulom_readout_start       : std_logic;
+  signal vulom_readout_end         : std_logic;
+  signal vulom_busy                : std_logic;
+  signal vulom_lvl1_trigger_i      : std_logic;
   signal vulom_lvl1_trigger_code_i : std_logic_vector(3 downto 0);
-  signal vulom_lvl1_trigger_tag_i : std_logic_vector(7 downto 0);
-  signal ext_lvl1_trigger_i : std_logic:='0';
-  signal ext_tag : std_logic_vector(7 downto 0):=x"00";
-  signal ext_lvl1_trigger_pulse : std_logic;
-  
-  --opt ctu
-  signal opt_lvl1_busy_i : std_logic;
-  signal opt_lvl2_busy_i : std_logic;
-  signal not_lvl1_busy_opt : std_logic;
-  signal opt_ctu_debug_i : std_logic_vector(31 downto 0);
+  signal vulom_lvl1_trigger_tag_i  : std_logic_vector(15 downto 0);
+  signal ext_lvl1_trigger_i        : std_logic                    := '0';
+  signal ext_tag                   : std_logic_vector(7 downto 0) := x"00";
+  signal ext_lvl1_trigger_pulse    : std_logic;
+  signal lvl1_vulom_trigger        : std_logic;
+
+  --opt ctu 
+  signal opt_lvl1_busy_i       : std_logic;
+  signal opt_lvl2_busy_i       : std_logic;
+  signal not_lvl1_busy_opt     : std_logic;
+  signal opt_ctu_debug_i       : std_logic_vector(31 downto 0);
   signal opt_busy_lvl1_or_lvl2 : std_logic;
-  signal lvl2_opt_busy_pulse : std_logic;
-  signal not_lvl2_opt_busy : std_logic;
+  signal lvl2_opt_busy_pulse   : std_logic;
+  signal not_lvl2_opt_busy     : std_logic;
   
-  --spi
+  --spi  
   --a
   signal spi_sck_a : std_logic;
   signal spi_cs_a  : std_logic;
   signal spi_sdi_a : std_logic;
-  signal spi_sdo_a : std_logic;
+  signal spi_sdo_a : std_logic;  
   --b
   signal spi_sck_b : std_logic;
   signal spi_cs_b  : std_logic;
   signal spi_sdi_b : std_logic;
-  signal spi_sdo_b : std_logic;
+  signal spi_sdo_b : std_logic;  
   --c
   signal spi_sck_c : std_logic;
   signal spi_cs_c  : std_logic;
   signal spi_sdi_c : std_logic;
-  signal spi_sdo_c : std_logic;
+  signal spi_sdo_c : std_logic;  
   --d
   signal spi_sck_d : std_logic;
   signal spi_cs_d  : std_logic;
   signal spi_sdi_d : std_logic;
   signal spi_sdo_d : std_logic;
   
-  --test signals
-  signal test_a1        : std_logic;
-  signal test_a2        : std_logic;
-  signal test_b1        : std_logic;
-  signal test_b2        : std_logic;
-  signal test_c1        : std_logic;
-  signal test_c2        : std_logic;
-  signal test_d1        : std_logic;
-  signal test_d2        : std_logic;
-  signal test_counter_1 : std_logic_vector(31 downto 0);
-  signal test_counter_2 : std_logic_vector(31 downto 0);
+  --test signals  
+  signal test_a1                 : std_logic;
+  signal test_a2                 : std_logic;
+  signal test_b1                 : std_logic;
+  signal test_b2                 : std_logic;
+  signal test_c1                 : std_logic;
+  signal test_c2                 : std_logic;
+  signal test_d1                 : std_logic;
+  signal test_d2                 : std_logic;
+  signal test_counter_1          : std_logic_vector(31 downto 0);
+  signal test_counter_2          : std_logic_vector(31 downto 0);
   signal trigger_for_test_signal : std_logic;
-  signal ref_time_counter : std_logic_vector(7 downto 0);
+  signal ref_time_counter        : std_logic_vector(7 downto 0);
 
-  
+
+  signal lvl1_cts_busy_out_i : std_logic;
+  signal lvl2_cts_busy_out_i : std_logic;
+  signal lvl1_rnd_number_out_i : std_logic_vector(7 downto 0);
+  signal lvl2_rnd_number_out_i : std_logic_vector(7 downto 0);
 begin
 
+  
   ----------------------------------------------------------------------------
   -- Global reset
   ----------------------------------------------------------------------------
   MAKE_START_RESET: process (CLK)
   begin
     if rising_edge(CLK) then
-      if global_reset_counter < x"f" then
+      if global_reset_counter < x"e" then
         global_reset_counter <= global_reset_counter + 1;
         reset_i <= '1';
       else
@@ -1209,7 +1303,7 @@ begin
     end if;
   end process MAKE_START_RESET;
 
-     -- We should  add reseet from etrax ( . . .)
+     -- add reseet from etrax and from trbnet( . . .)
 
   ----------------------------------------------------------------------------
   -- LVDS signals
@@ -1237,6 +1331,7 @@ begin
 --         CLK0_OUT        => clk,
 --         CLK2X_OUT       => clk200,
 --         LOCKED_OUT      => locked_out);
+  
   -- AddOn clk ----------------------------------------------------------------
   IBUFGDS_ADDCLK : IBUFDS                 
     generic map (
@@ -1246,7 +1341,6 @@ begin
       I => ADDON_TO_TRB_CLKINP,  
       IB => ADDON_TO_TRB_CLKINN -- Diff_n clock buffer input (connect to top-level port)
       );
-
   
   -- TDC ----------------------------------------------------------------------
   IBUFGDS_TDC_CLK : IBUFGDS                 
@@ -1279,7 +1373,7 @@ begin
     port map ( O => D_TDC_EV_RESET, OB =>D_TDC_EV_RESETB, I => event_reset_i);
   
   --fast trigg-----------------------------------------------------------------
-  IBUFDS_FAST_TRIGGER : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
+  IBUFDS_FAST_TRIGGER : IBUFDS generic map (DIFF_TERM => TRUE)
     port map (I => VIR_TRIG, IB => VIR_TRIGB, O => fast_ref_trigger);
   
   -- SPI ----------------------------------------------------------------------
@@ -1394,157 +1488,168 @@ begin
   test_d2 <= '0' when (test_counter_1 < x"7D0" and fpga_register_0e_i(7)='1')  else '1';
 
   trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1)='1' or fpga_register_06_i(2) ='1' )) else '0';
+-------------------------------------------------------------------------------
+-- rpc temperature
+-------------------------------------------------------------------------------
+  GENERAT_ONE_WIRE_CONNECTION: for i in 0 to 3 generate
 
+    onewire_interface : trb_net_onewire
+    generic map(
+      USE_TEMPERATURE_READOUT => 1,
+      CLK_PERIOD => 10
+      )
+    port map(
+      CLK      => CLK,
+      RESET    => reset_i,
+      --connection to 1-wire interface
+      ONEWIRE  => TEMP_SENS(i),
+      --connection to id ram, according to memory map in TrbNetRegIO
+      DATA_OUT => open,
+      ADDR_OUT => open,
+      WRITE_OUT=> open,
+      TEMP_OUT => temp_sens_i(i),
+      STAT     => temp_sens_status_i(i)
+      );
+    
+  end generate GENERAT_ONE_WIRE_CONNECTION;
+  r_register_i(15)(11 downto 0)    <= temp_sens_i(0);
+  r_register_i(15)(23 downto 12) <= temp_sens_i(1);
+  r_register_i(16)(11 downto 0)    <= temp_sens_i(2);
+  r_register_i(16)(23 downto 12) <= temp_sens_i(3);
+  
+-- ADD_LVDS IN------------------------------------------------------------------
+    ADO_LVDS_IN_PROC: for line in 0 to 25 generate  --62 lines in total
+      IBUFDS_LVDS : IBUFDS
+        generic map (
+          DIFF_TERM => TRUE
+          )
+        port map (
+          I => ADO_LVDS_IN(line*2),
+          IB => ADO_LVDS_IN(line*2+1),  
+          O => lvds_add_on_data(line)
+          );
+    end generate ADO_LVDS_IN_PROC;
+  
+-- ADD_LVDS OUT------------------------------------------------------------------
+  ADO_LVDS_OUT_PROC: for line in 0 to 4 generate
+    OBUFDS_LVDS_LINE : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25"
+        )
+      port map (
+        O =>  ADO_LVDS_OUT(line*2),
+        OB => ADO_LVDS_OUT(line*2+1),
+        I => ado_lv_out_i(line)
+        );
+  end generate ADO_LVDS_OUT_PROC;
+      
 
--- ADD_LVDS ------------------------------------------------------------------
---    ADO_LVDS: for line in 0 to 25 generate  --62 lines in total
---      IBUFDS_LVDS : IBUFDS
---        generic map (
---          IOSTANDARD => "LVDS_25_DCI"
---          )
---        port map (
---          I => ADO_LV(line*2),
---          IB => ADO_LV(line*2+1),  
---          O => lvds_add_on_data(line)
---          );
---    end generate ADO_LVDS;
+  
+  
 -------------------------------------------------------------------------------
 -- tiger sharc dma
 -------------------------------------------------------------------------------
  
     
 -------------------------------------------------------------------------------
--- TRBnet
+-- TRBnet - cts
 -------------------------------------------------------------------------------
 
-  TRBnet: if trbnet_enable=1 generate
---     TRBNET_ENDPOINT_INST: trb_net16_endpoint_hades_full
---       generic map (
---           REGIO_NUM_STAT_REGS       => 4,
---           REGIO_NUM_CTRL_REGS       => 2,
---           REGIO_USE_DAT_PORT        => c_No,
---           REGIO_USED_CTRL_REGS      => (others => '1'),
---           REGIO_COMPILE_TIME        => conv_std_logic_vector(VERSION_NUMBER_TIME,32)
---           )
---       port map (
---           CLK                       => CLK,
---           RESET                     => reset_i,
---           CLK_EN                    => '1',
---           MED_DATAREADY_OUT         => med_dataready_out_i,
---           MED_DATA_OUT              => med_data_out_i,
---           MED_PACKET_NUM_OUT        => med_packet_num_out_i,
---           MED_READ_IN               => med_read_in_i,
---           MED_DATAREADY_IN          => med_dataready_in_i,
---           MED_DATA_IN               => med_data_in_i,
---           MED_PACKET_NUM_IN         => med_packet_num_in_i,
---           MED_READ_OUT              => med_read_out_i,
---           MED_STAT_OP_IN            => med_stat_op_in_i,
---           MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
---           LVL1_TRG_TYPE_OUT         => lvl1_trg_type_out_i,
---           LVL1_TRG_RECEIVED_OUT     => lvl1_trg_received_out_i,
---           LVL1_TRG_NUMBER_OUT       => lvl1_trg_number_out_i,
---           LVL1_TRG_CODE_OUT         => lvl1_trg_code_out_i,
---           LVL1_TRG_INFORMATION_OUT  => lvl1_trg_information_out_i,
---           LVL1_ERROR_PATTERN_IN     => lvl1_error_pattern_in_i,
---           LVL1_TRG_RELEASE_IN       => lvl1_trg_release_in_i,
---           IPU_NUMBER_OUT            => ipu_number_out_i,
---           IPU_INFORMATION_OUT       => ipu_information_out_i,
---           IPU_START_READOUT_OUT     => ipu_start_readout_out_i,
---           IPU_DATA_IN               => ipu_data_in_i,
---           IPU_DATAREADY_IN          => ipu_dataready_in_i,
---           IPU_READOUT_FINISHED_IN   => ipu_readout_finished_in_i,
---           IPU_READ_OUT              => ipu_read_out_i,
---           IPU_LENGTH_IN             => ipu_length_in_i,
---           IPU_ERROR_PATTERN_IN      => ipu_error_pattern_in_i,
---           REGIO_COMMON_STAT_REG_IN  => regio_common_stat_reg_in_i,
---           REGIO_COMMON_CTRL_REG_OUT => regio_common_ctrl_reg_out_i,
---           REGIO_REGISTERS_IN        => regio_registers_in_i,
---           REGIO_REGISTERS_OUT       => regio_registers_out_i,
---           REGIO_ADDR_OUT            => regio_addr_out_i,
---           REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
---           REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
---           REGIO_DATA_OUT            => regio_data_out_i,
---           REGIO_DATA_IN             => regio_data_in_i,
---           REGIO_DATAREADY_IN        => regio_dataready_in_i,
---           REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
---           REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
---           REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
---           REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
---           REGIO_IDRAM_DATA_IN       => regio_idram_data_in_i,
---           REGIO_IDRAM_DATA_OUT      => regio_idram_data_out_i,
---           REGIO_IDRAM_ADDR_IN       => regio_idram_addr_in_i,
---           REGIO_IDRAM_WR_IN         => regio_idram_wr_in_i,
---           REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
---           REGIO_EXT_REG_DATA_IN     => regio_ext_reg_data_in_i,
---           REGIO_EXT_REG_DATA_OUT    => regio_ext_reg_data_out_i,
---           REGIO_EXT_REG_WRITE_IN    => regio_ext_reg_write_in_i,
---           REGIO_EXT_REG_ADDR_IN     => regio_ext_reg_addr_in_i,
---           STAT_DEBUG_IPU            => stat_debug_ipu_i,
---           STAT_DEBUG_1              => stat_debug_1_i,
---           STAT_DEBUG_2              => stat_debug_2_i,
---           MED_STAT_OP               => med_stat_op_i,
---           CTRL_MPLEX                => ctrl_mplex_i,
---           IOBUF_CTRL_GEN            => iobuf_ctrl_gen_i,
---           STAT_ONEWIRE              => stat_onewire_i,
---           STAT_ADDR_DEBUG           => stat_addr_debug_i);
-
---   -----------------------------------------------------------------------------
---   -- media to api, api to media
---   -----------------------------------------------------------------------------
+  TRBnet_CTS: if TRBNET_ENABLE=2 generate
     
---      TLK_RX_CLK_BUFR : BUFR
---        port map(
---          CE => '1',
---          CLR => '0',
---          I => TLK_RX_CLK,
---          O => tlk_rx_clk_r(0)
---          );
     
---      TLK_CLK_BUFR: BUFR
---        port map(
---          CE => '1',
---          CLR => '0',
---          I => TLK_CLK,
---          O => tlk_clk_r(0)
---          );
-    
---      TLK_API_INT: trb_net16_med_tlk
---        port map (
---          RESET              => reset_i,
---          CLK                => CLK,
---          TLK_CLK            => tlk_clk_r(0),
---          TLK_ENABLE         => TLK_ENABLE,
---          TLK_LCKREFN        => TLK_LCKREFN,
---          TLK_LOOPEN         => TLK_LOOPEN,
---          TLK_PRBSEN         => TLK_PRBSEN,
---          TLK_RXD            => TLK_RXD,
---          TLK_RX_CLK         => tlk_rx_clk_r(0),
---          TLK_RX_DV          => TLK_RX_DV,
---          TLK_RX_ER          => TLK_RX_ER,
---          TLK_TXD            => TLK_TXD,
---          TLK_TX_EN          => TLK_TX_EN,
---          TLK_TX_ER          => TLK_TX_ER,
---          SFP_LOS            => SFP_LOS,
---          SFP_TX_DIS         => SFP_TX_DIS,
---          MED_DATAREADY_IN   => med_dataready_in_i,
---          MED_READ_IN        => med_read_in_i,
---          MED_DATA_IN        => med_data_in_i,
---          MED_PACKET_NUM_IN  => med_packet_num_in_i,
---          MED_DATAREADY_OUT  => med_dataready_out_i,
---          MED_READ_OUT       => med_read_out_i,
---          MED_DATA_OUT       => med_data_out_i,
---          MED_PACKET_NUM_OUT => med_packet_num_out_i,
---          MED_ERROR_OUT      => med_error_out_i,
---          STAT               => stat_i,
---          STAT_MONITOR       => open,
---          STAT_OP            => stat_op_i,
---          CTRL_OP            => ctrl_op_i);
-    end generate TRBnet;
-
-  
-  -------------------------------------------------------------------------------
-  -- Vulom interafce
-  -------------------------------------------------------------------------------
+    THE_TRBNET_CTS : trb_net16_endpoint_hades_cts
+      generic map (
+        USE_CHANNEL               =>  (c_YES, c_YES, c_NO, c_YES),
+        IBUF_DEPTH                => (6, 6, 6, 6),
+        FIFO_TO_INT_DEPTH         => (1, 1, 6, 6),
+        FIFO_TO_APL_DEPTH         => (1, 6, 6, 6),
+        INIT_CAN_SEND_DATA        => (c_YES, c_YES, c_NO, c_NO),
+        REPLY_CAN_SEND_DATA       => (c_NO, c_NO, c_NO, c_YES),
+        REPLY_CAN_RECEIVE_DATA    => (c_YES, c_YES, c_NO, c_NO),
+        USE_CHECKSUM              => (c_NO, c_YES, c_YES, c_YES),
+        APL_WRITE_ALL_WORDS       => (c_NO, c_NO, c_NO, c_NO),
+        BROADCAST_BITMASK         => x"FF",
+        REGIO_NUM_STAT_REGS       => 2,  --log2 of number of status registers
+        REGIO_NUM_CTRL_REGS       => 3,  --log2 of number of ctrl registers
+        --standard values for out
+        REGIO_INIT_CTRL_REGS      => (others => '0'),
+        --set to 0 for unused ctr
+        REGIO_USED_CTRL_REGS      => "00000001",
+        --set to 0 for each unuse
+        REGIO_USED_CTRL_BITMASK   => (others => '1'),
+        REGIO_USE_DAT_PORT        => c_YES,  --internal data port
+        REGIO_INIT_ADDRESS        => x"FFFF",
+        REGIO_INIT_UNIQUE_ID      => x"0000_0000_0000_0000",
+        REGIO_INIT_BOARD_INFO     => x"0000_0000",
+        REGIO_INIT_ENDPOINT_ID    => x"0001",
+        REGIO_COMPILE_TIME        => x"00000000",
+        REGIO_COMPILE_VERSION     => x"0001",
+        REGIO_HARDWARE_VERSION    => x"00000000",
+        REGIO_USE_1WIRE_INTERFACE => c_YES,  --c_YES,c_NO,c_MONITOR
+        CLOCK_FREQUENCY           => 100
+        )
+        port map (
+          CLK                       => CLK,
+          RESET                     => reset_i,
+          CLK_EN                    => '1',
+          MED_DATAREADY_OUT         => med_dataready_in_i(0),
+          MED_DATA_OUT              => med_data_in_i,
+          MED_PACKET_NUM_OUT        => med_packet_num_in_i,
+          MED_READ_IN               => '1',--med_read_out_i(0),
+          MED_DATAREADY_IN          => med_dataready_out_i(0),
+          MED_DATA_IN               => med_data_out_i,
+          MED_PACKET_NUM_IN         => med_packet_num_out_i,
+          MED_READ_OUT              => med_read_in_i(0),
+          MED_STAT_OP_IN            => med_stat_op_in_i,
+          MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
+          TRG_SEND_IN               => lvl1_trigger_i,
+          TRG_TYPE_IN               => lvl1_trigger_code_i,
+          TRG_NUMBER_IN             => lvl1_trigger_tag_i,
+          TRG_INFORMATION_IN        => x"00",
+          TRG_RND_CODE_IN           => lvl1_rnd_number_out_i,
+          TRG_STATUS_BITS_OUT       => trg_status_bits_out_i,
+          TRG_BUSY_OUT              => trg_busy_out_i,
+          IPU_SEND_IN               => lvl2_trigger_i,
+          IPU_TYPE_IN               => lvl2_trigger_code_i,
+          IPU_NUMBER_IN             => lvl2_trigger_tag_i,
+          IPU_INFORMATION_IN        => x"00",
+          IPU_RND_CODE_IN           => lvl2_rnd_number_out_i,
+          IPU_DATA_OUT              => ipu_data_out_i,
+          IPU_DATAREADY_OUT         => ipu_dataready_out_i,
+          IPU_READ_IN               => '1',--ipu_read_in_i,
+          IPU_STATUS_BITS_OUT       => ipu_status_bits_out_i,
+          IPU_BUSY_OUT              => ipu_busy_out_i,
+          REGIO_COMMON_STAT_REG_IN  => (others => '0'),--regio_common_stat_reg_in_i,
+          REGIO_COMMON_CTRL_REG_OUT => open,--regio_common_ctrl_reg_out_i,
+          REGIO_REGISTERS_IN        => regio_registers_in_i,
+          REGIO_REGISTERS_OUT       => regio_registers_out_i,
+          REGIO_ADDR_OUT            => regio_addr_out_i,
+          REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
+          REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
+          REGIO_DATA_OUT            => regio_data_out_i,
+          REGIO_DATA_IN             => regio_data_in_i,
+          REGIO_DATAREADY_IN        => regio_dataready_in_i,
+          REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
+          REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
+          REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
+          REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
+          REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
+          REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
+          REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
+          TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
+          GLOBAL_TIME_OUT           => global_time_out_i,
+          LOCAL_TIME_OUT            => local_time_out_i,
+          TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
+          TIMER_US_TICK_OUT         => open,
+          STAT_DEBUG_1              => stat_debug_1_i,
+          STAT_DEBUG_2              => stat_debug_2_i);
+  end generate TRBnet_CTS;
+
+-------------------------------------------------------------------------------
+-- Vulom interafce
+-------------------------------------------------------------------------------
+  
   VULOM_EN: if TRBV2_TYPE = 4 generate
     vulom_busy <= lvl1_busy_i or opt_lvl1_busy_i ;
      VULOM_INT : vulom_interface
@@ -1564,10 +1669,10 @@ begin
          API_RUN_OUT                  => vulom_busy,--lvl1_busy_i,  --lvl1_cts_busy or lvl1_system_busy,  --apl_run_out_i,
          API_SHORT_TRANSFER           => open,
          API_DTYPE                    => open,
-         API_SEND                     => apl_send_in_i,
+         API_SEND                     => lvl1_vulom_trigger,
          API_WRITE_IN                 => open,
          API_TARGET_ADDRESS           => open,
-         API_SEQNR_OUT                => apl_seqnr_out_i,  --x"00",
+         API_SEQNR_OUT                => x"00",
          VULOM_INT_REG                => fpga_register_09_i,--vulom_int_reg_00,
          INTERFACE_CONTROL            => fpga_register_06_i(11 downto 8),
          EVENT_OUT                    => vulom_event,
@@ -1577,20 +1682,300 @@ begin
          START_READOUT                => vulom_lvl1_trigger_i,
          LVL1_TRANSFER_BUSY           => lvl1_busy_i, --lvl1_cts_busy  --lvl1_cts_busy or lvl1_system_busy
          LVL1_TRIGGER_CODE            => vulom_lvl1_trigger_code_i,
-         LVL1_TRIGGER_TAG             => vulom_lvl1_trigger_tag_i 
+         LVL1_TRIGGER_TAG             => vulom_lvl1_trigger_tag_i(7 downto 0) 
          );
      ADO_TTL(42 downto 40) <= (others => 'Z');
 --           ADO_TTL(34) <= '1';
     
   end generate VULOM_EN;
 
+
   
-  --------------------------------------------------------------------------- 
-  -- tdc interface 
-  ---------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- cts
+-------------------------------------------------------------------------------  
+  CTS_GENERATE : if TRBNET_ENABLE /= 1 generate
+    THE_CTS : cts
+      generic map (
+        TRBNET_ENABLE => TRBNET_ENABLE
+        )
+      port map (
+        RESET                      => reset_i,
+        CLK                        => CLK,
+        CLK40_IN                   => TDC_CLK,
+        LVL1_LVDS_TRIGGER_IN       => lvds_add_on_data(4 downto 0),
+        LVL1_TTL_TRIGGER_IN        => ADO_TTL(20 downto 16),
+        LVL1_FAST_TRIGG_IN         => fast_ref_trigger,
+        LVL1_TIMING_TRIGGER_OUT    => ado_lv_out_i(0),
+        LVL1_APV_TRIGGER_OUT       => ado_lv_out_i(1),
+        LVL1_VULOM_TRIGGER_IN      => lvl1_vulom_trigger,
+        LVL1_VULOM_TRIGGER_CODE_IN => vulom_lvl1_trigger_code_i,
+        LVL1_VULOM_TRIGGER_TAG_IN  => vulom_lvl1_trigger_tag_i,
+        LVL1_VULOM_BUSY_IN         => '0',   --vulom_busy,
+        LVL1_LOCAL_BUSY            => '0',   --lvl1_busy_i,
+        LVL1_TRBNET_BUSY           => trg_busy_out_i,
+        LVL1_CTS_BUSY_OUT          => lvl1_cts_busy_out_i,
+        LVL1_TRIGGER_OUT           => lvl1_trigger_i,
+        LVL1_TRIGGER_CODE_OUT      => lvl1_trigger_code_i,
+        LVL1_TRIGGER_TAG_OUT       => lvl1_trigger_tag_i,
+        LVL1_RND_NUMBER_OUT        => lvl1_rnd_number_out_i,
+        LVL2_LVDS_TRIGGER_IN       => '0',   --lvds_add_on_data(6),
+        LVL2_LVDS_TRIGGER_CODE_IN  => x"0",  --lvds_add_on_data(10 downto 7),
+        LVL2_LVDS_TRIGGER_TAG_IN   => x"0000",  --lvds_add_on_data(26 downto 11),
+        LVL2_LOCAL_TRIGGER_IN      => '0',   --lvl2_local_trigger_in_i,
+        LVL2_LOCAL_TRIGGER_CODE_IN => x"0",  --lvl2_local_trigger_code_in_i,
+        LVL2_LOCAL_TRIGGER_TAG_IN  => x"0000",  --lvl2_local_trigger_tag_in_i,
+        LVL2_LOCAL_BUSY            => '0',--lvl2_busy_i,
+        LVL2_TRBNET_BUSY           => ipu_busy_out_i,
+        LVL2_CTS_BUSY_OUT          => lvl2_cts_busy_out_i,
+        LVL2_TRIGGER_OUT           => lvl2_trigger_i,
+        LVL2_TRIGGER_CODE_OUT      => lvl2_trigger_code_i,
+        LVL2_TRIGGER_TAG_OUT       => lvl2_trigger_tag_i,
+        LVL2_RND_NUMBER_OUT        => lvl2_rnd_number_out_i,
+        CTS_STASUS_0UT_0           => r_register_i(17),
+        CTS_STASUS_0UT_1           => r_register_i(18),
+        CTS_STASUS_0UT_2           => r_register_i(19),
+        CTS_CTRL_IN_0              => rw_register_i(5),
+        CTS_CTRL_IN_1              => rw_register_i(6)
+        );
+
+    ado_lv_out_i(2) <= lvl1_cts_busy_out_i;
+    ado_lv_out_i(3) <= lvl2_cts_busy_out_i;
+    ado_lv_out_i(4) <= TDC_CLK;
+
+  end generate CTS_GENERATE;
+
+  TRBnet_END_POINT : if TRBNET_ENABLE = 1 generate
+    
+    THE_TRBNET_END_POINT: trb_net16_endpoint_hades_full
+      generic map(
+        USE_CHANNEL                  => (c_YES,c_YES,c_NO,c_YES),
+        IBUF_DEPTH                   => (6,6,6,6),
+        FIFO_TO_INT_DEPTH            => (6,6,6,6),
+        FIFO_TO_APL_DEPTH            => (1,1,1,1),
+        IBUF_SECURE_MODE             => (c_YES,c_YES,c_YES,c_YES),
+        API_SECURE_MODE_TO_APL       => (c_YES,c_YES,c_YES,c_YES),
+        API_SECURE_MODE_TO_INT       => (c_YES,c_YES,c_YES,c_YES),
+        OBUF_DATA_COUNT_WIDTH        => std_DATA_COUNT_WIDTH,
+        INIT_CAN_SEND_DATA           => (c_NO,c_NO,c_NO,c_NO),
+        REPLY_CAN_SEND_DATA          => (c_YES,c_YES,c_YES,c_YES),
+        REPLY_CAN_RECEIVE_DATA       => (c_NO,c_NO,c_NO,c_NO),
+        USE_CHECKSUM                 => (c_NO,c_YES,c_YES,c_YES),
+        APL_WRITE_ALL_WORDS          => (c_NO,c_NO,c_NO,c_NO),
+        BROADCAST_BITMASK            => x"FF",
+        REGIO_NUM_STAT_REGS          => 3, --log2 of number of status registers
+        REGIO_NUM_CTRL_REGS          => 3, --log2 of number of ctrl registers
+        --standard values for output registers
+        REGIO_INIT_CTRL_REGS         => (others => '0'),
+        --set to 0 for unused ctrl registers to save resources
+        REGIO_USED_CTRL_REGS         => "00000001",
+        --set to 0 for each unused bit in a register
+        REGIO_USED_CTRL_BITMASK      => (others => '1'),
+        REGIO_USE_DAT_PORT           => c_YES,  --internal data port
+        REGIO_INIT_ADDRESS           => x"FFFF",
+        REGIO_INIT_UNIQUE_ID         => x"1000_2000_3654_4876",
+        REGIO_INIT_BOARD_INFO        => x"1111_2222",
+        REGIO_INIT_ENDPOINT_ID       => x"0001",
+        REGIO_COMPILE_TIME           => x"00000000",
+        REGIO_COMPILE_VERSION        => x"0001",
+        REGIO_HARDWARE_VERSION       => x"12345678",
+        REGIO_USE_1WIRE_INTERFACE    => c_YES, --c_YES,c_NO,c_MONITOR
+        CLOCK_FREQUENCY              => 100
+        )
+    port map (
+      CLK                       => CLK,
+      RESET                     => reset_i,
+      CLK_EN                    => '1',
+      MED_DATAREADY_OUT         => med_dataready_in_i(0),
+      MED_DATA_OUT              => med_data_in_i,
+      MED_PACKET_NUM_OUT        => med_packet_num_in_i,
+      MED_READ_IN               => '1',--med_read_out_i(0),
+      MED_DATAREADY_IN          => med_dataready_out_i(0),
+      MED_DATA_IN               => med_data_out_i,
+      MED_PACKET_NUM_IN         => med_packet_num_out_i,
+      MED_READ_OUT              => med_read_in_i(0),
+      MED_STAT_OP_IN            => med_stat_op_in_i,
+      MED_CTRL_OP_OUT           => med_ctrl_op_out_i,
+      LVL1_TRG_TYPE_OUT         => lvl1_trigger_code_i,--open,
+      LVL1_TRG_RECEIVED_OUT     => lvl1_trigger_i,
+      LVL1_TRG_NUMBER_OUT       => lvl1_trigger_tag_i,
+      LVL1_TRG_CODE_OUT         => open,--lvl1_trigger_code_i,
+      LVL1_TRG_INFORMATION_OUT  => open,
+      LVL1_ERROR_PATTERN_IN     => (others => '0'),
+      LVL1_TRG_RELEASE_IN       => lvl1_finished_i,
+      IPU_NUMBER_OUT            => lvl2_trigger_tag_i,
+      IPU_INFORMATION_OUT       => open,
+      IPU_START_READOUT_OUT     => lvl2_trigger_i,
+      IPU_DATA_IN               => ipu_data_in_i,--(others => '0'),
+      IPU_DATAREADY_IN          => ipu_dataready_in_i,--tdc_data_valid_i,
+      IPU_READOUT_FINISHED_IN   => lvl2_finished_i,
+      IPU_READ_OUT              => ipu_read_out_i,
+      IPU_LENGTH_IN             => (others => '0'),
+      IPU_ERROR_PATTERN_IN      => (others => '0'),
+      REGIO_COMMON_STAT_REG_IN  => (others => '0'),
+      REGIO_COMMON_CTRL_REG_OUT => open,
+      REGIO_REGISTERS_IN        => (others => '0'),
+      REGIO_REGISTERS_OUT       => regio_registers_out_i,
+      REGIO_ADDR_OUT            => regio_addr_out_i,
+      REGIO_READ_ENABLE_OUT     => regio_read_enable_out_i,
+      REGIO_WRITE_ENABLE_OUT    => regio_write_enable_out_i,
+      REGIO_DATA_OUT            => regio_data_out_i,
+      REGIO_DATA_IN             => regio_data_in_i,
+      REGIO_DATAREADY_IN        => regio_dataready_in_i,
+      REGIO_NO_MORE_DATA_IN     => regio_no_more_data_in_i,
+      REGIO_WRITE_ACK_IN        => regio_write_ack_in_i,
+      REGIO_UNKNOWN_ADDR_IN     => regio_unknown_addr_in_i,
+      REGIO_TIMEOUT_OUT         => regio_timeout_out_i,
+      REGIO_IDRAM_DATA_IN       => regio_idram_data_in_i,
+      REGIO_IDRAM_DATA_OUT      => regio_idram_data_out_i,
+      REGIO_IDRAM_ADDR_IN       => regio_idram_addr_in_i,
+      REGIO_IDRAM_WR_IN         => regio_idram_wr_in_i,
+      REGIO_ONEWIRE_INOUT       => regio_onewire_inout_i,
+      REGIO_ONEWIRE_MONITOR_IN  => regio_onewire_monitor_in_i,
+      REGIO_ONEWIRE_MONITOR_OUT => regio_onewire_monitor_out_i,
+      TRIGGER_MONITOR_IN        => trigger_monitor_in_i,
+      GLOBAL_TIME_OUT           => global_time_out_i,
+      LOCAL_TIME_OUT            => local_time_out_i,
+      TIME_SINCE_LAST_TRG_OUT   => time_since_last_trg_out_i,
+      TIMER_US_TICK_OUT         => timer_us_tick_out_i,
+      STAT_DEBUG_IPU            => stat_debug_ipu_i,
+      STAT_DEBUG_1              => stat_debug_1_i,
+      STAT_DEBUG_2              => stat_debug_2_i,
+      MED_STAT_OP               => open,
+      CTRL_MPLEX                => (others => '0'),
+      IOBUF_CTRL_GEN            => (others => '0'),
+      STAT_ONEWIRE              => open,
+      STAT_ADDR_DEBUG           => open);
+    
+    
+    EXT_LVL2_PULSER : edge_to_pulse
+      port map (
+        clock  => CLK,
+        en_clk => '1',
+        signal_in => lvl2_trigger_i,
+        pulse  => lvl2_trigger_i_pulse);
+    
+    
+    MAKE_DUMMY_DATA_IN : process (CLK, reset_i)
+    begin
+      if rising_edge(CLK) then
+        if reset_i= '1' or (cntr_for_dummy_header = 1 and ipu_read_out_i = '1') or (cntr_for_dummy_header = 3 and lvl2_finished_i = '0')then
+          ipu_dataready_in_i <= '0';
+          cntr_for_dummy_header <= cntr_for_dummy_header(0) & cntr_for_dummy_header(1);
+        elsif lvl2_trigger_i_pulse = '1' or (cntr_for_dummy_header = 2 and ipu_read_out_i = '1') then
+          ipu_dataready_in_i <= '1';
+          cntr_for_dummy_header <= cntr_for_dummy_header +1;
+        elsif lvl2_finished_i = '1' then
+          ipu_dataready_in_i <= '0';
+          cntr_for_dummy_header <=  "00";
+        end if;
+      end if;
+    end process MAKE_DUMMY_DATA_IN;
+    ipu_data_in_i <= x"0" & x"4" & x"83" & x"0000" when cntr_for_dummy_header < 2 else x"00000000";
+    
+   end generate TRBnet_END_POINT;
+
+--   -----------------------------------------------------------------------------
+--   -- media to api, api to media
+--   -----------------------------------------------------------------------------
+    
+      TLK_RX_CLK_BUFR : BUFR
+        port map(
+          CE => '1',
+          CLR => '0',
+          I => TLK_RX_CLK,
+          O => tlk_rx_clk_r(0)
+          );
+    
+      TLK_CLK_BUFR: BUFR
+        port map(
+          CE => '1',
+          CLR => '0',
+          I => TLK_CLK,
+          O => tlk_clk_r(0)
+          );
+    
+      TLK_API_INT: trb_net16_med_tlk
+        port map (
+          RESET              => reset_i,
+          CLK                => CLK,
+          TLK_CLK            => tlk_clk_r(0),
+          TLK_ENABLE         => TLK_ENABLE,
+          TLK_LCKREFN        => TLK_LCKREFN,
+          TLK_LOOPEN         => TLK_LOOPEN,
+          TLK_PRBSEN         => TLK_PRBSEN,
+          TLK_RXD            => TLK_RXD,
+          TLK_RX_CLK         => tlk_rx_clk_r(0),
+          TLK_RX_DV          => TLK_RX_DV,
+          TLK_RX_ER          => TLK_RX_ER,
+          TLK_TXD            => TLK_TXD,
+          TLK_TX_EN          => TLK_TX_EN,
+          TLK_TX_ER          => TLK_TX_ER,
+          SFP_LOS            => SFP_LOS,
+          SFP_TX_DIS         => SFP_TX_DIS,
+          MED_DATAREADY_IN   => med_dataready_in_i(0),
+          MED_READ_IN        => med_read_in_i(0),
+          MED_DATA_IN        => med_data_in_i,
+          MED_PACKET_NUM_IN  => med_packet_num_in_i,
+          MED_DATAREADY_OUT  => med_dataready_out_i(0),
+          MED_READ_OUT       => med_read_out_i(0),
+          MED_DATA_OUT       => med_data_out_i,
+          MED_PACKET_NUM_OUT => med_packet_num_out_i,
+          STAT               => open,
+          STAT_MONITOR       => open,
+          STAT_OP            => med_stat_op_in_i,
+          CTRL_OP            => x"0000");
+    DGOOD <=  med_stat_op_in_i(9);
+  
+--  r_register_i(20)(8) <= lvds_add_on_data(0) and
+--                          lvds_add_on_data(1) and
+--                          lvds_add_on_data(2) and
+--                          lvds_add_on_data(3) and
+--                          lvds_add_on_data(4) and
+--                          lvds_add_on_data(5) and
+--                          lvds_add_on_data(6) and
+--                          lvds_add_on_data(7) and
+--                          lvds_add_on_data(8) and
+--                          lvds_add_on_data(9) and
+--                          lvds_add_on_data(10) and
+--                          lvds_add_on_data(11) and
+--                          lvds_add_on_data(12) and
+--                          lvds_add_on_data(13) and
+--                          lvds_add_on_data(14) and
+--                          lvds_add_on_data(15) and
+--                          lvds_add_on_data(16) and
+--                          lvds_add_on_data(17) and
+--                          lvds_add_on_data(18) and
+--                          lvds_add_on_data(19) and
+--                          lvds_add_on_data(21) and
+--                          lvds_add_on_data(22) and
+--                          lvds_add_on_data(23) and
+--                          lvds_add_on_data(24) and
+--                          lvds_add_on_data(25);
+
+--------------------------------------------------------------------------- 
+-- tdc interface 
+---------------------------------------------------------------------------
+  --debug
+  
+--    ADO_TTL(0) <= not_hades_trigger;
+--    ADO_TTL(1) <= trigger_to_tdc_i;
+--    ADO_TTL(2) <= lvl1_busy_i;
+--    ADO_TTL(3) <= A_DATA_READY;
+--    ADO_TTL(4) <= B_DATA_READY;
+--    ADO_TTL(5) <= C_DATA_READY;
+--    ADO_TTL(6) <= D_DATA_READY;
+--    ADO_TTL(7) <= token_out_i;
+--    ADO_TTL(8) <= TOKEN_IN;
+--    ADO_TTL(9) <= lvl2_busy_i;
+--    ADO_TTL(10) <= bunch_reset_i;
+--    ADO_TTL(11) <= event_reset_i;
+--    ADO_TTL(12) <= TDC_CLK;
+   --end debug
   VIRT_TRST <= not fpga_register_06_i(5);--'1';
   TDC_RESET <= '0';--fpga_register_06_i(5);--'0';
 
+  --TDC TRB
   TDC_INT_FOR_DIFF_PLATFORMSa: if TRBV2_TYPE = 0 generate
     tdc_clk_i <= TDC_CLK;
     tdc_data_in_i <= TDC_OUT;
@@ -1602,6 +1987,7 @@ begin
     TOKEN_OUT <= token_out_i;
   end generate TDC_INT_FOR_DIFF_PLATFORMSa;
 
+  --Shower or MDC
   TDC_INT_FOR_DIFF_PLATFORMSb: if TRBV2_TYPE = 1 or TRBV2_TYPE = 2 generate
     tdc_clk_i <= addon_clk;
     tdc_data_in_i <= ADO_TTL(38 downto 7);
@@ -1628,6 +2014,7 @@ begin
     
   end generate TDC_INT_FOR_DIFF_PLATFORMSb;
 
+  --CTS plus Vulom
    TDC_INT_FOR_DIFF_PLATFORMSc: if TRBV2_TYPE = 4 generate
      tdc_clk_i <= CLK;
      tdc_data_in_i <= vulom_event;
@@ -1639,20 +2026,32 @@ begin
      vulom_readout_start <= token_out_i;          --longer token !?
      TOKEN_OUT <= '0';
    end generate TDC_INT_FOR_DIFF_PLATFORMSc;
-  
+
+  --Only CTS
   TDC_INT_FOR_DIFF_PLATFORMSd: if TRBV2_TYPE = 5 generate
+    
+    not_ipu_dataready_out_i <=  ipu_dataready_out_i;
+    
+    EXT_TRIGGER_1 : edge_to_pulse
+      port map (
+        clock  => TDC_CLK,
+        en_clk => '1',
+        signal_in => not_ipu_dataready_out_i,
+        pulse  => ipu_dataready_out_end_pulse);
+    
      tdc_clk_i <= CLK;
-     tdc_data_in_i <= x"babeface";
-     a_data_ready_i <= '0';--start_readout_i;
-     b_data_ready_i <= '0';--start_readout_i;
-     c_data_ready_i <= '0';--start_readout_i;
-     d_data_ready_i <= '0';--start_readout_i;
-     token_in_i <= '0';
+     tdc_data_in_i <= ipu_data_out_i;
+     a_data_ready_i <= ipu_dataready_out_i;
+     b_data_ready_i <= ipu_dataready_out_i;
+     c_data_ready_i <= ipu_dataready_out_i;
+     d_data_ready_i <= ipu_dataready_out_i;
+     token_in_i <= ipu_dataready_out_end_pulse ;
      TOKEN_OUT <= '0';
+    
    end generate TDC_INT_FOR_DIFF_PLATFORMSd;
 
  
-  TDC_INT : tdc_interface
+  TDC_INT : tdc_interfacev2
     generic map (
       ENABLE_DMA => ENABLE_DMA,
       NUMBER_OFF_ADD_DATA =>  NUMBER_OFF_ADD_DATA
@@ -1667,10 +2066,6 @@ begin
       B_TDC_ERROR            => B_TDC_ERROR,
       C_TDC_ERROR            => C_TDC_ERROR,
       D_TDC_ERROR            => D_TDC_ERROR,
-      A_TDC_POWERUP          => open,   --A_TDC_POWERUP, ??????????????????
-      B_TDC_POWERUP          => open,   --B_TDC_POWERUP,
-      C_TDC_POWERUP          => open,   --C_TDC_POWERUP,
-      D_TDC_POWERUP          => open,   --D_TDC_POWERUP,
       A_TDC_READY            => a_data_ready_i,
       B_TDC_READY            => b_data_ready_i,
       C_TDC_READY            => c_data_ready_i,
@@ -1680,8 +2075,9 @@ begin
       GET_TDC_DATA           => GET_DATA,
       LVL2_READOUT_COMPLETED => lvl2_readout_completed_i,
       LVL1_TAG               => lvl1_trigger_tag_i,  --apl_seqnr_out_i,  --tdc_tag_i,
+      LVL1_RND_CODE          => lvl1_rnd_number_out_i,  --apl_seqnr_out_i,  --tdc_tag_i,
       LVL1_CODE              => lvl1_trigger_code_i,  --apl_data_out_i(3 downto 0),  --tdc_code_i,
-      LVL2_TAG               => lvl2_trigger_tag_i,  --apl_seqnr_out_i,  --tdc_tag_i,
+      LVL2_TAG               => lvl2_trigger_tag_i(7 downto 0),  --apl_seqnr_out_i,  --tdc_tag_i,
       HOW_MANY_ADD_DATA      => fpga_register_06_i(23 downto 16), 
       ADDITIONAL_DATA        => additional_data_i,
       LVL2_TRIGGER           => lvl2_trigger_i, 
@@ -1700,128 +2096,22 @@ begin
       BUNCH_RESET            => bunch_reset_i,
       EVENT_RESET            => event_reset_i,
       DELAY_TRIGGER          => fpga_register_06_i(31 downto 24),
+      DELAY_TOKEN            => fpga_register_0e_i(23 downto 16),
       TDC_START              => trigger_to_tdc_i,
-      TRIGGER_WITHOUT_HADES  => fpga_register_06_i(7),
       TRIGGER_WITH_GEN_EN    => fpga_register_06_i(8),
       TRIGGER_WITH_GEN       => not_hades_trigger,
-      TRB_ID                 => rw_register_i((4+1)*32-1 downto 4*32)
+      TRB_ID                 => rw_register_i(4),
+      LVL1_FINISHED          => lvl1_finished_i,
+      LVL2_FINISHED          => lvl2_finished_i,
+      TRBNET_HEADER_BUILD    => rw_register_i(3)(31)
       );
-  ONE_SECOND_COUNTER: up_down_counter
-      generic map (
-        NUMBER_OF_BITS => 28)
-      port map (
-        CLK       => CLK,
-        RESET     => one_second_reset,
-        COUNT_OUT => one_second_cntr,
-        UP_IN     => '1',
-        DOWN_IN   => '0');
-  
-  SET_RESET_EACH_ONE_SECOND : process (CLK, reset_i)
-  begin  
-    if rising_edge(CLK) then  
-      if reset_i = '1' then
-        one_second_reset <= '0';
-        r_register_i((14+1)*32-1 downto 14*32) <= (others => '0');
-      elsif one_second_cntr = x"5F5E100" then
-        one_second_reset <= '1';
-         r_register_i((14+1)*32-1 downto 14*32) <= x"000" & event_rate_cntr;
-      else
-        one_second_reset <= '0';
-        r_register_i((14+1)*32-1 downto 14*32) <= r_register_i((14+1)*32-1 downto 14*32);
-      end if;
-    end if;
-  end process SET_RESET_EACH_ONE_SECOND;
-
-  LOCAL_CLK_EVENT_END_PULSE : edge_to_pulse
-    port map (
-      clock  => CLK,
-      en_clk => '1',
-      signal_in => token_in_i,--fast_ref_trigger_synch,
-      pulse  => event_end_pulse);
-
-    
-  TRIGGER_COUNTER_RATE: up_down_counter
-      generic map (
-        NUMBER_OF_BITS => 20)
-      port map (
-        CLK       => CLK,
-        RESET     => one_second_reset,
-        COUNT_OUT => event_rate_cntr,
-        UP_IN     => event_end_pulse,
-        DOWN_IN   => '0');
-
 
---  not_hades_trigger <= trigger_for_test_signal or fast_ref_trigger_pulse;  --'0';  -- or trigger_for_test_signal;
-  ADO_TTL(24) <= 'Z';
---  not_hades_trigger <= trigger_for_test_signal or ADO_TTL(24) or fast_ref_trigger or self_trigg_counter(7);  --'0';  -- or trigger_for_test_signal;
-
-  CONFIG_SELF_TRIG : process (CLK, reset_i)
-  begin  
-    if rising_edge(CLK) then  
-      if reset_i = '1' then
-        self_trigg <= '0';
-      else
-        case (rw_register_i( (3+1)*32 - 1 downto (3*32) +28)) is
-          when x"0" =>
-            self_trigg <=  one_second_cntr(26);
-          when x"1" =>
-            self_trigg <=  one_second_cntr(22);
-          when x"2" =>
-            self_trigg <=  one_second_cntr(18);
-          when x"3" =>
-            self_trigg <=  one_second_cntr(14);
-          when x"4" =>
-            self_trigg <=  one_second_cntr(10);
-          when x"5" =>
-            self_trigg <=  one_second_cntr(8);
-          when x"6" =>
-            self_trigg <=  one_second_cntr(4);
-          when x"7" =>
-            self_trigg <=  one_second_cntr(0);
-          when others =>
-            self_trigg <= '0';
-        end case;
-      end if;
-    end if;
-  end process CONFIG_SELF_TRIG;
-  SYNCH_EXTERNAL_TRIGGER : process (CLK, reset_i)
-  begin  
-    if rising_edge(CLK) then  
-      if reset_i = '1' then
-        not_hades_trigger <= '0';
-      else
-        not_hades_trigger <= (ADO_TTL(24) and rw_register_i(3*32+3)) or (fast_ref_trigger and  rw_register_i(3*32+2)) or (self_trigg and rw_register_i(3*32+1)) ;  
-      end if;
-    end if;
-  end process SYNCH_EXTERNAL_TRIGGER;
-  
+  -----------------------------------------------------------------------------
+  -- lvl1 trigger logic 
+  -----------------------------------------------------------------------------
   
-
--- correct trigers - miss match , check reference time (on two diff boards counters) 
-
   
-  SET_SAF_MODE: process (TDC_CLK,reset_i)
-  begin
-    if rising_edge(TDC_CLK) then  
-      if reset_i = '1' or lvl2_trigger_i = '1' then
-        safe_mode_only_one_ref <= '1';
-      elsif fast_ref_trigger_pulse = '1' then
-        safe_mode_only_one_ref <= '0';
-      end if;
-    end if; 
-  end process SET_SAF_MODE;
   
-  MAKE_SYNCH_REF: process (TDC_CLK, reset_i)
-  begin  
-    if rising_edge(TDC_CLK) then  
-      if reset_i = '1' then
-        fast_ref_trigger_synch <= '0';
-      else 
-        fast_ref_trigger_synch <= (fast_ref_trigger and safe_mode_only_one_ref);
-      end if;
-    end if;
-  end process MAKE_SYNCH_REF;
-
   OMIT_PROBLEM_WITH_MISS_REF: process (CLK, reset_i)
   begin  
     if rising_edge(CLK) then
@@ -1838,7 +2128,8 @@ begin
       end if;
     end if;
   end process OMIT_PROBLEM_WITH_MISS_REF;
-    
+
+
   EXT_TRIGGER_1 : edge_to_pulse
     port map (
       clock  => TDC_CLK,
@@ -1856,14 +2147,35 @@ begin
       end if;
     end if;
   end process SYNCH_WITHC_TDC_CLK;
+  
   a_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
   b_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
   c_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
   d_trigg          <= trigger_to_tdc_i;--fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
-  A_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod
-  B_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod
-  C_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod
-  D_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod
+
+
+  BLINK_TDC_DIODS_ON_TRBv2c : process (CLK, reset_i)
+  begin  
+    if rising_edge(CLK) then
+      if reset_i = '1' then
+        A_TDC_POWERUP  <=  '1';       --in trbv2c this is a diod in trbv2b real!!!
+        B_TDC_POWERUP  <=  '1';       -- -//-
+        C_TDC_POWERUP  <=  '1';       -- -//-
+        D_TDC_POWERUP  <=  '1';       -- -//-
+      elsif rw_register_i(3)(8) = '0'  then  --trbv2b deafoult '0'
+        A_TDC_POWERUP  <=  '1';      
+        B_TDC_POWERUP  <=  '1';      
+        C_TDC_POWERUP  <=  '1';      
+        D_TDC_POWERUP  <=  '1';      
+      else
+        A_TDC_POWERUP  <=  not r_register_i(19)(7);       
+        B_TDC_POWERUP  <=  not r_register_i(19)(9);      
+        C_TDC_POWERUP  <=  not r_register_i(19)(11);      
+        D_TDC_POWERUP  <=  not r_register_i(19)(13);       
+      end if;
+    end if;
+  end process BLINK_TDC_DIODS_ON_TRBv2c;
+  
   DBAD         <= lvl1_busy_i;
   DINT         <= TDC_CLK;--tdc_data_valid_i;
   DWAIT        <= addon_clk;
@@ -1884,15 +2196,15 @@ begin
     if rising_edge(CLK) then
       if reset_i = '1' then            
         trigger_miss_match <= '0';
-      elsif lvl1_trigger_i  = '1' and (ref_time_counter /= lvl1_trigger_tag_i) then
+      elsif lvl1_trigger_i  = '1' and (ref_time_counter /= lvl1_trigger_tag_i(7 downto 0)) then
         trigger_miss_match <= '1';
-      elsif fast_ref_trigger_pulse = '1' and (ref_time_counter /= lvl1_trigger_tag_i) then
+      elsif fast_ref_trigger_pulse = '1' and (ref_time_counter /= lvl1_trigger_tag_i(7 downto 0)) then
         trigger_miss_match <= '0'; --trigger_miss_match;
       end if;
     end if;
   end process CHECK_REF_AND_DIGITAL_TRIGGER;
   
-  fpga_register_0a_i(15 downto 0) <= ref_time_counter & lvl1_trigger_tag_i;
+  fpga_register_0a_i(15 downto 0) <= ref_time_counter & lvl1_trigger_tag_i(7 downto 0);
   fpga_register_0a_i(30) <= not_hades_trigger;
   fpga_register_0a_i(31) <= fast_ref_trigger;
 -----------------------------------------------------------------------------
@@ -1908,42 +2220,65 @@ begin
           external_data_in_i <= dsp_data_out_i;
         elsif external_mode_i(7 downto 0) = x"02" then
           external_data_in_i <= sdram_data_out_i;
---                  elsif external_mode_i(7 downto 0) = x"03" then
---            external_data_in_i <= x"add000" & ADO_TTL(42 downto 35);
         else
           external_data_in_i <= x"0000"&external_mode_i;
         end if;
       end if;
   end process MULTIPLEX_DATA_TO_ETRAX;
---       ADO_TTL(42 downto 35) <= (others => 'Z');
---       ADO_TTL(34 downto 19) <= external_address_i(15 downto 0);
---       ADO_TTL(18 downto 11) <= external_data_out_i(7 downto 0);
---       ADO_TTL(10)           <= external_mode_i(15);
---       ADO_TTL(9) <= '1' when external_mode_i(7 downto 0) = x"03" and external_ack_i = '1' else '0';
 --       dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
---  --     external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or ADO_TTL(12);
---       external_valid_i <= ADO_TTL(8);
---       ADO_TTL(8) <= 'Z';
-
+  --\@@##$$%%^^&&**(((  put dsp_strobe to the dsp interface (extarnal mode has
+  -- to be there)
+--       sdram_strobe_i <= '1' when external_mode_i(7 downto 0) = x"02" and external_ack_i = '1' else '0';  
+--       external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or ADO_TTL(12);
+-------------------------------------------------------------------------------
+-- sfp interface
+-------------------------------------------------------------------------------
+  THE_SFP_INTERFACE: Sfp_Interface
+     generic map (
+      TEMP_START_ADD  =>  "01100000",
+      TEMP_STOP_ADD   =>  "01100001",
+      OP_PWR_START_ADD => "01101000",
+      OP_PWR_STOP_ADD =>  "01101001",
+      DEVICE_ADD      =>  "10100010",
+      I2C_SPEED       =>  "11111101"
+      )
+    port map (
+      CLK_IN           => clk,
+      RST_IN           => reset_i,
+      EN_SFP_INTERFACE => '1',
+      TEMP_DATA_OUT    => r_register_i(20)(15 downto 0),
+      OPT_DATA_OUT     => r_register_i(20)(31 downto 16),
+      SCL              => SCL,
+      SDA              => SDA,
+      BIT_CTRL_DEBUG   => open,
+      BYTE_CTRL_DEBUG  => r_register_i(21)(15 downto 0)
+      );
+  
 -------------------------------------------------------------------------------
 -- etrax interface
 -------------------------------------------------------------------------------
   ETRAX_IRQ    <= '1';
+
+  
   ETRAX_INTERFACE_LOGIC : etrax_interfacev2
     generic map (
       ENABLE_DMA => ENABLE_DMA,
       RW_SYSTEM => RW_SYSTEM,
       RW_REGISTERS_NUMBER => RW_REGISTERS_NUMBER,
-      R_REGISTERS_NUMBER => R_REGISTERS_NUMBER
+      R_REGISTERS_NUMBER => R_REGISTERS_NUMBER,
+      TRBNET_ENABLE => TRBNET_ENABLE
       )
     port map (
       CLK                    => CLK,
       RESET                  => reset_i,
       DATA_BUS               => tdc_data_out_i,
       ETRAX_DATA_BUS_B       => FS_PB,
-      ETRAX_DATA_BUS_B_17       => FS_PB_17,
+      ETRAX_DATA_BUS_B_17    => FS_PB_17,
       ETRAX_DATA_BUS_C       => FS_PC,
       ETRAX_DATA_BUS_E       => open,
+      IPU_READY_IN           => ipu_read_out_i,
+      IPU_DATAREADY_OUT      => ipu_dataready_in_i,
+      IPU_DATA_OUT           => ipu_data_in_i,
       DATA_VALID             => tdc_data_valid_i,
       ETRAX_BUS_BUSY         => etrax_bus_busy_i,
       ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
@@ -1959,10 +2294,20 @@ begin
       EXTERNAL_ACK           => external_ack_i,
       EXTERNAL_VALID         => external_valid_i,
       EXTERNAL_MODE          => external_mode_i,
-      RW_REGISTER            => rw_register_i,
-      R_REGISTER             => r_register_i,
-      LVL2_VALID             => lvl2_trigger_code_i(3)
+      RW_REGISTER            => rw_register_vector,
+      R_REGISTER             => r_register_vector,
+      LVL2_VALID             => lvl2_trigger_code_i(3),
+      TRB_LVL2_BUSY          => lvl2_busy_i
       );
+
+  REWRITE_R_REGISTER: for i in 1 to R_REGISTERS_NUMBER generate
+    r_register_vector(32*i-1 downto 32*(i-1)) <= r_register_i(i-1);
+  end generate REWRITE_R_REGISTER;
+
+  REWRITE_RW_REGISTER: for i in 1 to RW_REGISTERS_NUMBER generate
+    rw_register_i(i-1) <= rw_register_vector(32*i-1 downto 32*(i-1));
+  end generate REWRITE_RW_REGISTER;
+  
   fpga_register_01_i <= tdc_register_00_i;
   fpga_register_02_i <= tdc_register_01_i;
   fpga_register_03_i <= tdc_register_02_i;
@@ -1974,81 +2319,33 @@ begin
 --  fpga_register_0b_i <= FS_PB_17&lvl2_trigger_code_i(3)& tdc_data_valid_i& '0' & lvl1_trigger_code_i & lvl1_trigger_tag_i & x"00" & lvl1_trigger_tag_i;
   fpga_register_0c_i <= trigger_miss_match & opt_busy_lvl1_or_lvl2 & TLK_RX_DV & TLK_RX_ER & x"000"& TLK_RXD;
 --  fpga_register_0d_i <= dtu_debug_00_i;--stat_init_buffer_i;
-  r_register_i((0+1)*32-1 downto 0*32) <= x"aaaabbbb";
-  r_register_i((1+1)*32-1 downto 1*32) <= tdc_register_00_i;
-  r_register_i((2+1)*32-1 downto 2*32) <= tdc_register_01_i;
-  r_register_i((3+1)*32-1 downto 3*32) <= tdc_register_02_i;
-  r_register_i((4+1)*32-1 downto 4*32) <= tdc_register_03_i;
-  r_register_i((5+1)*32-1 downto 5*32) <= fpga_register_05_i;
-  r_register_i((6+1)*32-1 downto 6*32) <= conv_std_logic_vector(VERSION_NUMBER_TIME,32);
-  r_register_i((7+1)*32-1 downto 7*32) <= x"abcd0001";--fpga_register_07_i;
-  r_register_i((8+1)*32-1 downto 8*32) <= fpga_register_08_i;
-  r_register_i((9+1)*32-1 downto 9*32) <= fpga_register_09_i;
-  r_register_i((10+1)*32-1 downto 10*32) <= fpga_register_0a_i;
-  r_register_i((11+1)*32-1 downto 11*32) <= fpga_register_0b_i;
-  r_register_i((12+1)*32-1 downto 12*32) <= fpga_register_0c_i;
-  r_register_i((13+1)*32-1 downto 13*32) <= fpga_register_0d_i;
+  r_register_i(0) <= x"aaaabbbb";
+  r_register_i(1) <= tdc_register_00_i;
+  r_register_i(2) <= tdc_register_01_i;
+  r_register_i(3) <= tdc_register_02_i;
+  r_register_i(4) <= tdc_register_03_i;
+  r_register_i(5) <= fpga_register_05_i;
+  r_register_i(6) <= conv_std_logic_vector(VERSION_NUMBER_TIME,32);
+  r_register_i(7) <= x"abcd0001";--fpga_register_07_i;
+  r_register_i(8) <= fpga_register_08_i;
+  r_register_i(9) <= fpga_register_09_i;
+  r_register_i(10) <= fpga_register_0a_i;
+  r_register_i(11) <= fpga_register_0b_i;
+  r_register_i(12) <= fpga_register_0c_i;
+  r_register_i(13) <= fpga_register_0d_i;
 --  r_register_i((14+1)*32-1 downto 14*32) <= x"abcd0002";
-  fpga_register_06_i <= rw_register_i((0+1)*32-1 downto 0*32);
-  fpga_register_07_i <= rw_register_i((1+1)*32-1 downto 1*32);
-  fpga_register_0e_i <= rw_register_i((2+1)*32-1 downto 2*32);
-  
--------------------------------------------------------------------------------
--- tlk
--------------------------------------------------------------------------------
---  DGOOD        <= lvl2_busy_i;
---   TLK_TXD    <= x"abcd";
---   TLK_TX_ER  <= '0';
---   SFP_TX_DIS   <= fpga_register_06_i(15);
---     TLK_LOOPEN  <= '0';
---   TLK_LCKREFN <= '1';
---   TLK_ENABLE  <= '1';
---   TLK_PRBSEN  <= '0';
---   TLK_RX_CLK_BUFR: BUFR
---     port map(
---       CE => '1',
---       CLR => '0',
---       I => TLK_RX_CLK,
---       O => tlk_rx_clk_r(0)
---       );
---   TLK_CLK_BUFR: BUFR
---     port map(
---       CE => '1',
---       CLR => '0',
---       I => TLK_CLK,
---       O => tlk_clk_r(0)
---       ); 
---          tlk_interface_logic: tlk_interface 
---          port map (
---            VIRT_CLK     => CLK,
---            ENABLE       => TLK_ENABLE,
---            LCKREFN      => TLK_LCKREFN,
---            LOOPEN       => TLK_LOOPEN,
---            PRBSEN       => TLK_PRBSEN,
---            RX_CLK       => tlk_rx_clk_r(0),
---            RX_DV        => TLK_RX_DV,
---            RX_ER        => TLK_RX_ER,
---            TLK_CLK      => tlk_clk_r(0),
---            TLK_RXD      => TLK_RXD,
---            TLK_TXD      => TLK_TXD,
---            TX_EN        => open,--TLK_TX_EN,
---            TX_ER        => open,--TLK_TX_ER,
---            RESET_VIRT   => reset_i,
---            TLK_REGISTER_00 => tlk_register_00_i,
---            TLK_REGISTER_01 => tlk_register_01_i,
---            SFP_LOS => SFP_LOS,
---            TX_DIS => open--SFP_TX_DIS
---            );
---   --      TLK_LCKREFN <= fpga_register_06_i(15);
---    --     TLK_TXD <= x"abcd";
---         TLK_TX_EN <= '0';
---         TLK_TX_ER <= '0';
---        fpga_register_08_i(4) <= SFP_LOS;
+  fpga_register_06_i <= rw_register_i(0);
+  fpga_register_07_i <= rw_register_i(1);
+  fpga_register_0e_i <= rw_register_i(2);
 
-    
+
+  
 -------------------------------------------------------------------------------
--- dsp
+-- dsp -- remember about offset for 
+-- adressing internal registers (0x10000000). DSP is foreseen
+-- for multiprocessor environment  
 -------------------------------------------------------------------------------
+  
   DSP_EN: if DSP_INT_ENABLE = 1 generate
     DSP_DATA_REGISTER: process (CLK, reset_i)
     begin  -- process DSP_DATA_REGISTER
@@ -2108,6 +2405,7 @@ begin
 -------------------------------------------------------------------------------
 -- sdram interface
 -------------------------------------------------------------------------------
+  
     SDRAM_EN: if SDRAM_INT_ENABLE = 1 generate
       SDRAM_INTERFACE_LOGIC: sdram_interface
         port map (
@@ -2141,6 +2439,7 @@ begin
 -------------------------------------------------------------------------------
 -- opt dtu
 -------------------------------------------------------------------------------
+  
   CTU_DTU_OPT_EN: if DTU_ENABLE = 2 generate
 
     TLK_TX_ER  <= '0';
@@ -2180,10 +2479,10 @@ begin
           OPT_DATA_SEND          => TLK_TX_EN,
           LVL1_TRIGGER           => lvl1_trigger_i,
           LVL1_TRIGGER_CODE      => lvl1_trigger_code_i,
-          LVL1_TRIGGER_TAG       => lvl1_trigger_tag_i,
+          LVL1_TRIGGER_TAG       => lvl1_trigger_tag_i(7 downto 0),
           LVL2_TRIGGER           => lvl2_trigger_i,
           LVL2_TRIGGER_CODE      => lvl2_trigger_code_i(3),
-          LVL2_TRIGGER_TAG       => lvl2_trigger_tag_i,
+          LVL2_TRIGGER_TAG       => lvl2_trigger_tag_i(7 downto 0),
           LVL1_BUSY              => busy_or_error,
           LVL2_BUSY              => lvl2_busy_i,
           OPT_DTU_DEBUG_REGISTER_00 => fpga_register_0d_i,
@@ -2204,7 +2503,11 @@ begin
 
     end generate DTU_EN;
     
-    CTU_EN: if TRBV2_TYPE =4 or TRBV2_TYPE =5 generate
+---------------------------------------------------------------------------
+-- optical ctu 
+---------------------------------------------------------------------------
+    
+    CTU_EN: if (TRBV2_TYPE =4 or TRBV2_TYPE =5) and TRBNET_ENABLE = 0 generate
       CTU_OPT_INST: optical_ctu
         port map (
             CLK               => CLK,
@@ -2218,15 +2521,16 @@ begin
             OPT_DATA_SEND     => TLK_TX_EN,
             LVL1_TRIGGER      => lvl1_trigger_i,
             LVL1_CODE         => lvl1_trigger_code_i,
-            LVL1_TAG          => lvl1_trigger_tag_i,
+            LVL1_TAG          => lvl1_trigger_tag_i(7 downto 0),
             LVL1_BUSY         => opt_lvl1_busy_i,
             LVL2_TRIGGER      => lvl2_trigger_i,
             LVL2_CODE         => lvl2_trigger_code_i(3),
-            LVL2_TAG          => lvl2_trigger_tag_i,
+            LVL2_TAG          => lvl2_trigger_tag_i(7 downto 0),
             LVL2_BUSY         => opt_lvl2_busy_i,
             OPT_CTU_DEBUG_00     => fpga_register_0d_i,
             OPT_CTU_DEBUG_01     => fpga_register_0b_i
             );
+      
     ADO_TTL(0) <= TLK_RX_ER;
     ADO_TTL(1) <= TLK_RX_DV;
     ADO_TTL(5 downto 2) <= TLK_RXD(15 downto 12);
@@ -2254,13 +2558,13 @@ begin
             ext_lvl1_trigger_i <= '0';
             lvl1_trigger_i <= '0';
             lvl1_trigger_code_i <= x"1";
-            lvl1_trigger_tag_i <= x"00";
+            lvl1_trigger_tag_i(7 downto 0) <= x"00";
 
           else
             ext_lvl1_trigger_i <= (not_hades_trigger and fpga_register_06_i(7) and (not(opt_busy_lvl1_or_lvl2))) or fpga_register_0e_i(0);
             lvl1_trigger_i <= ext_lvl1_trigger_pulse;
             lvl1_trigger_code_i <= x"1";
-            lvl1_trigger_tag_i <= ext_tag;
+            lvl1_trigger_tag_i(7 downto 0) <= ext_tag;
 
           end if;
         end if;
@@ -2304,7 +2608,7 @@ begin
 
       fpga_register_09_i(7 downto 0) <= ext_tag;
       fpga_register_09_i(31) <= opt_lvl1_busy_i;
-      fpga_register_09_i(15 downto 8) <= lvl2_trigger_tag_i;
+      fpga_register_09_i(15 downto 8) <= lvl2_trigger_tag_i(7 downto 0);
                                          
         
     AUTO_LVL2 : edge_to_pulse
@@ -2320,7 +2624,7 @@ begin
         port map (
           CLK       => CLK,
           RESET     => reset_i,
-          COUNT_OUT => lvl2_trigger_tag_i,
+          COUNT_OUT => lvl2_trigger_tag_i(7 downto 0),
           UP_IN     => lvl2_trigger_i,
           DOWN_IN   => '0');
       
@@ -2330,10 +2634,11 @@ begin
 
   end generate CTU_DTU_OPT_EN;
 
-  -----------------------------------------------------------------------------
-  -- dummy tlk for ise and not only :)
-  -----------------------------------------------------------------------------
-  TLK_ISE: if DTU_ENABLE=0 generate
+-----------------------------------------------------------------------------
+-- tlk interface
+-----------------------------------------------------------------------------
+  
+  TLK_ISE: if DTU_ENABLE=0 and TRBV2_TYPE < 4 and TRBNET_ENABLE = 0 generate
     TLK_TX_ER  <= '0';
     SFP_TX_DIS   <= '0';--fpga_register_06_i(15);
     TLK_LOOPEN  <= '0';
@@ -2347,7 +2652,6 @@ begin
     rx_k_i <= x"0" & "000" & TLK_RX_DV;
     tlk_rxd_i <= x"000000000000" &  TLK_RXD;
     TLK_TXD <= tlk_txd_i(15 downto 0);
-
     
     TLK_RX_CLK_BUFR: BUFR
       port map(
@@ -2391,8 +2695,8 @@ begin
           MED_READ_IN        => med_read_in_i,
           MED_PACKET_NUM_IN  => med_packet_num_in_i,
           MED_PACKET_NUM_OUT => med_packet_num_out_i,
-          MED_STAT_OP        => med_stat_op_i,
-          MED_CTRL_OP        => med_ctrl_op_i,
+          MED_STAT_OP        => med_stat_op_in_i,
+          MED_CTRL_OP        => med_ctrl_op_out_i,
           LINK_DEBUG         => link_debug_i,
           TX_DIS             => open,
           SFP_INP_N          => x"00",
@@ -2400,7 +2704,8 @@ begin
           SFP_OUT_N          => open,
           SFP_OUT_P          => open
           );
-    DGOOD <= med_stat_op_i(9);
+    
+    DGOOD <= med_stat_op_in_i(9);
     media_status_i(0) <= sfp_los_vect(0);
     fpga_register_0b_i(15 downto 0) <= media_status_i;
     fpga_register_0d_i <= link_debug_i;
@@ -2408,7 +2713,8 @@ begin
 
   
 -------------------------------------------------------------------------------
--- dtu 
+-- dtu - there has to be an GP-AddOn with correct configuration see GP_AddOn
+-- directory (not available now). Old HADES bus saved for any case.
 -------------------------------------------------------------------------------
     DTU_INT_ENABLE: if DTU_ENABLE = 1 generate
       DTU_INT: dtu_interface
@@ -2422,7 +2728,7 @@ begin
               LVL1_BUSY_BUS         => ADO_TTL(7),
               LVL1_TRIGGER          => lvl1_trigger_i,
               LVL1_CODE             => lvl1_trigger_code_i,
-              LVL1_TAG              => lvl1_trigger_tag_i,
+              LVL1_TAG              => lvl1_trigger_tag_i(7 downto 0),
               LVL1_BUSY             => lvl1_busy_i,--'0',
               LVL2_TRIGGER_BUS      => ADO_TTL(8),
               LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
@@ -2431,7 +2737,7 @@ begin
               LVL2_BUSY_BUS         => ADO_TTL(15),
               LVL2_TRIGGER          => lvl2_trigger_i,
               LVL2_CODE             => lvl2_trigger_code_i,
-              LVL2_TAG              => lvl2_trigger_tag_i,
+              LVL2_TAG              => lvl2_trigger_tag_i(7 downto 0),
               LVL2_BUSY             => lvl2_busy_i,
               LVL2_TRB_ACK          => lvl2_readout_completed_i,--lvl2_trb_ack_i,
               DTU_DEBUG_00          => dtu_debug_00_i);
@@ -2443,7 +2749,8 @@ begin
     end generate DTU_INT_ENABLE;
 
 -------------------------------------------------------------------------------
--- ctu
+-- ctu - there has to be an GP-AddOn with correct configuration see GP_AddOn
+-- directory (not available now). Old HADES bus Saved for any case.
 -------------------------------------------------------------------------------
     CTU_INT_ENABLE: if CTU_ENABLE = 1 generate
       lvl2_trigger_code_i(3) <= '0';
@@ -2455,7 +2762,7 @@ begin
             RESET            => reset_i,
             LVL1_TRIGG       => ADO_TTL(7 downto 0),
             LVL1_START       => lvl1_trigger_i,
-            LVL1_TAG         => lvl1_trigger_tag_i,
+            LVL1_TAG         => lvl1_trigger_tag_i(7 downto 0),
             LVL1_CODE        => lvl1_trigger_code_i,
             LVL1_BUSY        => lvl1_busy_i,
             LVL2_TRIGG       => "00",     --MU
@@ -2470,7 +2777,8 @@ begin
 
   
 --------------------------------------------------------------------------
--- scalers
+-- scalers - there has to be an GP-AddOn with correct configuration see GP_AddOn
+-- directory (not available now).
 -------------------------------------------------------------------------
   SCALERS_ON_TTL_ENABLE: if SCALERS_ENABLE = 1 generate
     SCALER: for ttl_line in 0 to 7 generate
@@ -2492,7 +2800,7 @@ begin
 
   
 --------------------------------------------------------------------------
--- others
+-- others --simple test for clock quality (osciloscope)
 --------------------------------------------------------------------------
 
   COUNTER_FOR_CLOCK_CHECK: process (CLK, reset_i)

diff --git a/trb_v2b_fpga_syn.prj b/trb_v2b_fpga_syn.prj
index e0784027beb87c81baca286b455089f3ffcebd35..fd305054c724f16468230537889a2eedea288a72 100644 (file)
--- a/trb_v2b_fpga_syn.prj
+++ b/trb_v2b_fpga_syn.prj
@@ -3,15 +3,25 @@
 
 
 #add_file options
+#$$$$$$$$$$$$$$$$$$$$$$$$$$$$sfp temp and opt power$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#
+
+
+add_file -vhdl -lib work "sfp_interaface.vhd"
+add_file -vhdl -lib work "bit_controller.vhd" 
+add_file -vhdl -lib work "byte_ctrl.vhd"
+add_file -vhdl -lib work "cahit_divider.vhd"
+
+#$$$$$$$$$$$$$$$$$$$$$$$$$$$$trb$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#
+
+add_file -vhdl -lib work "cts.vhd"
+add_file -vhdl -lib work "cts_fifo.vhd"
+
 add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "~/trbnet/optical_link/media_interface.vhd"
-add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_8bit.vhd"
-add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_16bit.vhd"
-add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_32bit.vhd"
+add_file -vhdl -lib work "up_down_counter.vhd"
 add_file -vhdl -lib work "etrax_interface.vhd"
 add_file -vhdl -lib work "etrax_interfacev2.vhd"
 add_file -vhdl -lib work "f_divider.vhd"
-add_file -vhdl -lib work "tdc_interface.vhd"
+add_file -vhdl -lib work "tdc_interfacev2.vhd"
 add_file -vhdl -lib work "trb_v2b_fpga.vhd"
 add_file -vhdl -lib work "dtu_interface.vhd"
 add_file -vhdl -lib work "dsp_interface.vhd"
@@ -24,51 +34,97 @@ add_file -vhdl -lib work "vulom_interface.vhd"
 add_file -vhdl -lib work "~/trbnet/optical_link/flexi_PCS_synch.vhd"
 add_file -vhdl -lib work "~/trbnet/optical_link/flexi_PCS_channel_synch.vhd"
 add_file -vhdl -lib work "trbv2_cross_clk.vhd"
-add_file -vhdl -lib work "trbv2_link_fifo.vho"
-add_file -vhdl -lib work "~/trbnet/optical_link/"
+add_file -vhdl -lib work "trbv2_link_fifo.vhd"
+add_file -vhdl -lib work "DCM_100MHz_to_200MHz.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../trbnet/optical_link/media_interface.vhd"
+add_file -vhdl -lib work "../trbnet/optical_link/flexi_PCS_synch.vhd"
+add_file -vhdl -lib work "../trbnet/optical_link/flexi_PCS_channel_synch.vhd"
+add_file -vhdl -lib work "header_add_data_fifo_4kW.vhd"
+add_file -vhdl -lib work "lvl1_buffer_32kW.vhd"
+#######cts first level components #1 second level #2-- ....###########
+#0
+
+add_file -vhdl -lib work "~/trbnet/trb_net16_med_tlk.vhd"
+#1
+add_file -vhdl -lib work "~/trbnet/trb_net16_endpoint_hades_full.vhd"
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_ipudata.vhd"
+    add_file -vhdl -lib work "~/trbnet/trb_net16_trigger.vhd"
+
+add_file -vhdl -lib work "~/trbnet/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd"
+add_file -vhdl -lib work "~/trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "~/trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "~/trbnet/trb_net16_endpoint_hades_cts.vhd"
+#1
+  add_file -vhdl -lib work "~/trbnet/trb_net16_api_base.vhd"
+#$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_term.vhd"
+    add_file -vhdl -lib work "~/trbnet/trb_net16_sbuf.vhd"
+#3----
+       ###@@@trb_net_sbuf.vhd
+      add_file -vhdl -lib work "~/trbnet/trb_net_sbuf.vhd"
+      add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/trb_net16_fifo_arch.vhd" 
+      #trb_net16_fifo
+#4------
+       add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/xilinx_fifo_18x1k.vhd"
+       add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/xilinx_fifo_18x16.vhd"
+       add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/xilinx_fifo_18x32.vhd"
+       add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/xilinx_fifo_18x64.vhd"
+       add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/xilinx_fifo_18x1k_datacount.vhd"
+       add_file -vhdl -lib work "~/trbnet/xilinx/xilinx_fifo_lut.vhd"
+#5---------
+       add_file -vhdl -lib work "~/trbnet/xilinx/shift_lut_x16.vhd"
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_dummy_fifo.vhd"
+#3----
+      add_file -vhdl -lib work "~/trbnet/trb_net_dummy_fifo.vhd"       
+
+#1
+  add_file -vhdl -lib work "~/trbnet/trb_net16_iobuf.vhd"
+#$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$#
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_ibuf.vhd"
+#3----
+      ###@@@trb_net16_fifo.vhd 
+      ###@@@trb_net16_sbuf.vhd
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_term_ibuf.vhd"
+#3----
+      ###@@@trb_net16_sbuf.vhd
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_obuf.vhd"
+#3----
+      ###@@@trb_net16_sbuf.vhd
+      add_file -vhdl -lib work "~/trbnet/trb_net_CRC.vhd"
+#2--
+    add_file -vhdl -lib work "~/trbnet/trb_net16_obuf_nodata.vhd"
+#1    
+  add_file -vhdl -lib work "~/trbnet/trb_net16_term_buf.vhd"
+#1
+  add_file -vhdl -lib work "~/trbnet/trb_net16_io_multiplexer.vhd"
+#2--
+    ###@@@trb_net16_sbuf.vhd
+    add_file -vhdl -lib work "~/trbnet/trb_net_priority_arbiter.vhd"
+#3----
+      add_file -vhdl -lib work "~/trbnet/trb_net_priority_encoder.vhd"
+#1      
+  add_file -vhdl -lib work "~/trbnet/trb_net16_regIO.vhd"
+#2--
+    add_file -vhdl -lib work "~/trbnet/basics/rom_16x8.vhd"
+    add_file -vhdl -lib work "~/trbnet/trb_net_pattern_gen.vhd"
+    add_file -vhdl -lib work "~/trbnet/trb_net16_addresses.vhd"
+#3----
+      add_file -vhdl -lib work "~/trbnet/basics/ram_16x16_dp.vhd"
+#1
+  add_file -vhdl -lib work "~/trbnet/trb_net_onewire_listener.vhd"
+#2--
+    add_file -vhdl -lib work "~/trbnet/basics/signal_sync.vhd"
 
 
 #add_file -vhdl -lib work ""
 
-add_file -vhdl -lib work "~/trbnet/trb_net16_med_tlk"
-add_file -vhdl -lib work "~/trbnet/trb_net_rom_16x8.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_ram_dp.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_ram.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_ram_16x8_dp.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_hub_func.vhd"
-#add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/lattice_scm_fifo_18x1k.vhd"
-#add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/lattice_scm_fifo_18x16.vhd"
-#add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/lattice_scm_fifo_18x32.vhd"
-#add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/lattice_scm_fifo_18x64.vhd"
-add_file -vhdl -lib work "~/trbnet/xilinx/virtex4/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_fifo.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "~/trbnet/xilinx/shift_lut_x16.vhd"
-add_file -vhdl -lib work "~/trbnet/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_hub_logic.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_hub_func.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_endpoint_0_trg_1_api.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_med_tlk.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "~/trbnet/trb_net16_endpoint_1_trg_0_api.vhd"
 
 
 #add_file -constraint "trb_v2a_fpga_syn.sdc"

diff --git a/trb_v2b_fpga_tb.vhd b/trb_v2b_fpga_tb.vhd
index 2344741a65a1c4ca35169dc4aea5d30ae275f33e..06d3d57c9a84a7e37fa34485a0c07c92cc1fc1e3 100644 (file)
--- a/trb_v2b_fpga_tb.vhd
+++ b/trb_v2b_fpga_tb.vhd
@@ -8,8 +8,9 @@ use UNISIM.VComponents.all;
 
 ENTITY trb_v2b_fpga_tb IS
 END trb_v2b_fpga_tb;
-
-ARCHITECTURE behavior OF trb_v2b_fpga_tb IS 
+--simulate at lest for 100 us
+ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
+  
   component trb_v2b_fpga
     port (
       VIRT_CLK        : in    std_logic;
@@ -20,13 +21,10 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       DINT            : out   std_logic;
       DWAIT           : out   std_logic;
       A_RESERVED      : in    std_logic;
-      A_TEMP          : in    std_logic;
       B_RESERVED      : in    std_logic;
-      B_TEMP          : in    std_logic;
       C_RESERVED      : in    std_logic;
-      C_TEMP          : in    std_logic;
       D_RESERVED      : in    std_logic;
-      D_TEMP          : in    std_logic;
+      TEMP_SENS       : inout std_logic_vector(3 downto 0);
        VIR_TRIG        : in    std_logic;
        VIR_TRIGB       : in    std_logic;
       A_TDC_ERROR     : in    std_logic;
@@ -166,7 +164,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       SFP_LOS         : in    std_logic;
       SFP_TX_DIS      : out   std_logic;
       SFP_TX_FAULT    : in    std_logic;
-      ADO_LV          : in    std_logic_vector(51 downto 0);
+      ADO_LVDS_IN          : in    std_logic_vector(51 downto 0);
+      ADO_LVDS_OUT                    : out std_logic_vector(9 downto 0);
       ADDON_TO_TRB_CLKINN       : in std_logic;
      ADDON_TO_TRB_CLKINP       : in std_logic;
       ADO_TTL         : inout std_logic_vector(46 downto 0);
@@ -177,6 +176,172 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       VIRT_TMS        : out   std_logic;
       VIRT_TRST       : out   std_logic);
   end component;
+    component trb_v2b_fpga_endpoint
+    port (
+      VIRT_CLK        : in    std_logic;
+      VIRT_CLKB       : in    std_logic;
+      RESET_VIRT      : in    std_logic;
+      DBAD            : out   std_logic;
+      DGOOD           : out   std_logic;
+      DINT            : out   std_logic;
+      DWAIT           : out   std_logic;
+      A_RESERVED      : in    std_logic;
+      B_RESERVED      : in    std_logic;
+      C_RESERVED      : in    std_logic;
+      D_RESERVED      : in    std_logic;
+      TEMP_SENS       : inout std_logic_vector(3 downto 0);
+       VIR_TRIG        : in    std_logic;
+       VIR_TRIGB       : in    std_logic;
+      A_TDC_ERROR     : in    std_logic;
+      B_TDC_ERROR     : in    std_logic;
+      C_TDC_ERROR     : in    std_logic;
+      D_TDC_ERROR     : in    std_logic;
+      A_TDC_POWERUP   : out   std_logic;
+      B_TDC_POWERUP   : out   std_logic;
+      C_TDC_POWERUP   : out   std_logic;
+      D_TDC_POWERUP   : out   std_logic;
+      TOKEN_IN        : in    std_logic;
+      TOKEN_OUT       : out   std_logic;
+      C_TOKEN_OUT_TTL : in    std_logic;
+      GET_DATA        : out   std_logic;
+      A_DATA_READY    : in    std_logic;
+      B_DATA_READY    : in    std_logic;
+      C_DATA_READY    : in    std_logic;
+      D_DATA_READY    : in    std_logic;
+      REF_TDC_CLK     : in    std_logic;
+      REF_TDC_CLKB    : in    std_logic;
+      A_TDC_BU_RESET  : out   std_logic;
+      A_TDC_BU_RESETB : out   std_logic;
+      A_TDC_EV_RESET  : out   std_logic;
+      A_TDC_EV_RESETB : out   std_logic;
+      B_TDC_BU_RESET  : out   std_logic;
+      B_TDC_BU_RESETB : out   std_logic;
+      B_TDC_EV_RESET  : out   std_logic;
+      B_TDC_EV_RESETB : out   std_logic;
+      C_TDC_BU_RESET  : out   std_logic;
+      C_TDC_BU_RESETB : out   std_logic;
+      C_TDC_EV_RESET  : out   std_logic;
+      C_TDC_EV_RESETB : out   std_logic;
+      D_TDC_BU_RESET  : out   std_logic;
+      D_TDC_BU_RESETB : out   std_logic;
+      D_TDC_EV_RESET  : out   std_logic;
+      D_TDC_EV_RESETB : out   std_logic;
+      TDC_OUT         : in    std_logic_vector (31 downto 0);
+      TDC_RESET       : out   std_logic;
+      A_TRIGGER       : out   std_logic;
+      A_TRIGGERB      : out   std_logic;
+      B_TRIGGER       : out   std_logic;
+      B_TRIGGERB      : out   std_logic;
+      C_TRIGGER       : out   std_logic;
+      C_TRIGGERB      : out   std_logic;
+      D_TRIGGER       : out   std_logic;
+      D_TRIGGERB      : out   std_logic;
+      FS_PB           : inout   std_logic_vector (16 downto 0);
+      FS_PB_17           : in   std_logic;
+      FS_PC           : inout std_logic_vector (17 downto 0);
+      ETRAX_IRQ       : out   std_logic;
+      A_SCK           : out   std_logic;
+      A_SCKB          : out   std_logic;
+      A_SDI           : in    std_logic;
+      A_SDIB          : in    std_logic;
+      A_SDO           : out   std_logic;
+      A_SDOB          : out   std_logic;
+      A_CSB           : out   std_logic;
+      A_CS            : out   std_logic;
+      B_SCK           : out   std_logic;
+      B_SCKB          : out   std_logic;
+      B_SDI           : in    std_logic;
+      B_SDIB          : in    std_logic;
+      B_SDO           : out   std_logic;
+      B_SDOB          : out   std_logic;
+      B_CSB           : out   std_logic;
+      B_CS            : out   std_logic;
+      C_SCK           : out   std_logic;
+      C_SCKB          : out   std_logic;
+      C_SDI           : in    std_logic;
+      C_SDIB          : in    std_logic;
+      C_SDO           : out   std_logic;
+      C_SDOB          : out   std_logic;
+      C_CSB           : out   std_logic;
+      C_CS            : out   std_logic;
+      D_SCK           : out   std_logic;
+      D_SCKB          : out   std_logic;
+      D_SDI           : in    std_logic;
+      D_SDIB          : in    std_logic;
+      D_SDO           : out   std_logic;
+      D_SDOB          : out   std_logic;
+      D_CSB           : out   std_logic;
+      D_CS            : out   std_logic;
+      A_TEST1         : out   std_logic;
+      A_TEST1B        : out   std_logic;
+      A_TEST2         : out   std_logic;
+      A_TEST2B        : out   std_logic;
+      B_TEST1         : out   std_logic;
+      B_TEST1B        : out   std_logic;
+      B_TEST2         : out   std_logic;
+      B_TEST2B        : out   std_logic;
+      C_TEST1         : out   std_logic;
+      C_TEST1B        : out   std_logic;
+      C_TEST2         : out   std_logic;
+      C_TEST2B        : out   std_logic;
+      D_TEST1         : out   std_logic;
+      D_TEST1B        : out   std_logic;
+      D_TEST2         : out   std_logic;
+      D_TEST2B        : out   std_logic;
+       DSPADDR         : out   std_logic_vector (31 downto 0);
+       DSPDAT          : inout std_logic_vector (31 downto 0);
+       DSP_ACK         : in    std_logic;
+       DSP_BM          : inout std_logic;
+       DSP_BMS         : out   std_logic;
+       DSP_BOFF        : out   std_logic;
+       DSP_BRST        : inout std_logic;
+       DSP_HBG         : in    std_logic;
+       DSP_HBR         : out   std_logic;
+       DSP_IRQ         : out   std_logic_vector (3 downto 0);
+       DSP_RD          : out   std_logic;
+       DSP_RESET       : out   std_logic;
+       DSP_RESET_OUT   : in    std_logic;
+       DSP_WRH         : out   std_logic;
+       DSP_WRL         : out   std_logic;
+       VSD_A           : out   std_logic_vector (12 downto 0);
+       VSD_BA          : out   std_logic_vector (1 downto 0);
+       VSD_CAS         : out   std_logic;
+       VSD_CKE         : out   std_logic;
+       VSD_CLOCK       : out   std_logic;
+       VSD_CSEH        : out   std_logic;
+       VSD_CSEL        : out   std_logic;
+       VSD_D           : inout std_logic_vector (31 downto 0);
+       VSD_DQML        : out   std_logic_vector (3 downto 0);
+       VSD_RAS         : out   std_logic;
+       VSD_WE          : out   std_logic;
+       TLK_CLK         : in    std_logic;
+       TLK_ENABLE      : out   std_logic;
+       TLK_LCKREFN     : out   std_logic;
+       TLK_LOOPEN      : out   std_logic;
+       TLK_PRBSEN      : out   std_logic;
+       TLK_RXD         : in    std_logic_vector (15 downto 0);
+       TLK_RX_CLK      : in    std_logic;
+       TLK_RX_DV       : in    std_logic;
+       TLK_RX_ER       : in    std_logic;
+       TLK_TXD         : out   std_logic_vector (15 downto 0);
+       TLK_TX_EN       : out   std_logic;
+       TLK_TX_ER       : out   std_logic;
+      SFP_LOS         : in    std_logic;
+      SFP_TX_DIS      : out   std_logic;
+      SFP_TX_FAULT    : in    std_logic;
+      ADO_LVDS_IN          : in    std_logic_vector(51 downto 0);
+      ADO_LVDS_OUT                    : out std_logic_vector(9 downto 0);
+      ADDON_TO_TRB_CLKINN       : in std_logic;
+     ADDON_TO_TRB_CLKINP       : in std_logic;
+      ADO_TTL         : inout std_logic_vector(46 downto 0);
+--      ADO_TTL         : inout std_logic_vector(15 downto 0);
+      VIRT_TCK        : out   std_logic;
+      VIRT_TDI        : out   std_logic;
+      VIRT_TDO        : in    std_logic;
+      VIRT_TMS        : out   std_logic;
+      VIRT_TRST       : out   std_logic);
+  end component;
+
   component edge_to_pulse
     port (
       clock       : in  std_logic;
@@ -184,7 +349,177 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       signal_in   : in  std_logic;
       pulse       : out std_logic);
   end component;
-  signal VIRT_CLK :     std_logic;
+  constant ENABLE_DMA: integer := 2;
+-------------------------------------------------------------------------------
+-- cts
+-------------------------------------------------------------------------------
+  
+  signal CTS_VIRT_CLK        : std_logic;
+  signal CTS_VIRT_CLKB       : std_logic;
+  signal CTS_RESET_VIRT      : std_logic;
+  signal CTS_DBAD            : std_logic;
+  signal CTS_DGOOD           : std_logic;
+  signal CTS_DINT            : std_logic;
+  signal CTS_DWAIT           : std_logic;
+  signal CTS_A_RESERVED      : std_logic;
+  signal CTS_B_RESERVED      : std_logic;
+  signal CTS_C_RESERVED      : std_logic;
+  signal CTS_D_RESERVED      : std_logic;
+  signal CTS_TEMP_SENS : std_logic_vector(3 downto 0);
+  signal CTS_VIR_TRIG        : std_logic;
+  signal CTS_VIR_TRIGB       : std_logic;
+  signal CTS_A_TDC_ERROR     : std_logic;
+  signal CTS_B_TDC_ERROR     : std_logic;
+  signal CTS_C_TDC_ERROR     : std_logic;
+  signal CTS_D_TDC_ERROR     : std_logic;
+  signal CTS_A_TDC_POWERUP   : std_logic;
+  signal CTS_B_TDC_POWERUP   : std_logic;
+  signal CTS_C_TDC_POWERUP   : std_logic;
+  signal CTS_D_TDC_POWERUP   : std_logic;
+  signal CTS_TOKEN_IN        : std_logic;
+  signal CTS_TOKEN_OUT       : std_logic;
+  signal CTS_C_TOKEN_OUT_TTL : std_logic;
+  signal CTS_GET_DATA        : std_logic;
+  signal CTS_A_DATA_READY    : std_logic;
+  signal CTS_B_DATA_READY    : std_logic;
+  signal CTS_C_DATA_READY    : std_logic;
+  signal CTS_D_DATA_READY    : std_logic;
+  signal CTS_REF_TDC_CLK     : std_logic;
+  signal CTS_REF_TDC_CLKB    : std_logic;
+  signal CTS_A_TDC_BU_RESET  : std_logic;
+  signal CTS_A_TDC_BU_RESETB : std_logic;
+  signal CTS_A_TDC_EV_RESET  : std_logic;
+  signal CTS_A_TDC_EV_RESETB : std_logic;
+  signal CTS_B_TDC_BU_RESET  : std_logic;
+  signal CTS_B_TDC_BU_RESETB : std_logic;
+  signal CTS_B_TDC_EV_RESET  : std_logic;
+  signal CTS_B_TDC_EV_RESETB : std_logic;
+  signal CTS_C_TDC_BU_RESET  : std_logic;
+  signal CTS_C_TDC_BU_RESETB : std_logic;
+  signal CTS_C_TDC_EV_RESET  : std_logic;
+  signal CTS_C_TDC_EV_RESETB : std_logic;
+  signal CTS_D_TDC_BU_RESET  : std_logic;
+  signal CTS_D_TDC_BU_RESETB : std_logic;
+  signal CTS_D_TDC_EV_RESET  : std_logic;
+  signal CTS_D_TDC_EV_RESETB : std_logic;
+  signal CTS_TDC_OUT         : std_logic_vector (31 downto 0);
+  signal CTS_TDC_RESET       : std_logic;
+  signal CTS_A_TRIGGER       : std_logic;
+  signal CTS_A_TRIGGERB      : std_logic;
+  signal CTS_B_TRIGGER       : std_logic;
+  signal CTS_B_TRIGGERB      : std_logic;
+  signal CTS_C_TRIGGER       : std_logic;
+  signal CTS_C_TRIGGERB      : std_logic;
+  signal CTS_D_TRIGGER       : std_logic;
+  signal CTS_D_TRIGGERB      : std_logic;
+  signal CTS_FS_PB           : std_logic_vector (16 downto 0);
+  signal CTS_FS_PB_17           : std_logic;
+  signal CTS_FS_PC           : std_logic_vector (17 downto 0);
+  signal CTS_ETRAX_IRQ       : std_logic;
+  signal CTS_A_SCK           : std_logic;
+  signal CTS_A_SCKB          : std_logic;
+  signal CTS_A_SDI           : std_logic;
+  signal CTS_A_SDIB          : std_logic;
+  signal CTS_A_SDO           : std_logic;
+  signal CTS_A_SDOB          : std_logic;
+  signal CTS_A_CSB           : std_logic;
+  signal CTS_A_CS            : std_logic;
+  signal CTS_B_SCK           : std_logic;
+  signal CTS_B_SCKB          : std_logic;
+  signal CTS_B_SDI           : std_logic;
+  signal CTS_B_SDIB          : std_logic;
+  signal CTS_B_SDO           : std_logic;
+  signal CTS_B_SDOB          : std_logic;
+  signal CTS_B_CSB           : std_logic;
+  signal CTS_B_CS            : std_logic;
+  signal CTS_C_SCK           : std_logic;
+  signal CTS_C_SCKB          : std_logic;
+  signal CTS_C_SDI           : std_logic;
+  signal CTS_C_SDIB          : std_logic;
+  signal CTS_C_SDO           : std_logic;
+  signal CTS_C_SDOB          : std_logic;
+  signal CTS_C_CSB           : std_logic;
+  signal CTS_C_CS            : std_logic;
+  signal CTS_D_SCK           : std_logic;
+  signal CTS_D_SCKB          : std_logic;
+  signal CTS_D_SDI           : std_logic;
+  signal CTS_D_SDIB          : std_logic;
+  signal CTS_D_SDO           : std_logic;
+  signal CTS_D_SDOB          : std_logic;
+  signal CTS_D_CSB           : std_logic;
+  signal CTS_D_CS            : std_logic;
+  signal CTS_A_TEST1         : std_logic;
+  signal CTS_A_TEST1B        : std_logic;
+  signal CTS_A_TEST2         : std_logic;
+  signal CTS_A_TEST2B        : std_logic;
+  signal CTS_B_TEST1         : std_logic;
+  signal CTS_B_TEST1B        : std_logic;
+  signal CTS_B_TEST2         : std_logic;
+  signal CTS_B_TEST2B        : std_logic;
+  signal CTS_C_TEST1         : std_logic;
+  signal CTS_C_TEST1B        : std_logic;
+  signal CTS_C_TEST2         : std_logic;
+  signal CTS_C_TEST2B        : std_logic;
+  signal CTS_D_TEST1         : std_logic;
+  signal CTS_D_TEST1B        : std_logic;
+  signal CTS_D_TEST2         : std_logic;
+  signal CTS_D_TEST2B        : std_logic;
+  signal CTS_DSPADDR         : std_logic_vector (31 downto 0);
+  signal CTS_DSPDAT          : std_logic_vector (31 downto 0);
+  signal CTS_DSP_ACK         : std_logic;
+  signal CTS_DSP_BM          : std_logic;
+  signal CTS_DSP_BMS         : std_logic;
+  signal CTS_DSP_BOFF        : std_logic;
+  signal CTS_DSP_BRST        : std_logic;
+  signal CTS_DSP_HBG         : std_logic;
+  signal CTS_DSP_HBR         : std_logic;
+  signal CTS_DSP_IRQ         : std_logic_vector (3 downto 0);
+  signal CTS_DSP_RD          : std_logic;
+  signal CTS_DSP_RESET       : std_logic;
+  signal CTS_DSP_RESET_OUT   : std_logic;
+  signal CTS_DSP_WRH         : std_logic;
+  signal CTS_DSP_WRL         : std_logic;
+  signal CTS_VSD_A           : std_logic_vector (12 downto 0);
+  signal CTS_VSD_BA          : std_logic_vector (1 downto 0);
+  signal CTS_VSD_CAS         : std_logic;
+  signal CTS_VSD_CKE         : std_logic;
+  signal CTS_VSD_CLOCK       : std_logic;
+  signal CTS_VSD_CSEH        : std_logic;
+  signal CTS_VSD_CSEL        : std_logic;
+  signal CTS_VSD_D           : std_logic_vector (31 downto 0);
+  signal CTS_VSD_DQML        : std_logic_vector (3 downto 0);
+  signal CTS_VSD_RAS         : std_logic;
+  signal CTS_VSD_WE          : std_logic;
+  signal CTS_TLK_CLK         : std_logic;
+  signal CTS_TLK_ENABLE      : std_logic;
+  signal CTS_TLK_LCKREFN     : std_logic;
+  signal CTS_TLK_LOOPEN      : std_logic;
+  signal CTS_TLK_PRBSEN      : std_logic;
+  signal CTS_TLK_RXD         : std_logic_vector (15 downto 0);
+  signal CTS_TLK_RX_CLK      : std_logic;
+  signal CTS_TLK_RX_DV       : std_logic;
+  signal CTS_TLK_RX_ER       : std_logic;
+  signal CTS_TLK_TXD         : std_logic_vector (15 downto 0);
+  signal CTS_TLK_TX_EN       : std_logic;
+  signal CTS_TLK_TX_ER       : std_logic;
+  signal CTS_SFP_LOS         : std_logic;
+  signal CTS_SFP_TX_DIS      : std_logic;
+  signal CTS_SFP_TX_FAULT    : std_logic;
+  signal CTS_ADO_LVDS_IN          : std_logic_vector(51 downto 0);
+  signal CTS_ADO_LVDS_OUT          : std_logic_vector(9 downto 0);
+  signal CTS_ADO_TTL         : std_logic_vector(46 downto 0);
+--    signal CTS_ADO_TTL         : std_logic_vector(15 downto 0);
+  signal CTS_VIRT_TCK        : std_logic;
+  signal CTS_VIRT_TDI        : std_logic;
+  signal CTS_VIRT_TDO        : std_logic;
+  signal CTS_VIRT_TMS        : std_logic;
+  signal CTS_VIRT_TRST       : std_logic;
+  signal CTS_ADDON_TO_TRB_CLKINN       :  std_logic;
+  signal CTS_ADDON_TO_TRB_CLKINP       :  std_logic;
+-------------------------------------------------------------------------------
+-- trb signals
+-------------------------------------------------------------------------------
+  signal VIRT_CLK        : std_logic;
   signal VIRT_CLKB       : std_logic;
   signal RESET_VIRT      : std_logic;
   signal DBAD            : std_logic;
@@ -192,13 +527,10 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal DINT            : std_logic;
   signal DWAIT           : std_logic;
   signal A_RESERVED      : std_logic;
-  signal A_TEMP          : std_logic;
   signal B_RESERVED      : std_logic;
-  signal B_TEMP          : std_logic;
   signal C_RESERVED      : std_logic;
-  signal C_TEMP          : std_logic;
   signal D_RESERVED      : std_logic;
-  signal D_TEMP          : std_logic;
+  signal TEMP_SENS       : std_logic_vector(3 downto 0);
   signal VIR_TRIG        : std_logic;
   signal VIR_TRIGB       : std_logic;
   signal A_TDC_ERROR     : std_logic;
@@ -338,7 +670,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal SFP_LOS         : std_logic;
   signal SFP_TX_DIS      : std_logic;
   signal SFP_TX_FAULT    : std_logic;
-  signal ADO_LV          : std_logic_vector(51 downto 0);
+  signal ADO_LVDS_IN     : std_logic_vector(51 downto 0);
+  signal ADO_LVDS_OUT    : std_logic_vector(9 downto 0);
   signal ADO_TTL         : std_logic_vector(46 downto 0);
 --    signal ADO_TTL         : std_logic_vector(15 downto 0);
   signal VIRT_TCK        : std_logic;
@@ -346,9 +679,10 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal VIRT_TDO        : std_logic;
   signal VIRT_TMS        : std_logic;
   signal VIRT_TRST       : std_logic;
-  signal    ADDON_TO_TRB_CLKINN       :  std_logic;
-  signal    ADDON_TO_TRB_CLKINP       :  std_logic;
+  signal ADDON_TO_TRB_CLKINN       :  std_logic;
+  signal ADDON_TO_TRB_CLKINP       :  std_logic;
 
+  
   signal test_synch_00 : std_logic;
   signal dtu_clk : std_logic;
   signal dtu_lvl1_tag : std_logic_vector(7 downto 0);
@@ -371,7 +705,171 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal etrax_busy_counter : std_logic_vector(15 downto 0);
   signal etrax_busy : std_logic;
 BEGIN
-  trb: trb_v2b_fpga
+  trb_cts: trb_v2b_fpga
+    port map (
+        VIRT_CLK        => VIRT_CLK,
+        VIRT_CLKB       => VIRT_CLKB,
+        RESET_VIRT      => CTS_RESET_VIRT,
+        DBAD            => CTS_DBAD,
+        DGOOD           => CTS_DGOOD,
+        DINT            => CTS_DINT,
+        DWAIT           => CTS_DWAIT,
+        A_RESERVED      => CTS_A_RESERVED,
+        B_RESERVED      => CTS_B_RESERVED,
+        C_RESERVED      => CTS_C_RESERVED,
+        D_RESERVED      => CTS_D_RESERVED,
+        TEMP_SENS       => CTS_temp_sens,
+         VIR_TRIG        => CTS_VIR_TRIG,
+         VIR_TRIGB       => CTS_VIR_TRIGB,
+        A_TDC_ERROR     => CTS_A_TDC_ERROR,
+        B_TDC_ERROR     => CTS_B_TDC_ERROR,
+        C_TDC_ERROR     => CTS_C_TDC_ERROR,
+        D_TDC_ERROR     => CTS_D_TDC_ERROR,
+        A_TDC_POWERUP   => CTS_A_TDC_POWERUP,
+        B_TDC_POWERUP   => CTS_B_TDC_POWERUP,
+        C_TDC_POWERUP   => CTS_C_TDC_POWERUP,
+        D_TDC_POWERUP   => CTS_D_TDC_POWERUP,
+        TOKEN_IN        => CTS_TOKEN_IN,
+        TOKEN_OUT       => CTS_TOKEN_OUT,
+        C_TOKEN_OUT_TTL => CTS_C_TOKEN_OUT_TTL,
+        GET_DATA        => CTS_GET_DATA,
+        A_DATA_READY    => CTS_A_DATA_READY,
+        B_DATA_READY    => CTS_B_DATA_READY,
+        C_DATA_READY    => CTS_C_DATA_READY,
+        D_DATA_READY    => CTS_D_DATA_READY,
+        REF_TDC_CLK     => REF_TDC_CLK,
+        REF_TDC_CLKB    => REF_TDC_CLKB,
+        A_TDC_BU_RESET  => CTS_A_TDC_BU_RESET,
+        A_TDC_BU_RESETB => CTS_A_TDC_BU_RESETB,
+        A_TDC_EV_RESET  => CTS_A_TDC_EV_RESET,
+        A_TDC_EV_RESETB => CTS_A_TDC_EV_RESETB,
+        B_TDC_BU_RESET  => CTS_B_TDC_BU_RESET,
+        B_TDC_BU_RESETB => CTS_B_TDC_BU_RESETB,
+        B_TDC_EV_RESET  => CTS_B_TDC_EV_RESET,
+        B_TDC_EV_RESETB => CTS_B_TDC_EV_RESETB,
+        C_TDC_BU_RESET  => CTS_C_TDC_BU_RESET,
+        C_TDC_BU_RESETB => CTS_C_TDC_BU_RESETB,
+        C_TDC_EV_RESET  => CTS_C_TDC_EV_RESET,
+        C_TDC_EV_RESETB => CTS_C_TDC_EV_RESETB,
+        D_TDC_BU_RESET  => CTS_D_TDC_BU_RESET,
+        D_TDC_BU_RESETB => CTS_D_TDC_BU_RESETB,
+        D_TDC_EV_RESET  => CTS_D_TDC_EV_RESET,
+        D_TDC_EV_RESETB => CTS_D_TDC_EV_RESETB,
+        TDC_OUT         => CTS_TDC_OUT,
+        TDC_RESET       => CTS_TDC_RESET,
+        A_TRIGGER       => CTS_A_TRIGGER,
+        A_TRIGGERB      => CTS_A_TRIGGERB,
+        B_TRIGGER       => CTS_B_TRIGGER,
+        B_TRIGGERB      => CTS_B_TRIGGERB,
+        C_TRIGGER       => CTS_C_TRIGGER,
+        C_TRIGGERB      => CTS_C_TRIGGERB,
+        D_TRIGGER       => CTS_D_TRIGGER,
+        D_TRIGGERB      => CTS_D_TRIGGERB,
+        FS_PB           => CTS_FS_PB,
+        FS_PB_17           => CTS_FS_PB_17,
+        FS_PC           => CTS_FS_PC,
+        ETRAX_IRQ       => CTS_ETRAX_IRQ,
+        A_SCK           => CTS_A_SCK,
+        A_SCKB          => CTS_A_SCKB,
+        A_SDI           => CTS_A_SDI,
+        A_SDIB          => CTS_A_SDIB,
+        A_SDO           => CTS_A_SDO,
+        A_SDOB          => CTS_A_SDOB,
+        A_CSB           => CTS_A_CSB,
+        A_CS            => CTS_A_CS,
+        B_SCK           => CTS_B_SCK,
+        B_SCKB          => CTS_B_SCKB,
+        B_SDI           => CTS_B_SDI,
+        B_SDIB          => CTS_B_SDIB,
+        B_SDO           => CTS_B_SDO,
+        B_SDOB          => CTS_B_SDOB,
+        B_CSB           => CTS_B_CSB,
+        B_CS            => CTS_B_CS,
+        C_SCK           => CTS_C_SCK,
+        C_SCKB          => CTS_C_SCKB,
+        C_SDI           => CTS_C_SDI,
+        C_SDIB          => CTS_C_SDIB,
+        C_SDO           => CTS_C_SDO,
+        C_SDOB          => CTS_C_SDOB,
+        C_CSB           => CTS_C_CSB,
+        C_CS            => CTS_C_CS,
+        D_SCK           => CTS_D_SCK,
+        D_SCKB          => CTS_D_SCKB,
+        D_SDI           => CTS_D_SDI,
+        D_SDIB          => CTS_D_SDIB,
+        D_SDO           => CTS_D_SDO,
+        D_SDOB          => CTS_D_SDOB,
+        D_CSB           => CTS_D_CSB,
+        D_CS            => CTS_D_CS,
+        A_TEST1         => CTS_A_TEST1,
+        A_TEST1B        => CTS_A_TEST1B,
+        A_TEST2         => CTS_A_TEST2,
+        A_TEST2B        => CTS_A_TEST2B,
+        B_TEST1         => CTS_B_TEST1,
+        B_TEST1B        => CTS_B_TEST1B,
+        B_TEST2         => CTS_B_TEST2,
+        B_TEST2B        => CTS_B_TEST2B,
+        C_TEST1         => CTS_C_TEST1,
+        C_TEST1B        => CTS_C_TEST1B,
+        C_TEST2         => CTS_C_TEST2,
+        C_TEST2B        => CTS_C_TEST2B,
+        D_TEST1         => CTS_D_TEST1,
+        D_TEST1B        => CTS_D_TEST1B,
+        D_TEST2         => CTS_D_TEST2,
+        D_TEST2B        => CTS_D_TEST2B,
+         DSPADDR         => CTS_DSPADDR,
+         DSPDAT          => CTS_DSPDAT,
+         DSP_ACK         => CTS_DSP_ACK,
+         DSP_BM          => CTS_DSP_BM,
+         DSP_BMS         => CTS_DSP_BMS,
+         DSP_BOFF        => CTS_DSP_BOFF,
+         DSP_BRST        => CTS_DSP_BRST,
+         DSP_HBG         => CTS_DSP_HBG,
+         DSP_HBR         => CTS_DSP_HBR,
+         DSP_IRQ         => CTS_DSP_IRQ,
+         DSP_RD          => CTS_DSP_RD,
+         DSP_RESET       => CTS_DSP_RESET,
+         DSP_RESET_OUT   => CTS_DSP_RESET_OUT,
+         DSP_WRH         => CTS_DSP_WRH,
+         DSP_WRL         => CTS_DSP_WRL,
+         VSD_A           => CTS_VSD_A,
+         VSD_BA          => CTS_VSD_BA,
+         VSD_CAS         => CTS_VSD_CAS,
+         VSD_CKE         => CTS_VSD_CKE,
+         VSD_CLOCK       => CTS_VSD_CLOCK,
+         VSD_CSEH        => CTS_VSD_CSEH,
+         VSD_CSEL        => CTS_VSD_CSEL,
+         VSD_D           => CTS_VSD_D,
+         VSD_DQML        => CTS_VSD_DQML,
+         VSD_RAS         => CTS_VSD_RAS,
+         VSD_WE          => CTS_VSD_WE,
+         TLK_CLK         => TLK_CLK,
+         TLK_ENABLE      => CTS_TLK_ENABLE,
+         TLK_LCKREFN     => CTS_TLK_LCKREFN,
+         TLK_LOOPEN      => CTS_TLK_LOOPEN,
+         TLK_PRBSEN      => CTS_TLK_PRBSEN,
+         TLK_RXD         => CTS_TLK_RXD,
+         TLK_RX_CLK      => TLK_RX_CLK,
+         TLK_RX_DV       => CTS_TLK_RX_DV,
+         TLK_RX_ER       => CTS_TLK_RX_ER,
+         TLK_TXD         => CTS_TLK_TXD,
+         TLK_TX_EN       => CTS_TLK_TX_EN,
+         TLK_TX_ER       => CTS_TLK_TX_ER,
+        SFP_LOS         => CTS_SFP_LOS,
+        SFP_TX_DIS      => CTS_SFP_TX_DIS,
+        SFP_TX_FAULT    => CTS_SFP_TX_FAULT,
+        ADO_LVDS_OUT          => CTS_ADO_LVDS_OUT,
+        ADO_LVDS_IN       => CTS_ADO_LVDS_IN,
+        ADO_TTL         => CTS_ADO_TTL,
+        ADDON_TO_TRB_CLKINN => CTS_ADDON_TO_TRB_CLKINN,
+        ADDON_TO_TRB_CLKINP => CTS_ADDON_TO_TRB_CLKINP,
+        VIRT_TCK        => CTS_VIRT_TCK,
+        VIRT_TDI        => CTS_VIRT_TDI,
+        VIRT_TDO        => CTS_VIRT_TDO,
+        VIRT_TMS        => CTS_VIRT_TMS,
+        VIRT_TRST       => CTS_VIRT_TRST);
+  
+  trb_end: trb_v2b_fpga_endpoint
     port map (
         VIRT_CLK        => VIRT_CLK,
         VIRT_CLKB       => VIRT_CLKB,
@@ -381,13 +879,10 @@ BEGIN
         DINT            => DINT,
         DWAIT           => DWAIT,
         A_RESERVED      => A_RESERVED,
-        A_TEMP          => A_TEMP,
         B_RESERVED      => B_RESERVED,
-        B_TEMP          => B_TEMP,
         C_RESERVED      => C_RESERVED,
-        C_TEMP          => C_TEMP,
         D_RESERVED      => D_RESERVED,
-        D_TEMP          => D_TEMP,
+        TEMP_SENS       => temp_sens,
          VIR_TRIG        => VIR_TRIG,
          VIR_TRIGB       => VIR_TRIGB,
         A_TDC_ERROR     => A_TDC_ERROR,
@@ -527,7 +1022,8 @@ BEGIN
         SFP_LOS         => SFP_LOS,
         SFP_TX_DIS      => SFP_TX_DIS,
         SFP_TX_FAULT    => SFP_TX_FAULT,
-        ADO_LV          => ADO_LV,
+        ADO_LVDS_OUT          => ADO_LVDS_OUT,
+        ADO_LVDS_IN       => ADO_LVDS_IN,
         ADO_TTL         => ADO_TTL,
         ADDON_TO_TRB_CLKINN => ADDON_TO_TRB_CLKINN,
         ADDON_TO_TRB_CLKINP => ADDON_TO_TRB_CLKINP,
@@ -546,98 +1042,277 @@ BEGIN
   etrax_int_test: process
   begin
     ---------------------------------------------------------------------------
-    -- writing register
+    -- writing register - enable not HADES triggering
     ---------------------------------------------------------------------------
     rw_mode <= x"0000";
-    address <= x"00000006";
-    data <= x"00000102";
-    FS_PC(17) <= '0';
-    FS_PC(16) <= '0';
+    address <= x"000000c0";
+    data <= x"40000000";
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
     wait for 1000 ns;
     for rw_mode_counter in 0 to 15 loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= rw_mode(rw_mode_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= rw_mode(rw_mode_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
     end loop;
     wait for 300 ns;
     for address_counter in 0 to 31 loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= address(address_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= address(address_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
     end loop;
     wait for 300 ns;
     for data_counter in 0 to 31  loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= data(data_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= data(data_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
     end loop;
     wait for 300 ns;
-    FS_PC(17) <= '0';
-    FS_PC(16) <= '0';
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
     wait for 400 ns;
-    FS_PC(17) <= '1';
+    CTS_FS_PC(17) <= '1';
     wait for 100 ns;
-    FS_PC(17) <= '0';
+    CTS_FS_PC(17) <= '0';
+    ---------------------------------------------------------------------------
+    -- writing register - write trb ID 
+    ---------------------------------------------------------------------------
+    rw_mode <= x"0000";
+    address <= x"000000c4";
+    data <= x"00000324";
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 1000 ns;
+    for rw_mode_counter in 0 to 15 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+    end loop;
+    wait for 300 ns;
+    for address_counter in 0 to 31 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
+    end loop;
+    wait for 300 ns;
+    for data_counter in 0 to 31  loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
+    end loop;
+    wait for 300 ns;
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 400 ns;
+    CTS_FS_PC(17) <= '1';
+    wait for 100 ns;
+    CTS_FS_PC(17) <= '0';
+    
+    ---------------------------------------------------------------------------
+    -- writing register - enable EB header inside the FPGA 
+    ---------------------------------------------------------------------------
+
+    if ENABLE_DMA = 1 then
+      rw_mode     <= x"0000";
+      address     <= x"000000c2";
+      data        <= x"80000000";
+      CTS_FS_PC(17)   <= '0';
+      CTS_FS_PC(16)   <= '0';
+    elsif ENABLE_DMA = 2 then
+      rw_mode     <= x"0000";
+      address     <= x"000000c2";
+      data        <= x"00400000";
+      CTS_FS_PC(17)   <= '0';
+      CTS_FS_PC(16)   <= '0';
+    end if;    
+      wait for 1000 ns;
+      for rw_mode_counter in 0 to 15 loop
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '0';
+        CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '1';
+        CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+      end loop;
+      wait for 300 ns;
+      for address_counter in 0 to 31 loop
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '0';
+        CTS_FS_PC(16) <= address(address_counter);
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '1';
+        CTS_FS_PC(16) <= address(address_counter);
+      end loop;
+      wait for 300 ns;
+      for data_counter in 0 to 31 loop
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '0';
+        CTS_FS_PC(16) <= data(data_counter);
+        wait for 100 ns;
+        CTS_FS_PC(17) <= '1';
+        CTS_FS_PC(16) <= data(data_counter);
+      end loop;
+      wait for 300 ns;
+      CTS_FS_PC(17)   <= '0';
+      CTS_FS_PC(16)   <= '0';
+      wait for 400 ns;
+      CTS_FS_PC(17)   <= '1';
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+    
+    ---------------------------------------------------------------------------
+    -- writing register - enable self triggering 
+    ---------------------------------------------------------------------------
+    rw_mode <= x"0000";
+    address <= x"000000c5";
+    data <= x"80000800";
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 1000 ns;
+    for rw_mode_counter in 0 to 15 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+    end loop;
+    wait for 300 ns;
+    for address_counter in 0 to 31 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
+    end loop;
+    wait for 300 ns;
+    for data_counter in 0 to 31  loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
+    end loop;
+    wait for 300 ns;
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 400 ns;
+    CTS_FS_PC(17) <= '1';
+    wait for 100 ns;
+    CTS_FS_PC(17) <= '0';
+    ---------------------------------------------------------------------------
+    -- writing register - enable self triggering with max freq
+    ---------------------------------------------------------------------------
+    rw_mode <= x"0000";
+    address <= x"000000c6";
+    data <= x"00000100";
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 1000 ns;
+    for rw_mode_counter in 0 to 15 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+    end loop;
+    wait for 300 ns;
+    for address_counter in 0 to 31 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
+    end loop;
+    wait for 300 ns;
+    for data_counter in 0 to 31  loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
+    end loop;
+    wait for 300 ns;
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 400 ns;
+    CTS_FS_PC(17) <= '1';
+    wait for 100 ns;
+    CTS_FS_PC(17) <= '0';
 
     ---------------------------------------------------------------------------
     -- reading register
     ---------------------------------------------------------------------------
     rw_mode <= x"8000";
-    address <= x"00000006";
+    address <= x"000000c0";
     data <= x"f000f00f";
-    FS_PC(17) <= '0';
-    FS_PC(16) <= '0';
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
     wait for 1000 ns;
     for rw_mode_counter in 0 to 15 loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= rw_mode(rw_mode_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= rw_mode(rw_mode_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
     end loop;
     for address_counter in 0 to 31 loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= address(address_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= address(address_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
     end loop;
     for data_counter in 0 to 31  loop
       wait for 100 ns;
-      FS_PC(17) <= '0';
-      FS_PC(16) <= data(data_counter);
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
       wait for 100 ns;
-      FS_PC(17) <= '1';
-      FS_PC(16) <= data(data_counter);
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
     end loop;
     wait for 100 ns;
-    FS_PC(17) <= '0';
+    CTS_FS_PC(17) <= '0';
     wait for 300 ns;
-    FS_PC(16) <= 'Z';
+    CTS_FS_PC(16) <= 'Z';
     wait for 300 ns;
-    FS_PC(17) <= '1';      --fpga should change the direction of line
+    CTS_FS_PC(17) <= '1';      --fpga should change the direction of line
     wait for 100 ns;
-    FS_PC(17) <= '0';
+    CTS_FS_PC(17) <= '0';
 
     
     wait for 300 ns;
     for data_to_etrax_counter in 0 to 31  loop
-      FS_PC(16) <= 'Z';
+      CTS_FS_PC(16) <= 'Z';
       wait for 100 ns;
-      FS_PC(17) <= '0';
+      CTS_FS_PC(17) <= '0';
       wait for 100 ns;
-      FS_PC(17) <= '1';
+      CTS_FS_PC(17) <= '1';
     end loop;
     wait;
 
@@ -699,16 +1374,22 @@ BEGIN
         TLK_RX_CLK <=  '1';
         wait for 5 ns;
         end process;
-        RX_ER: process
-          begin
-          TLK_RX_ER <= '0';
-          wait for 2200 ns;
-          TLK_RX_ER <= '1';
-          wait for 120 ns;             
-        end process;
-        TLK_RXD <= TLK_TXD;
-        --TLK_RX_ER <= '0';
-        TLK_RX_DV <= '1';
+--        RX_ER: process
+--          begin
+--          TLK_RX_ER <= '0';
+--          wait for 2200 ns;
+--          TLK_RX_ER <= '1';
+--          wait for 120 ns;             
+--        end process;
+--        TLK_RXD <= TLK_TXD;
+            TLK_RX_ER <= '0';
+            CTS_TLK_RX_ER <= '0';
+            TLK_RX_DV <= CTS_TLK_TX_EN;
+            CTS_TLK_RX_DV <= TLK_TX_EN;
+            TLK_RXD <= CTS_TLK_TXD;
+            CTS_TLK_RXD <= TLK_TXD;
+            SFP_LOS <= '0';
+            CTS_SFP_LOS <= '0';
         -----------------------------------------------------------------------
         -- process check headers - number of words in event
         -----------------------------------------------------------------------
@@ -717,9 +1398,9 @@ BEGIN
 --           port map (
 --               clock  => VIRT_CLK,
 --               en_clk => '1',
---               signal_in    => FS_PB(16),
+--               signal_in    => CTS_FS_PB(16),
 --               pulse  => valid_pulse_i);
---         not_valid <= FS_PB(16);
+--         not_valid <= CTS_FS_PB(16);
 --         not_valid_pulse: edge_to_pulse
 --           port map (
 --               clock  => VIRT_CLK,
@@ -737,7 +1418,7 @@ BEGIN
 --         begin 
 --           if rising_edge(VIRT_CLK) then
 --             if valid_pulse_i = '1' then
---               save_lenght <= FS_PB(15 downto 0);
+--               save_lenght <= CTS_FS_PB(15 downto 0);
 --               compare_counter <= (others => '0');
 --             elsif etrax_ready_pulse = '1' then
 --               save_lenght <= save_lenght;
@@ -748,7 +1429,7 @@ BEGIN
 --             end if;
 --           end if;
 --         end process ckeck_header;
---         wrong_lenght_of_event <= '1' when ((save_lenght /= compare_counter) and FS_PB(16) = '0')  else '0';
+--         wrong_lenght_of_event <= '1' when ((save_lenght /= compare_counter) and CTS_FS_PB(16) = '0')  else '0';
         -----------------------------------------------------------------------
         -- TDC and etrax readout
         -----------------------------------------------------------------------
@@ -816,34 +1497,80 @@ BEGIN
           wait for 0 ns;
 --          ADO_TTL(6) <= '1';
           TOKEN_IN <= '1';
-          wait for 25 ns;
+          wait for 50 ns;
 --          ADO_TTL(6) <= '0';
           TOKEN_IN <= '0';
     --      wait on REF_TDC_CLK until DBAD = '0';
           valid_time := valid_time*3/2 +1; 
          end process;
-         ETRAX_BUSY_PROC: process
-           variable etrax_busy_time : integer :=0;
-         begin  -- process ETRAX_BUSY
-           FS_PB_17 <= '0';
-           wait on VIRT_CLK until FS_PB(16) ='1';
-           wait for 20 ns;
-           FS_PB_17 <= '1';
-           wait for 80 ns;
-           wait on VIRT_CLK until etrax_busy  ='0';
 
-           
---           wait for ((etrax_busy_time mod 7 )*5+20)*ns;
-           etrax_busy_time := etrax_busy_time*3/2 +1;
-         end process ETRAX_BUSY_PROC;
+        ETRAX_HAS_NO_DMA_CTS: if ENABLE_DMA = 2 generate
+          ETRAX_BUSY_PROC: process
+            variable etrax_busy_time : integer :=0;
+          begin  -- process ETRAX_BUSY
+            CTS_FS_PB_17 <= '0';
+            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+            wait for 20 ns;
+            CTS_FS_PB_17 <= '1';
+            wait for 80 ns;
+            wait on VIRT_CLK until etrax_busy  ='0';
+            etrax_busy_time := etrax_busy_time*3/2 +1;
+          end process ETRAX_BUSY_PROC;
+            
+        end generate ETRAX_HAS_NO_DMA_CTS;
+
+        ETRAX_HAS_DMA_CTS: if ENABLE_DMA = 1 generate
+          ETRAX_BUSY_PROC: process
+            variable etrax_busy_time : integer :=0;
+          begin  -- process ETRAX_BUSY
+            CTS_FS_PB_17 <= '0';
+            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+            wait for 20 ns;
+            CTS_FS_PB_17 <= '1';
+            wait for 680 ns;
+            etrax_busy_time := etrax_busy_time*3/2 +1;
+          end process ETRAX_BUSY_PROC;
+            
+        end generate ETRAX_HAS_DMA_CTS;
+
+         ETRAX_HAS_NO_DMA: if ENABLE_DMA = 2 generate
+          ETRAX_BUSY_PROC: process
+            variable etrax_busy_time : integer :=0;
+          begin  -- process ETRAX_BUSY
+            FS_PB_17 <= '0';
+            wait on VIRT_CLK until FS_PB(16) ='1';
+            wait for 20 ns;
+            FS_PB_17 <= '1';
+            wait for 80 ns;
+            wait on VIRT_CLK until etrax_busy  ='0';
+            etrax_busy_time := etrax_busy_time*3/2 +1;
+          end process ETRAX_BUSY_PROC;
+            
+        end generate ETRAX_HAS_NO_DMA;
+
+        ETRAX_HAS_DMA: if ENABLE_DMA = 1 generate
+          ETRAX_BUSY_PROC: process
+            variable etrax_busy_time : integer :=0;
+          begin  -- process ETRAX_BUSY
+            FS_PB_17 <= '0';
+            wait on VIRT_CLK until FS_PB(16) ='1';
+            wait for 20 ns;
+            FS_PB_17 <= '1';
+            wait for 680 ns;
+            etrax_busy_time := etrax_busy_time*3/2 +1;
+          end process ETRAX_BUSY_PROC;
+            
+        end generate ETRAX_HAS_DMA;
+
+        
 
           WAIT_FOR_TRANSFER_END: process
             variable wait_int : integer range 0 to 65535;
           begin
             etrax_busy <= '0';
-            wait on VIRT_CLK until FS_PB(16) ='1';
+            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
             etrax_busy <= '1';
---            etrax_busy_counter <= FS_PC(15 downto 0);
+--            etrax_busy_counter <= CTS_FS_PC(15 downto 0);
 --            wait for  to_integer(unsigned(etrax_busy_counter(15 downto 0)))*10 ns+ 40 ns;
             wait for 37*10 ns;
           end process WAIT_FOR_TRANSFER_END;
@@ -1057,26 +1784,26 @@ BEGIN
 --         end process send_external_trigger;
 --        ETRAX_RESPONSE: process
 --        begin
---          FS_PC(16) <= '0';
---            FS_PC(17) <= '0';
+--          CTS_FS_PC(16) <= '0';
+--            CTS_FS_PC(17) <= '0';
 --            wait for 10 ns;
 --            RESET_VIRT <= '0';
 
 --            wait for 10 ns;
---            FS_PC(16) <= '1';
---            FS_PC(17) <= '1';
+--            CTS_FS_PC(16) <= '1';
+--            CTS_FS_PC(17) <= '1';
 --            RESET_VIRT <= '1';
 --            wait for 10 ns;
     
 --            wait for 30 ns;
---            FS_PC(16) <= '0';
---            FS_PC(17) <= '0';
+--            CTS_FS_PC(16) <= '0';
+--            CTS_FS_PC(17) <= '0';
 --            wait for 10 ns;
 --            loop
---              FS_PC(17) <= '0';
---              wait on TLK_CLK until FS_PB(16) ='1';
+--              CTS_FS_PC(17) <= '0';
+--              wait on TLK_CLK until CTS_FS_PB(16) ='1';
 --              wait for 20 ns;
---              FS_PC(17) <= '1';
+--              CTS_FS_PC(17) <= '1';
 --              wait for 2000 ns;
 --          end loop;
 --        end process ETRAX_RESPONSE;