USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
package config is
constant INCLUDE_UART : integer := c_YES;
constant INCLUDE_SPI : integer := c_YES;
-
+ constant INCLUDE_LCD : integer := c_YES;
+
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ others => x"00");
+
+
+
+--With GbE:
+-- for MII_NUMBER=5 (4 downlinks, 1 uplink):
+-- port 0,1,2,3: downlinks to other FPGA
+-- port 4: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL
+-- port 5: SCTRL channel on uplink to CTS
+-- port 6: SCTRL channel from GbE interface
+
+ constant INTERFACE_NUM : integer := 5;
+ constant MII_IS_UPLINK : hub_mii_config_t := (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0);
+ constant MII_IS_DOWNLINK : hub_mii_config_t := (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0);
+ constant MII_IS_UPLINK_ONLY : hub_mii_config_t := (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0);
------------------------------------------------------------------------------
--Select settings by configuration
# compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3sc_basic"
+set_option -top_module "trb3sc_hubaddon"
set_option -resource_sharing false
# map options
# set result format/file last
project -result_format "edif"
-project -result_file "workdir/trb3sc_basic.edf"
+project -result_file "workdir/trb3sc_hubaddon.edf"
#implementation attributes
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
#Fifos
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd"
#Flash & Reload, Tools
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+#Hub
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
+
+
+#GbE
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v"
+#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd"
+
+
add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "./trb3sc_basic.vhd"
+add_file -vhdl -lib work "./trb3sc_hubaddon.vhd"
#add_file -fpga_constraint "./synplify.fdc"
use work.trb_net_gbe_components.all;
use work.med_sync_define.all;
-entity trb3sc_basic is
+entity trb3sc_hubaddon is
port(
CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
- --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
- --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
- --CLK_CORE_PLL_LEFT : in std_logic; --not used
- --CLK_CORE_PLL_RIGHT : in std_logic; --not used
- --CLK_EXT_PCLK : in std_logic; --not used
- --CLK_EXT_PLL_RIGHT : in std_logic; --not used
-
- TRIG_LEFT : in std_logic; --Trigger Input
- --TRIG_PLL : in std_logic; --not used
- --TRIG_RIGHT : in std_logic; --not used
-
- --Backplane, all lines
- BACK_GPIO : inout std_logic_vector(15 downto 0);
- BACK_LVDS : inout std_logic_vector( 1 downto 0);
- BACK_3V3 : inout std_logic_vector( 3 downto 0);
- --Backplane for slaves on trbv3scbp1
--- BACK_GPIO : inout std_logic_vector(3 downto 0);
-
- --AddOn Connector
- --to be added
-
- --KEL Connector
--- KEL : inout std_logic_vector(40 downto 1);
-
+
--Additional IO
HDR_IO : inout std_logic_vector(10 downto 1);
- RJ_IO : inout std_logic_vector( 3 downto 0);
- SPARE_IN : in std_logic_vector( 1 downto 0);
+-- RJ_IO : inout std_logic_vector( 3 downto 0);
+-- SPARE_IN : in std_logic_vector( 1 downto 0);
--LED
LED_GREEN : out std_logic;
SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z');
SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0');
- SERDES_TX : out std_logic_vector(1 downto 0);
- SERDES_RX : in std_logic_vector(1 downto 0);
+ SERDES_TX : out std_logic_vector(13 downto 0);
+ SERDES_RX : in std_logic_vector(13 downto 0);
+
+ LED_HUB_LINKOK : out std_logic_vector(6 downto 1);
+ LED_HUB_RX : out std_logic_vector(6 downto 1);
+ LED_HUB_TX : out std_logic_vector(6 downto 1);
+ HUB_MOD0 : in std_logic_vector(6 downto 1);
+ HUB_MOD1 : inout std_logic_vector(6 downto 1);
+ HUB_MOD2 : inout std_logic_vector(6 downto 1);
+ HUB_TXDIS : out std_logic_vector(6 downto 1);
+ HUB_LOS : in std_logic_vector(6 downto 1);
--Serdes switch
PCSSW_ENSMB : out std_logic;
end entity;
-architecture trb3sc_arch of trb3sc_basic is
+architecture trb3sc_arch of trb3sc_hubaddon is
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
signal debug_clock_reset : std_logic_vector(31 downto 0);
--Media Interface
- signal med2int : med2int_array_t(0 to 0);
- signal int2med : int2med_array_t(0 to 0);
+ signal med2int : med2int_array_t(0 to 4);
+ signal int2med : int2med_array_t(0 to 4);
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- --READOUT
- signal readout_rx : READOUT_RX;
- signal readout_tx : readout_tx_array_t(0 to 0);
-
- signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bussci_rx, bussci2_rx, bustools_rx, bustc_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bussci2_tx, bustools_tx, bustc_tx : CTRLBUS_TX;
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
signal sed_error_i : std_logic;
- signal clock_select : std_logic;
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
- signal uart_tx, uart_rx : std_logic;
signal timer : TIMERS;
-
+ signal lcd_data : std_logic_vector(511 downto 0);
+
+ signal cts_number : std_logic_vector(15 downto 0);
+ signal cts_code : std_logic_vector(7 downto 0);
+ signal cts_information : std_logic_vector(7 downto 0);
+ signal cts_start_readout : std_logic;
+ signal cts_readout_type : std_logic_vector(3 downto 0);
+ signal cts_data : std_logic_vector(31 downto 0);
+ signal cts_dataready : std_logic;
+ signal cts_readout_finished : std_logic;
+ signal cts_read : std_logic;
+ signal cts_length : std_logic_vector(15 downto 0);
+ signal cts_status_bits : std_logic_vector(31 downto 0);
+ signal fee_data : std_logic_vector(15 downto 0);
+ signal fee_dataready : std_logic;
+ signal fee_read : std_logic;
+ signal fee_status_bits : std_logic_vector(31 downto 0);
+ signal fee_busy : std_logic;
+ signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
+ signal gsc_init_read, gsc_reply_read : std_logic;
+ signal gsc_init_dataready, gsc_reply_dataready : std_logic;
+ signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
+ signal gsc_busy : std_logic;
+ signal my_address : std_logic_vector(15 downto 0);
+ signal mc_unique_id : std_logic_vector(63 downto 0);
+ signal reset_via_gbe : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
port map(
INT_CLK_IN => CLK_CORE_PCLK,
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(0).clk_full,
- NET_CLK_HALF_IN => med2int(0).clk_half,
- RESET_FROM_NET => med2int(0).stat_op(13),
+ NET_CLK_FULL_IN => med2int(4).clk_full,
+ NET_CLK_HALF_IN => med2int(4).clk_half,
+ RESET_FROM_NET => med2int(4).stat_op(13),
BUS_RX => bustc_rx,
BUS_TX => bustc_tx,
---------------------------------------------------------------------------
-- TrbNet Uplink
---------------------------------------------------------------------------
-
THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
generic map(
SERDES_NUM => 3,
- IS_SYNC_SLAVE => c_NO
+ IS_SYNC_SLAVE => c_YES
)
port map(
CLK => clk_full_osc,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(0),
- MEDIA_INT2MED => int2med(0),
+ MEDIA_MED2INT => med2int(4),
+ MEDIA_INT2MED => int2med(4),
--Sync operation
RX_DLM => open,
BUS_RX => bussci_rx,
BUS_TX => bussci_tx,
-- Status and control port
- STAT_DEBUG => med_stat_debug(63 downto 0),
+ STAT_DEBUG => open,
CTRL_DEBUG => open
);
SFP_TX_DIS(0) <= '1';
---------------------------------------------------------------------------
--- Endpoint
+-- TrbNet Downlink
---------------------------------------------------------------------------
-THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
- generic map (
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- REGIO_INIT_ENDPOINT_ID => x"0001",
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 10,
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**8,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**8
+THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
)
-
port map(
- -- Misc
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
+ CLK => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0 to 1) => med2int(2 to 3),
+ MEDIA_MED2INT(2 to 3) => med2int(0 to 1),
+ MEDIA_INT2MED(0 to 1) => int2med(2 to 3),
+ MEDIA_INT2MED(2 to 3) => int2med(0 to 1),
- -- Media direction port
- MEDIA_MED2INT => med2int(0),
- MEDIA_INT2MED => int2med(0),
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_RX(5 downto 2),
+ SD_RXD_N_IN => SERDES_RX(9 downto 6),
+ SD_TXD_P_OUT => SERDES_TX(5 downto 2),
+ SD_TXD_N_OUT => SERDES_TX(9 downto 6),
+ SD_PRSNT_N_IN(3 downto 2) => HUB_MOD0(2 downto 1),
+ SD_PRSNT_N_IN(1 downto 0) => HUB_MOD0(4 downto 3),
+ SD_LOS_IN(3 downto 2) => HUB_LOS(2 downto 1),
+ SD_LOS_IN(1 downto 0) => HUB_LOS(4 downto 3),
+ SD_TXDIS_OUT(3 downto 2) => HUB_TXDIS(2 downto 1),
+ SD_TXDIS_OUT(1 downto 0) => HUB_TXDIS(4 downto 3),
+
+ --Control Interface
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+ HUB_TXDIS(6 downto 5) <= "11";
+---------------------------------------------------------------------------
+-- GbE
+---------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------
+-- Hub
+---------------------------------------------------------------------------
+
+ THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record
+ generic map(
+ HUB_USED_CHANNELS => (1,1,0,1),
+ INIT_ADDRESS => INIT_ADDRESS,
+ MII_NUMBER => INTERFACE_NUM,
+ MII_IS_UPLINK => MII_IS_UPLINK,
+ MII_IS_DOWNLINK => MII_IS_DOWNLINK,
+ MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY,
+ USE_ONEWIRE => c_YES,
+ HARDWARE_VERSION => HARDWARE_INFO,
+ INCLUDED_FEATURES => INCLUDED_FEATURES,
+ INIT_ENDPOINT_ID => x"0001",
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY,
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ --Media interfacces
+ MEDIA_MED2INT => med2int,
+ MEDIA_INT2MED => int2med,
- READOUT_RX => readout_rx,
- READOUT_TX => readout_tx,
-
- --Slow Control Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- BUS_RX => ctrlbus_rx,
- BUS_TX => ctrlbus_tx,
- ONEWIRE_INOUT => TEMPSENS,
- --Timing registers
- TIMERS_OUT => timer
- );
+ --Event information coming from CTSCTS_READOUT_TYPE_OUT
+ CTS_NUMBER_OUT => cts_number,
+ CTS_CODE_OUT => cts_code,
+ CTS_INFORMATION_OUT => cts_information,
+ CTS_READOUT_TYPE_OUT => cts_readout_type,
+ CTS_START_READOUT_OUT => cts_start_readout,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN => cts_data,
+ CTS_DATAREADY_IN => cts_dataready,
+ CTS_READOUT_FINISHED_IN => cts_readout_finished,
+ CTS_READ_OUT => cts_read,
+ CTS_LENGTH_IN => cts_length,
+ CTS_STATUS_BITS_IN => cts_status_bits,
+ -- Data from Frontends
+ FEE_DATA_OUT => fee_data,
+ FEE_DATAREADY_OUT => fee_dataready,
+ FEE_READ_IN => fee_read,
+ FEE_STATUS_BITS_OUT => fee_status_bits,
+ FEE_BUSY_OUT => fee_busy,
+ MY_ADDRESS_IN => my_address,
+ COMMON_STAT_REGS => common_stat_reg, --open,
+ COMMON_CTRL_REGS => common_ctrl_reg, --open,
+ ONEWIRE => TEMPSENS,
+ MY_ADDRESS_OUT => my_address,
+ UNIQUE_ID_OUT => mc_unique_id,
+ EXTERNAL_SEND_RESET => reset_via_gbe,
+
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ TIMER => timer,
+
+ --Gbe Sctrl Input
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => '1', --gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+
+ --status and control ports
+ HUB_STAT_CHANNEL => open,
+ HUB_STAT_GEN => open,
+ MPLEX_CTRL => (others => '0'),
+ MPLEX_STAT => open,
+ STAT_REGS => open,
+ STAT_CTRL_REGS => open,
+
+ --Fixed status and control ports
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0),
+ PORT_NUMBER => 4,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"b200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 9, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
BUS_RX(1) => bussci_rx, --SCI Serdes
BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => bussci2_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bussci_tx,
BUS_TX(2) => bustc_tx,
-
+ BUS_TX(3) => bussci2_tx,
STAT_DEBUG => open
);
SPI_MOSI_OUT=> spi_mosi,
SPI_MISO_IN => spi_miso,
SPI_CLK_OUT => spi_clk,
- --UART
- UART_TX => uart_tx,
- UART_RX => uart_rx,
+ --Header
+ HEADER_IO => HDR_IO,
+ --LCD
+ LCD_DATA_IN => lcd_data,
--ADC
ADC_CS => ADC_CS,
ADC_MOSI => ADC_DIN,
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
---------------------------------------------------------------------------
--- I/O
----------------------------------------------------------------------------
- HDR_IO(1) <= uart_tx;
- uart_rx <= HDR_IO(2);
- HDR_IO(3) <= spi_mosi(8);
- spi_miso(8) <= HDR_IO(4);
- HDR_IO(5) <= spi_clk(8);
- HDR_IO(6) <= spi_cs(8);
- HDR_IO(10 downto 7) <= (others => '0');
-
- RJ_IO <= "0000";
-
- BACK_GPIO <= (others => 'Z');
- BACK_LVDS <= (others => '0');
- BACK_3V3 <= (others => 'Z');
+-- LCD Data to display
+---------------------------------------------------------------------------
+ lcd_data(15 downto 0) <= timer.network_address;
+ lcd_data(47 downto 16) <= timer.microsecond;
+ lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32));
+ lcd_data(511 downto 80) <= (others => '0');
---------------------------------------------------------------------------
-- LED
LED_RED <= not sed_error_i;
LED_YELLOW <= debug_clock_reset(2);
LED_WHITE <= led;
- LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status
- LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX
-
--- DEBUG_OUT(0) <= pll_int_lock;
--- DEBUG_OUT(1) <= pll_ext_lock;
--- DEBUG_OUT(2) <= clock_select;
+ LED_SFP_GREEN <= not med2int(4).stat_op(9) & '1'; --SFP Link Status
+ LED_SFP_RED <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)) & '1'; --SFP RX/TX
+
+ LED_HUB_LINKOK(1) <= not med2int(0).stat_op(9);
+ LED_HUB_TX(1) <= not (med2int(0).stat_op(10)); -- or med2int(0).stat_op(11));
+ LED_HUB_RX(1) <= not med2int(0).stat_op(11);
+ LED_HUB_LINKOK(2) <= not med2int(1).stat_op(9);
+ LED_HUB_TX(2) <= not (med2int(1).stat_op(10)); -- or med2int(1).stat_op(11));
+ LED_HUB_RX(2) <= not med2int(1).stat_op(11);
+ LED_HUB_LINKOK(3) <= not med2int(2).stat_op(9);
+ LED_HUB_TX(3) <= not (med2int(2).stat_op(10)); -- or med2int(2).stat_op(11));
+ LED_HUB_RX(3) <= not med2int(2).stat_op(11);
+ LED_HUB_LINKOK(4) <= not med2int(3).stat_op(9);
+ LED_HUB_TX(4) <= not (med2int(3).stat_op(10)); -- or med2int(3).stat_op(11));
+ LED_HUB_RX(4) <= not med2int(3).stat_op(11);
---------------------------------------------------------------------------
-- Test Circuits
end if;
end process;
- led(0) <= time_counter(26) and time_counter(19);
- led(1) <= time_counter(20);
+ led(0) <= time_counter(26) and time_counter(16);
+ led(1) <= not reset_i;
--- TEST_LINE <= med_stat_debug(15 downto 0);
+ TEST_LINE <= med_stat_debug(15 downto 0);
end architecture;
jspc29 / trb3sc.git / commitdiff