*** empty log message ***

diff --git a/testbenches/tb_rx_packets.vhd b/testbenches/tb_rx_packets.vhd
new file mode 100755 (executable)
index 0000000..2f02f22
--- /dev/null
+++ b/testbenches/tb_rx_packets.vhd
@@ -0,0 +1,227 @@
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+       COMPONENT trb_net16_rx_packets\r
+       PORT(\r
+               CLK_IN : IN std_logic;\r
+               SYSCLK_IN : IN std_logic;\r
+               RESET_IN : IN std_logic;\r
+               QUAD_RST_IN : IN std_logic;\r
+               RX_ALLOW_IN : IN std_logic;\r
+               RX_DATA_IN : IN std_logic_vector(7 downto 0);\r
+               RX_K_IN : IN std_logic;       \r
+               MED_DATA_OUT : OUT std_logic_vector(15 downto 0);\r
+               MED_DATAREADY_OUT : OUT std_logic;\r
+               MED_READ_IN : IN std_logic;\r
+               MED_PACKET_NUM_OUT : OUT std_logic_vector(2 downto 0);\r
+               SEND_RESET_WORDS_OUT : OUT std_logic;\r
+               MAKE_TRBNET_RESET_OUT : OUT std_logic;\r
+               LINK_BROKEN_OUT : OUT std_logic;\r
+               CLEAR_STATUS_IN : IN std_logic;\r
+               BSM_OUT : OUT std_logic_vector(3 downto 0);\r
+               DBG_OUT : OUT std_logic_vector(15 downto 0)\r
+               );\r
+       END COMPONENT;\r
+\r
+       SIGNAL CLK_IN :  std_logic;\r
+       SIGNAL SYSCLK_IN :  std_logic;\r
+       SIGNAL RESET_IN :  std_logic;\r
+       SIGNAL QUAD_RST_IN :  std_logic;\r
+       SIGNAL RX_ALLOW_IN :  std_logic;\r
+       SIGNAL RX_DATA_IN :  std_logic_vector(7 downto 0);\r
+       SIGNAL RX_K_IN :  std_logic;\r
+       SIGNAL MED_DATA_OUT :  std_logic_vector(15 downto 0);\r
+       SIGNAL MED_DATAREADY_OUT :  std_logic;\r
+       SIGNAL MED_READ_IN :  std_logic;\r
+       SIGNAL MED_PACKET_NUM_OUT :  std_logic_vector(2 downto 0);\r
+       SIGNAL SEND_RESET_WORDS_OUT :  std_logic;\r
+       SIGNAL MAKE_TRBNET_RESET_OUT :  std_logic;\r
+       SIGNAL LINK_BROKEN_OUT :  std_logic;\r
+       SIGNAL CLEAR_STATUS_IN :  std_logic;\r
+       SIGNAL BSM_OUT :  std_logic_vector(3 downto 0);\r
+       SIGNAL DBG_OUT :  std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+       uut: trb_net16_rx_packets PORT MAP(\r
+               CLK_IN => CLK_IN,\r
+               SYSCLK_IN => SYSCLK_IN,\r
+               RESET_IN => RESET_IN,\r
+               QUAD_RST_IN => QUAD_RST_IN,\r
+               RX_ALLOW_IN => RX_ALLOW_IN,\r
+               RX_DATA_IN => RX_DATA_IN,\r
+               RX_K_IN => RX_K_IN,\r
+               MED_DATA_OUT => MED_DATA_OUT,\r
+               MED_DATAREADY_OUT => MED_DATAREADY_OUT,\r
+               MED_READ_IN => MED_READ_IN,\r
+               MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,\r
+               SEND_RESET_WORDS_OUT => SEND_RESET_WORDS_OUT,\r
+               MAKE_TRBNET_RESET_OUT => MAKE_TRBNET_RESET_OUT,\r
+               LINK_BROKEN_OUT => LINK_BROKEN_OUT,\r
+               CLEAR_STATUS_IN => CLEAR_STATUS_IN,\r
+               BSM_OUT => BSM_OUT,\r
+               DBG_OUT => DBG_OUT\r
+       );\r
+\r
+-- Write clock (25MHz)\r
+SERDES_CLOCK_GEN: process\r
+begin\r
+       clk_in <= '1'; wait for 20.1 ns;\r
+       clk_in <= '0'; wait for 20.1 ns;\r
+end process SERDES_CLOCK_GEN;\r
+\r
+-- Read clock (100MHz)\r
+SYS_CLOCK_GEN: process\r
+begin\r
+       sysclk_in <= '1'; wait for 4.9 ns;\r
+       sysclk_in <= '0'; wait for 4.9 ns;\r
+end process SYS_CLOCK_GEN;\r
+\r
+-- Testbench\r
+THE_TESTBENCH: process\r
+begin\r
+       -- Setup signals\r
+       reset_in <= '0';\r
+       quad_rst_in <= '0';\r
+       rx_k_in <= '0';\r
+       rx_data_in <= x"00";\r
+       rx_allow_in <= '0';\r
+       med_read_in <= '0';\r
+       clear_status_in <= '0';\r
+\r
+       wait for 20 ns;\r
+       \r
+       -- Reset the whole stuff\r
+       reset_in <= '1'; clear_status_in <= '1'; wait for 33 ns;\r
+       reset_in <= '0'; clear_status_in <= '0'; wait for 55 ns;\r
+       \r
+       -- Tests may start now...\r
+       \r
+       -- TRBnet reset sequence\r
+       wait until rising_edge(clk_in);\r
+       rx_allow_in <= '1';\r
+       rx_k_in <= '1';\r
+       rx_data_in <= x"fe";\r
+       wait for 400 ns;\r
+\r
+       wait until rising_edge(sysclk_in);\r
+       med_read_in <= '1';\r
+\r
+       wait for 600 ns;\r
+       \r
+       THE_IDLE_LOOP: for I in 0 to 20 loop\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '1';\r
+               rx_data_in <= x"bc";\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '0';\r
+               rx_data_in <= x"50";\r
+       end loop THE_IDLE_LOOP; \r
+\r
+       wait until rising_edge(clk_in);\r
+       rx_k_in <= '0';\r
+       rx_data_in <= x"a0";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a1";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a2";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a3";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a4";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a5";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a6";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a7";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a8";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"a9";\r
+       wait until rising_edge(clk_in);\r
+\r
+       rx_data_in <= x"b0";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b1";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b2";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b3";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b4";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b5";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b6";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b7";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b8";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"b9";\r
+--     wait until rising_edge(clk_in);\r
+\r
+       THE_IDLE_LOOP_2: for I in 0 to 100 loop\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '1';\r
+               rx_data_in <= x"bc";\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '0';\r
+               rx_data_in <= x"50";\r
+       end loop THE_IDLE_LOOP_2;       \r
+       \r
+       rx_data_in <= x"c0";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c1";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c2";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c3";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c4";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c5";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c6";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c7";\r
+\r
+       THE_IDLE_LOOP_3: for I in 0 to 1200 loop\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '1';\r
+               rx_data_in <= x"bc";\r
+               wait until rising_edge(clk_in);\r
+               rx_k_in <= '0';\r
+               rx_data_in <= x"50";\r
+       end loop THE_IDLE_LOOP_3;       \r
+\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c8";\r
+       wait until rising_edge(clk_in);\r
+       rx_data_in <= x"c9";\r
+       wait until rising_edge(clk_in);\r
+\r
+--     THE_IDLE_LOOP_3: for I in 0 to 500 loop\r
+--             wait until rising_edge(clk_in);\r
+--             rx_k_in <= '1';\r
+--             rx_data_in <= x"bc";\r
+--             wait until rising_edge(clk_in);\r
+--             rx_k_in <= '0';\r
+--             rx_data_in <= x"50";\r
+--     end loop THE_IDLE_LOOP_3;       \r
+       \r
+       \r
+       -- Stay a while... stay forever!!!! Muahahaha!!!!\r
+       wait;\r
+       \r
+end process THE_TESTBENCH;\r
+\r
+END;\r