add trb_net_xdna to components so that it is not needed in every project

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index d2d2649bca6c87ba05394e6ef0a50e09589aa279..6bf80e77f6ecf87bc2e48d25d8162b5b943a78b5 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -661,7 +661,7 @@ begin
             REGIO_ONEWIRE_MONITOR_OUT <= '0';
             REGIO_ONEWIRE_INOUT       <= '0';
             
-            XilinxDNA : entity work.trb_net_xdna
+            XilinxDNA : trb_net_xdna
               port map(
                 CLK      => CLK,
                 RESET    => RESET,

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 3823fe6bbc18b25c9f0e5c72beab29ee4838a046..c40f48a4f83211e8daafe6af6c566e0ba986f771 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -3598,5 +3598,16 @@ end component;
       );\r
   end component;\r
 \r
+  component trb_net_xdna is\r
+    port (\r
+        CLK       : in  std_logic;\r
+        RESET     : in  std_logic;\r
+        DATA_OUT  : out std_logic_vector(15 downto 0);\r
+        ADDR_OUT  : out std_logic_vector( 2 downto 0);\r
+        WRITE_OUT : out std_logic;\r
+        TEMP_OUT  : out std_logic_vector(11 downto 0);\r
+        ID_OUT    : out std_logic_vector(63 downto 0)\r
+    );\r
+end component trb_net_xdna;\r
 \r
 end package;\r