*** empty log message ***

diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf
index f126c9ee988eeb7803919cf8ea0967d453520844..37f910c47d70fe06db7a9e48f238bb8f5e36787c 100644 (file)
--- a/base/trb3_periph.lpf
+++ b/base/trb3_periph.lpf
@@ -8,11 +8,6 @@ BLOCK RD_DURING_WR_PATHS ;
 
   SYSCONFIG MCCLK_FREQ = 2.5;
 
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 100 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf
index 046f3fd214f150d274982560fd6a1ec5232ee34c..957482f7abf3f4055105de463ab4babee5005607 100644 (file)
--- a/base/trb3_periph_constraints.lpf
+++ b/base/trb3_periph_constraints.lpf
@@ -6,10 +6,11 @@ BLOCK RD_DURING_WR_PATHS ;
 # Basic Settings
 #################################################################
 
+  SYSCONFIG MCCLK_FREQ = 2.5;
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
 
   
 #################################################################
@@ -417,4 +418,4 @@ LOCATE UGROUP "FIFO_7" REGION "Region_2" ;
 #LOCATE UGROUP "FC_46" SITE "R98C72D" ;
 #UGROUP "FC_47" BBOX 1 48 
 #BLKNAME GEN_FC_47_FC;
-#LOCATE UGROUP "FC_47" SITE "R102C72D" ;
\ No newline at end of file
+#LOCATE UGROUP "FC_47" SITE "R102C72D" ;