hit counters are directly synchronised to 100MHz

diff --git a/tdc_releases/tdc_v1.6.1/Channel.vhd b/tdc_releases/tdc_v1.6.1/Channel.vhd
index 9da5fbc4c9349fca231ee8724bdcc331c8c73b31..05bdfde6a211c1d44f02d7db350cde64c830f391 100644 (file)
--- a/tdc_releases/tdc_v1.6.1/Channel.vhd
+++ b/tdc_releases/tdc_v1.6.1/Channel.vhd
@@ -84,7 +84,6 @@ architecture Channel of Channel is
 
   -- debug
   signal sync_q                  : std_logic_vector(2 downto 0);
-  signal hit_pulse               : std_logic;
   signal hit_pulse_100           : std_logic;
   signal encoder_finished_i      : std_logic;
   signal encoder_finished_100    : std_logic;
@@ -221,24 +220,15 @@ begin
 -------------------------------------------------------------------------------
   gen_DEBUG : if DEBUG = c_YES generate
     --purpose: Hit Signal Synchroniser
-    sync_q(0) <= HIT_IN    when rising_edge(CLK_200);
-    sync_q(1) <= sync_q(0) when rising_edge(CLK_200);
-    sync_q(2) <= sync_q(1) when rising_edge(CLK_200);
+    sync_q(0) <= HIT_IN    when rising_edge(CLK_100);
+    sync_q(1) <= sync_q(0) when rising_edge(CLK_100);
+    sync_q(2) <= sync_q(1) when rising_edge(CLK_100);
 
     risingEdgeDetect_1 : risingEdgeDetect
       port map (
-        CLK       => CLK_200,
+        CLK       => CLK_100,
         SIGNAL_IN => sync_q(2),
-        PULSE_OUT => hit_pulse);
-
-    pulse_sync_hit : pulse_sync
-      port map (
-        CLK_A_IN    => CLK_200,
-        RESET_A_IN  => RESET_200,
-        PULSE_A_IN  => hit_pulse,
-        CLK_B_IN    => CLK_100,
-        RESET_B_IN  => RESET_100,
-        PULSE_B_OUT => hit_pulse_100);
+        PULSE_OUT => hit_pulse_100);
 
     --purpose: Counts the detected but unwritten hits
     Lost_Hit_Counter : process (CLK_100)

diff --git a/tdc_releases/tdc_v1.6.1/Channel_200.vhd b/tdc_releases/tdc_v1.6.1/Channel_200.vhd
index 91468e88e4b018857194bb8472937ee9c6bc8dd0..874b319a9c1b42dc88fb52a0d051aa7dc486580e 100644 (file)
--- a/tdc_releases/tdc_v1.6.1/Channel_200.vhd
+++ b/tdc_releases/tdc_v1.6.1/Channel_200.vhd
@@ -5,7 +5,7 @@
 -- File       : Channel_200.vhd
 -- Author     : c.ugur@gsi.de
 -- Created    : 2012-08-28
--- Last update: 2014-04-30
+-- Last update: 2014-05-06
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -337,7 +337,7 @@ begin  -- Channel_200
   FSM_CLK : process (CLK_200)
   begin
     if RESET_200 = '1' then
-      FSM_WR_CURRENT    <= WRITE_EPOCH;
+      FSM_WR_CURRENT <= WRITE_EPOCH;
     elsif rising_edge(CLK_200) then
       FSM_WR_CURRENT    <= FSM_WR_NEXT;
       write_epoch_i     <= write_epoch_fsm;
@@ -802,7 +802,7 @@ begin  -- Channel_200
   --CHANNEL_200_DEBUG(17)           <= fifo_data_valid_i;
   --CHANNEL_200_DEBUG(18)           <= ringBuffer_rd_en_i;
   --CHANNEL_200_DEBUG(23 downto 19) <= (others => '0');
-  CHANNEL_200_DEBUG(23 downto 0) <= (others => '0');
+  CHANNEL_200_DEBUG(23 downto 0)  <= (others => '0');
   CHANNEL_200_DEBUG(27 downto 24) <= fsm_rd_debug_i;
   CHANNEL_200_DEBUG(31 downto 28) <= fsm_wr_debug_i;
 

diff --git a/tdc_releases/tdc_v1.6.1/TDC.vhd b/tdc_releases/tdc_v1.6.1/TDC.vhd
index 26c69f95af9f9ffb1ebbb6ca6843a2649b80f431..9f8716d2f0c11085b7f5048781319aa60d812d89 100644 (file)
--- a/tdc_releases/tdc_v1.6.1/TDC.vhd
+++ b/tdc_releases/tdc_v1.6.1/TDC.vhd
@@ -128,6 +128,7 @@ architecture TDC of TDC is
   signal hit_latch                    : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
   signal hit_reg                      : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
   signal hit_2reg                     : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+  signal hit_3reg                     : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
 -- Calibration
   signal hit_calibration_cntr         : unsigned(15 downto 0)                       := (others => '0');
   signal hit_calibration_i            : std_logic;
@@ -230,9 +231,9 @@ begin
 
   -- Blocks the input after the rising edge against short pulses
   GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate
-    TheStretcher : process (HIT_IN, hit_2reg)
+    TheStretcher : process (HIT_IN, hit_3reg)
     begin
-      if hit_2reg(i) = '1' then
+      if hit_3reg(i) = '1' then
         hit_latch(i) <= '0';
       elsif rising_edge(HIT_IN(i)) then
         hit_latch(i) <= '1';
@@ -241,6 +242,7 @@ begin
   end generate GEN_HitBlock;
   hit_reg  <= hit_latch when rising_edge(CLK_TDC);
   hit_2reg <= hit_reg   when rising_edge(CLK_TDC);
+  hit_3reg <= hit_2reg  when rising_edge(CLK_TDC);
 
   GEN_hit_mux: for i in 1 to CHANNEL_NUMBER-1 generate
     hit_mux_ch: hit_mux