port (
clk : in std_logic; -- clk input
reset : in std_logic; -- reset input
+ bypass : in std_logic; -- bypass logic
gray_in : in std_logic_vector (NBITS - 1 downto 0); -- gray counter input
bin_out : out std_logic_vector (NBITS - 1 downto 0) -- binary counter output
);
for i in NBITS - 2 downto 0 loop
decoding(i) := gray_in(i) xor decoding(i + 1);
end loop;
- bin_out <= decoding;
+ if bypass = '1' then
+ bin_out <= gray_in;
+ else
+ bin_out <= decoding;
+ end if;
end if;
end if;
end process;