Update tdctemplate design

diff --git a/pinout/trb3sc_padiwa.lpf b/pinout/trb3sc_padiwa.lpf
index d787f5277016fb973db33b6eeeaf0fda460c6ae3..9efaf211d01be3998b50f0eacde7c02eedaa14a4 100644 (file)
--- a/pinout/trb3sc_padiwa.lpf
+++ b/pinout/trb3sc_padiwa.lpf
@@ -371,37 +371,37 @@ LOCATE COMP  "INP_95"   SITE "AD26";
 DEFINE PORT GROUP "INP_group" "INP*" ;
 IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 
-LOCATE COMP  "IN_SDI_1"  SITE "K4";     #was "DQUL1_2_P" 81
-LOCATE COMP  "IN_SDI_2"  SITE "M8";     #was "DQUL1_3_P" 89
-LOCATE COMP  "IN_SDI_3"  SITE "AF34";   #was "DQLR1_4_P" 189
-LOCATE COMP  "IN_SDI_4"  SITE "N9";     #was "DQSUL0_T"  86
-LOCATE COMP  "IN_SDI_5"  SITE "P7";
-LOCATE COMP  "IN_SDI_6"  SITE "M29";
-
-DEFINE PORT GROUP "IN_group" "IN*" ;
+LOCATE COMP  "DAC_IN_SDI_1"  SITE "K4";     #was "DQUL1_2_P" 81
+LOCATE COMP  "DAC_IN_SDI_2"  SITE "M8";     #was "DQUL1_3_P" 89
+LOCATE COMP  "DAC_IN_SDI_3"  SITE "AF34";   #was "DQLR1_4_P" 189
+LOCATE COMP  "DAC_IN_SDI_4"  SITE "N9";     #was "DQSUL0_T"  86
+LOCATE COMP  "DAC_IN_SDI_5"  SITE "P7";
+LOCATE COMP  "DAC_IN_SDI_6"  SITE "M29";
+
+DEFINE PORT GROUP "IN_group" "DAC_IN*" ;
 IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 
 
-LOCATE COMP  "OUT_SDO_1"   SITE "N2";     #was "DQUL3_1_P" 53
-LOCATE COMP  "OUT_SCK_1"   SITE "F3";     #was "DQUL2_1_P" 54
-LOCATE COMP  "OUT_CS_1"    SITE "G2";     #was "DQUL2_2_P" 58
-LOCATE COMP  "OUT_SDO_2"   SITE "K2";     #was "DQUL1_1_P" 77
-LOCATE COMP  "OUT_SCK_2"   SITE "M4";     #was "DQUL0_1_P" 78
-LOCATE COMP  "OUT_CS_2"    SITE "M7";     #was "DQUL0_4_P" 94
-LOCATE COMP  "OUT_SDO_3"   SITE "AD33";   #was "DQLR1_3_P" 185
-LOCATE COMP  "OUT_SCK_3"   SITE "Y34";    #was "DQLR2_3_P" 186
-LOCATE COMP  "OUT_CS_3"    SITE "Y26";    #was "DQLR2_4_P" 190
-LOCATE COMP  "OUT_SDO_4"   SITE "K6";     #was "DQUL0_2_P" 82
-LOCATE COMP  "OUT_SCK_4"   SITE "J3";     #was "DQUL2_4_P" 70
-LOCATE COMP  "OUT_CS_4"    SITE "K7";     #was "DQUL1_4_P" 93
-LOCATE COMP  "OUT_SDO_5"   SITE "R8";
-LOCATE COMP  "OUT_SCK_5"   SITE "R2";
-LOCATE COMP  "OUT_CS_5"    SITE "P9";
-LOCATE COMP  "OUT_SDO_6"   SITE "AC28";
-LOCATE COMP  "OUT_SCK_6"   SITE "M34";
-LOCATE COMP  "OUT_CS_6"    SITE "L28";
-
-DEFINE PORT GROUP "OUT_group" "OUT*" ;
+LOCATE COMP  "DAC_OUT_SDO_1"   SITE "N2";     #was "DQUL3_1_P" 53
+LOCATE COMP  "DAC_OUT_SCK_1"   SITE "F3";     #was "DQUL2_1_P" 54
+LOCATE COMP  "DAC_OUT_CS_1"    SITE "G2";     #was "DQUL2_2_P" 58
+LOCATE COMP  "DAC_OUT_SDO_2"   SITE "K2";     #was "DQUL1_1_P" 77
+LOCATE COMP  "DAC_OUT_SCK_2"   SITE "M4";     #was "DQUL0_1_P" 78
+LOCATE COMP  "DAC_OUT_CS_2"    SITE "M7";     #was "DQUL0_4_P" 94
+LOCATE COMP  "DAC_OUT_SDO_3"   SITE "AD33";   #was "DQLR1_3_P" 185
+LOCATE COMP  "DAC_OUT_SCK_3"   SITE "Y34";    #was "DQLR2_3_P" 186
+LOCATE COMP  "DAC_OUT_CS_3"    SITE "Y26";    #was "DQLR2_4_P" 190
+LOCATE COMP  "DAC_OUT_SDO_4"   SITE "K6";     #was "DQUL0_2_P" 82
+LOCATE COMP  "DAC_OUT_SCK_4"   SITE "J3";     #was "DQUL2_4_P" 70
+LOCATE COMP  "DAC_OUT_CS_4"    SITE "K7";     #was "DQUL1_4_P" 93
+LOCATE COMP  "DAC_OUT_SDO_5"   SITE "R8";
+LOCATE COMP  "DAC_OUT_SCK_5"   SITE "R2";
+LOCATE COMP  "DAC_OUT_CS_5"    SITE "P9";
+LOCATE COMP  "DAC_OUT_SDO_6"   SITE "AC28";
+LOCATE COMP  "DAC_OUT_SCK_6"   SITE "M34";
+LOCATE COMP  "DAC_OUT_CS_6"    SITE "L28";
+
+DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ;
 IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
 
 
@@ -567,4 +567,4 @@ LOCATE COMP "TEST_LINE_13"                    SITE "D20";
 LOCATE COMP "TEST_LINE_14"                    SITE "F21";
 LOCATE COMP "TEST_LINE_15"                    SITE "F22";
 DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
\ No newline at end of file
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;

diff --git a/scripts/compile.pl b/scripts/compile.pl
index 2e95fcc79cae7f1bfbc0a425356c915955325279..84347f6d24123e91375692e3b994d69a4cbf8b91 100755 (executable)
--- a/scripts/compile.pl
+++ b/scripts/compile.pl
@@ -196,6 +196,12 @@ if($con==1 || $all==1){
     $fh = new FileHandle(">$WORKDIR/$TOPNAME".".lpf");
     print $fh @newline;
     $fh -> close;
+    
+    
+  #edit the lpf file according to tdc settings
+  system("unlink $WORKDIR/compile_tdc.pl");
+  system("ln -s ../../../tdc/scripts/compile_tdc.pl $WORKDIR/");
+  system ("./$WORKDIR/compile_tdc.pl", $WORKDIR, $TOPNAME, "config");  
   }
 
   if($include_GBE) {
@@ -245,6 +251,7 @@ my $tpmap = $TOPNAME . "_map" ;
 
 chdir $WORKDIR;
 if($syn==1 || $all==1){
+    system ("./compile_tdc.pl", $WORKDIR, $TOPNAME, "prj") if ($include_TDC); ## edit prj file for different designs
     print GREEN, "Starting synthesis process...\n\n", RESET;
     $synplify_command = "$synplify_path/bin/synplify_premier_dp" unless $synplify_command;
     $c="$synplify_command -batch ../$TOPNAME.prj";

diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd
index fc255c3c0afd50a1fab1f44f389c1a033f0886ed..b82207e21b9283affa692c8d22626e5c7e31cddb 100644 (file)
--- a/tdctemplate/config.vhd
+++ b/tdctemplate/config.vhd
@@ -10,6 +10,8 @@ package config is
 --Begin of design configuration
 ------------------------------------------------------------------------------
 
+  constant FPGA_TYPE               : integer  := 3;  --3: ECP3, 5: ECP5
+  
   --pinout to be used - don't forget to change config_compile.pl as well
   -- 0: 32 Pin AddOn
   -- 1: 4conn AddOn
@@ -31,10 +33,11 @@ package config is
   constant TDC_DATA_FORMAT         : integer := 0;                                                                  
 
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant EVENT_MAX_SIZE          : integer := 4095;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
+    constant USE_200MHZOSCILLATOR   : integer := c_NO;
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
     constant CLOCK_FAST_SELECT      : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
@@ -131,6 +134,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
     t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
     return t;
   end function;   
 

diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf
index f7752d4ce6278ff2ea03ea2d75e02482b8bd0d4c..50f8f07d5ef14bd785b78be0a94ceddcc1a22d86 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.lpf
+++ b/tdctemplate/trb3sc_tdctemplate.lpf
@@ -1,9 +1,9 @@
 # MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full_osc" 1 X ;
 # MULTICYCLE FROM CLKNET "clk_full_osc" TO CLKNET "clk_sys" 2 X ;
 
-MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
-MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x;
-
-MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
-MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;
+# MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
+# MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CELL "THE_TDC/*Channe*/Channel200/RingBuffer*FIFO/*" 5x;
+# 
+# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
+# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;
 

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 2af62b3d33e472f9f7d93027df7e3bf7ad1b9583..5b65338e8216f2860608132af873df6f2f7ba0be 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -65,6 +65,7 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
 #Basic Infrastructure
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
 add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
 add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
@@ -189,8 +190,8 @@ add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
-#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"