*** empty log message ***

diff --git a/tdc_test/compile_periph_synonly_hades27.pl b/tdc_test/compile_periph_synonly_hades27.pl
index 305155fb2c4530834eefad43415d9710a43396c3..fd46de469a1caaedd849354deb87661f3a03d853 100755 (executable)
--- a/tdc_test/compile_periph_synonly_hades27.pl
+++ b/tdc_test/compile_periph_synonly_hades27.pl
@@ -39,7 +39,7 @@ my $SPEEDGRADE="8";
 
 
 #create full lpf file
-system("cp $BasePath/".$TOPNAME."_ada.lpf workdir/$TOPNAME.lpf");
+system("cp ".$TOPNAME."_ada_mainz.lpf workdir/$TOPNAME.lpf");
 system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
 
 

diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj
index d950480f2598b4b735fffea03d3bec51caefb678..102c15798e32c3eb807636d03da2babf86a43a8e 100644 (file)
--- a/tdc_test/trb3_periph.prj
+++ b/tdc_test/trb3_periph.prj
@@ -141,23 +141,17 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "source/Adder_304.vhd"
 add_file -vhdl -lib "work" "source/bit_sync.vhd"
 add_file -vhdl -lib "work" "source/Channel.vhd"
-add_file -vhdl -lib "work" "source/corell.vhd"
-
 add_file -vhdl -lib "work" "source/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "source/Encoder_304_ROMsuz.vhd"
-#add_file -vhdl -lib "work" "source/Encoder_304_Sngl_ROMsuz.vhd"
-
 add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd"
+add_file -vhdl -lib "work" "source/MB_SPI.vhd"
 add_file -vhdl -lib "work" "source/pll_100_in_5_out.vhd"
 add_file -vhdl -lib "work" "source/Reference_channel.vhd"
-add_file -vhdl -lib "work" "source/reset_generator.vhd"
 
 #add_file -vhdl -lib "work" "source/ROM_Encoder.vhd"
 #add_file -vhdl -lib "work" "source/ROM_encoder_2.vhd"
 add_file -vhdl -lib "work" "source/ROM_encoder_3.vhd"
 
 add_file -vhdl -lib "work" "source/ROM_FIFO.vhd"
-
 add_file -vhdl -lib "work" "source/TDC.vhd"
 add_file -vhdl -lib "work" "source/trb3_periph.vhd"
 add_file -vhdl -lib "work" "source/up_counter.vhd"