use work.trb_net_components.all;
-entity trb_net16_endpoint_hades_full_handler is
+entity trb_net16_endpoint_hades_full_handler_record is
generic (
IBUF_DEPTH : channel_config_t := (6,6,6,6);
FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
--internal data port
- BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);
- BUS_READ_ENABLE_OUT : out std_logic;
- BUS_WRITE_ENABLE_OUT : out std_logic;
- BUS_TIMEOUT_OUT : out std_logic;
- BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- BUS_DATAREADY_IN : in std_logic := '0';
- BUS_WRITE_ACK_IN : in std_logic := '0';
- BUS_NO_MORE_DATA_IN : in std_logic := '0';
- BUS_UNKNOWN_ADDR_IN : in std_logic := '0';
+ BUS_RX : out CTRLBUS_RX;
+ BUS_TX : in CTRLBUS_TX;
+
--Onewire
ONEWIRE_INOUT : inout std_logic; --temperature sensor
ONEWIRE_MONITOR_IN : in std_logic := '0';
-architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_hades_full_handler is
+architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endpoint_hades_full_handler_record is
signal lvl1_data_valid_i : std_logic;
signal lvl1_valid_i : std_logic;
signal stat_strobe_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
signal ctrl_strobe_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
- signal regio_addr_i : std_logic_vector (15 downto 0);
- signal regio_read_enable_i : std_logic;
- signal regio_write_enable_i : std_logic;
- signal regio_data_out_i : std_logic_vector (31 downto 0);
- signal regio_data_in_i : std_logic_vector (31 downto 0);
- signal regio_dataready_i : std_logic;
- signal regio_nomoredata_i : std_logic;
- signal regio_write_ack_i : std_logic;
- signal regio_unknown_addr_i : std_logic;
- signal regio_timeout_i : std_logic;
+ signal regio_rx, dbuf_rx, info_rx, stat_handler_rx, stat_buffer_rx : CTRLBUS_RX;
+ signal regio_tx, dbuf_tx, info_tx, stat_handler_tx, stat_buffer_tx : CTRLBUS_TX;
signal time_global_i : std_logic_vector (31 downto 0);
signal time_local_i : std_logic_vector ( 7 downto 0);
signal stat_data_buffer_level : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0);
signal stat_header_buffer_level: std_logic_vector (31 downto 0);
- signal dbuf_read_enable : std_logic;
- signal dbuf_addr : std_logic_vector (15 downto 0);
- signal dbuf_data_out : std_logic_vector (31 downto 0);
- signal dbuf_dataready : std_logic;
- signal dbuf_unknown_addr : std_logic;
-
- signal info_addr : std_logic_vector(15 downto 0);
- signal info_data_in : std_logic_vector(31 downto 0);
- signal info_data_out : std_logic_vector(31 downto 0);
- signal info_read : std_logic;
- signal info_write : std_logic;
signal info_rd_nack : std_logic;
signal info_wr_nack : std_logic;
- signal info_wr_ack : std_logic;
- signal info_valid : std_logic;
- signal info_invalid : std_logic;
- signal info_registers : std_logic_vector_array_32(0 to 3);
-
- signal stat_handler_addr : std_logic_vector(15 downto 0);
- signal stat_handler_data_in : std_logic_vector(31 downto 0);
- signal stat_handler_data_out : std_logic_vector(31 downto 0);
- signal stat_handler_read : std_logic;
- signal stat_handler_write : std_logic;
- signal stat_handler_valid : std_logic;
- signal stat_handler_invalid : std_logic;
+
+ signal info_registers : std_logic_vector_array_32(0 to 3);
signal stat_handler_registers : std_logic_vector_array_32(0 to 2);
- signal dummy : std_logic_vector(100 downto 0);
-
signal debug_data_handler_i : std_logic_vector(31 downto 0);
signal debug_ipu_handler_i : std_logic_vector(31 downto 0);
signal int_lvl1_long_trg : std_logic;
signal tmg_trg_error_i : std_logic;
- signal stat_buffer_out : std_logic_vector(31 downto 0);
- signal stat_buffer_read : std_logic;
- signal stat_buffer_write : std_logic;
- signal stat_buffer_ready : std_logic;
- signal stat_buffer_unknown : std_logic;
- signal stat_buffer_wr_nack : std_logic;
- signal stat_buffer_rd_nack : std_logic;
- signal stat_buffer_address : std_logic_vector(15 downto 0);
signal max_event_size : std_logic_vector(15 downto 0);
signal new_max_size : std_logic_vector(15 downto 0);
COMMON_CTRL_REG_STROBE => common_ctrl_strobe_i,
STAT_REG_STROBE => stat_strobe_i,
CTRL_REG_STROBE => ctrl_strobe_i,
-
- REGIO_ADDR_OUT => regio_addr_i,
- REGIO_READ_ENABLE_OUT => regio_read_enable_i,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_i,
- REGIO_DATA_OUT => regio_data_out_i,
- REGIO_DATA_IN => regio_data_in_i,
- REGIO_DATAREADY_IN => regio_dataready_i,
- REGIO_NO_MORE_DATA_IN => regio_nomoredata_i,
- REGIO_WRITE_ACK_IN => regio_write_ack_i,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_i,
- REGIO_TIMEOUT_OUT => regio_timeout_i,
+
+ REGIO_ADDR_OUT => regio_rx.addr, --regio_addr_out,
+ REGIO_READ_ENABLE_OUT => regio_rx.read, --regio_read_enable_out,
+ REGIO_WRITE_ENABLE_OUT => regio_rx.write, --regio_write_enable_out,
+ REGIO_DATA_OUT => regio_rx.data, --regio_data_out,
+ REGIO_DATA_IN => regio_tx.data, --regio_data_in,
+ REGIO_DATAREADY_IN => regio_tx.ack, --regio_dataready_in,
+ REGIO_NO_MORE_DATA_IN => regio_tx.nack, --regio_no_more_data_in,
+ REGIO_WRITE_ACK_IN => regio_tx.ack, --regio_write_ack_in,
+ REGIO_UNKNOWN_ADDR_IN => regio_tx.unknown, --regio_unknown_addr_in,
+ REGIO_TIMEOUT_OUT => regio_rx.timeout, --regio_timeout_out,
REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
REGIO_ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
-- RegIO Bus Handler
---------------------------------------------------------------------------
- THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler
+ THE_INTERNAL_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
PORT_NUMBER => 5,
PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7300", others => x"0000"),
PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 3, 3 => 2, 4 => 5, others => 0)
)
port map(
- CLK => CLK,
- RESET => RESET,
+ CLK => CLK,
+ RESET => RESET,
- DAT_ADDR_IN => regio_addr_i,
- DAT_DATA_IN => regio_data_out_i,
- DAT_DATA_OUT => regio_data_in_i,
- DAT_READ_ENABLE_IN => regio_read_enable_i,
- DAT_WRITE_ENABLE_IN => regio_write_enable_i,
- DAT_TIMEOUT_IN => regio_timeout_i,
- DAT_DATAREADY_OUT => regio_dataready_i,
- DAT_WRITE_ACK_OUT => regio_write_ack_i,
- DAT_NO_MORE_DATA_OUT => regio_nomoredata_i,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i,
-
---Fucking Modelsim wants it like this...
- BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,
- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,
- BUS_READ_ENABLE_OUT(2) => info_read,
- BUS_READ_ENABLE_OUT(3) => stat_handler_read,
- BUS_READ_ENABLE_OUT(4) => stat_buffer_read,
-
- BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,
- BUS_WRITE_ENABLE_OUT(1) => dummy(100),
- BUS_WRITE_ENABLE_OUT(2) => info_write,
- BUS_WRITE_ENABLE_OUT(3) => stat_handler_write,
- BUS_WRITE_ENABLE_OUT(4) => stat_buffer_write,
-
- BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,
- BUS_DATA_OUT(63 downto 32) => dummy(31 downto 0),
- BUS_DATA_OUT(95 downto 64) => info_data_in,
- BUS_DATA_OUT(127 downto 96) => dummy(63 downto 32),
- BUS_DATA_OUT(159 downto 128)=> dummy(95 downto 64),
-
- BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,
- BUS_ADDR_OUT(31 downto 16) => dbuf_addr,
- BUS_ADDR_OUT(47 downto 32) => info_addr,
- BUS_ADDR_OUT(63 downto 48) => stat_handler_addr,
- BUS_ADDR_OUT(79 downto 64) => stat_buffer_address,
-
- BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,
- BUS_TIMEOUT_OUT(1) => dummy(96),
- BUS_TIMEOUT_OUT(2) => dummy(97),
- BUS_TIMEOUT_OUT(3) => dummy(98),
- BUS_TIMEOUT_OUT(4) => dummy(99),
-
- BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,
- BUS_DATA_IN(63 downto 32) => dbuf_data_out,
- BUS_DATA_IN(95 downto 64) => info_data_out,
- BUS_DATA_IN(127 downto 96) => stat_handler_data_out,
- BUS_DATA_IN(159 downto 128)=> stat_buffer_out,
-
- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,
- BUS_DATAREADY_IN(1) => dbuf_dataready,
- BUS_DATAREADY_IN(2) => info_valid,
- BUS_DATAREADY_IN(3) => stat_handler_valid,
- BUS_DATAREADY_IN(4) => stat_buffer_ready,
-
- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,
- BUS_WRITE_ACK_IN(1) => '0',
- BUS_WRITE_ACK_IN(2) => info_wr_ack,
- BUS_WRITE_ACK_IN(3) => '0',
- BUS_WRITE_ACK_IN(4) => '0',
-
- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_NO_MORE_DATA_IN(4) => '0',
+ REGIO_RX => regio_rx,
+ REGIO_TX => regio_tx,
+
+ BUS_RX(0) => BUS_RX,
+ BUS_RX(1) => dbuf_rx,
+ BUS_RX(2) => info_rx,
+ BUS_RX(3) => stat_handler_rx,
+ BUS_RX(4) => stat_buffer_rx,
- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,
- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,
- BUS_UNKNOWN_ADDR_IN(2) => info_invalid,
- BUS_UNKNOWN_ADDR_IN(3) => stat_handler_invalid,
- BUS_UNKNOWN_ADDR_IN(4) => stat_buffer_unknown
+ BUS_TX(0) => BUS_TX,
+ BUS_TX(1) => dbuf_tx,
+ BUS_TX(2) => info_tx,
+ BUS_TX(3) => stat_handler_tx,
+ BUS_TX(4) => stat_buffer_tx
);
-stat_buffer_wr_nack <= stat_buffer_write;
-stat_buffer_unknown <= stat_buffer_wr_nack or stat_buffer_rd_nack when rising_edge(CLK);
-
---------------------------------------------------------------------------
-- registers 0x7110 ff.
---------------------------------------------------------------------------
RESET => RESET,
CLK => CLK,
DATA_IN => info_registers,
- READ_EN_IN => info_read,
+ READ_EN_IN => info_rx.read,
WRITE_EN_IN => '0',
- ADDR_IN(2 downto 0) => info_addr(2 downto 0),
+ ADDR_IN(2 downto 0) => info_rx.addr(2 downto 0),
ADDR_IN(6 downto 3) => "0000",
- DATA_OUT => info_data_out,
- DATAREADY_OUT => info_valid,
+ DATA_OUT => info_tx.data,
+ DATAREADY_OUT => info_tx.rack,
UNKNOWN_ADDR_OUT => info_rd_nack
);
-info_invalid <= info_rd_nack or info_wr_nack;
+info_tx.unknown <= info_rd_nack or info_wr_nack;
info_registers(0) <= stat_header_buffer_level;
info_registers(1) <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16)) & max_event_size;
info_registers(2) <= std_logic_vector(to_unsigned(DATA_BUFFER_FULL_THRESH,16))
proc_maxeventsize : process begin
wait until rising_edge(CLK);
+ info_tx.wack <= '0';
+ info_wr_nack <= info_rx.write;
if RESET = '1' then
max_event_size <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16));
- elsif info_write = '1' and info_addr(2 downto 0) = "001" then
- max_event_size <= info_data_in(15 downto 0);
- info_wr_ack <= '1';
- info_wr_nack <= '0';
- else
- info_wr_nack <= info_write;
+ elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "001" then
+ max_event_size <= info_rx.data(15 downto 0);
+ info_tx.wack <= '1';
+ info_tx.nack <= '0';
end if;
end process;
RESET => RESET,
CLK => CLK,
DATA_IN => stat_handler_registers,
- READ_EN_IN => stat_handler_read,
- WRITE_EN_IN => '0',
- ADDR_IN(2 downto 0) => stat_handler_addr(2 downto 0),
+ READ_EN_IN => stat_handler_rx.read,
+ WRITE_EN_IN => stat_handler_rx.write,
+ ADDR_IN(2 downto 0) => stat_handler_rx.addr(2 downto 0),
ADDR_IN(6 downto 3) => "0000",
- DATA_OUT => stat_handler_data_out,
- DATAREADY_OUT => stat_handler_valid,
- UNKNOWN_ADDR_OUT => stat_handler_invalid
+ DATA_OUT => stat_handler_tx.data,
+ DATAREADY_OUT => stat_handler_tx.ack,
+ UNKNOWN_ADDR_OUT => stat_handler_tx.unknown
);
stat_handler_registers(0) <= stat_handler_i(31 downto 0);
stat_handler_registers(1) <= stat_handler_i(63 downto 32);
STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level,
STATUS_OUT => stat_handler_i,
TIMER_TICKS_IN => time_ticks_i,
- STATISTICS_DATA_OUT => stat_buffer_out,
- STATISTICS_UNKNOWN_OUT => stat_buffer_rd_nack,
- STATISTICS_READY_OUT => stat_buffer_ready,
- STATISTICS_READ_IN => stat_buffer_read,
- STATISTICS_ADDR_IN => stat_buffer_address(4 downto 0),
+ STATISTICS_DATA_OUT => stat_buffer_tx.data,
+ STATISTICS_UNKNOWN_OUT => stat_buffer_tx.unknown,
+ STATISTICS_READY_OUT => stat_buffer_tx.ack,
+ STATISTICS_READ_IN => stat_buffer_rx.read,
+ STATISTICS_ADDR_IN => stat_buffer_rx.addr(4 downto 0),
--Debug
variable tmp : integer range 0 to 15;
begin
if rising_edge(CLK) then
- dbuf_unknown_addr <= '0';
- dbuf_dataready <= '0';
- if dbuf_read_enable = '1' then
- tmp := to_integer(unsigned(dbuf_addr(3 downto 0)));
+ dbuf_tx.nack <= '0';
+ dbuf_tx.unknown <= dbuf_rx.write;
+ dbuf_tx.ack <= '0';
+ if dbuf_rx.read = '1' then
+ tmp := to_integer(unsigned(dbuf_rx.addr(3 downto 0)));
if tmp < DATA_INTERFACE_NUMBER then
- dbuf_data_out <= stat_data_buffer_level(tmp*32+31 downto tmp*32);
- dbuf_dataready <= '1';
+ dbuf_tx.data <= stat_data_buffer_level(tmp*32+31 downto tmp*32);
+ dbuf_tx.ack <= '1';
else
- dbuf_data_out <= (others => '0');
- dbuf_unknown_addr <= '1';
+ dbuf_tx.data <= (others => '0');
+ dbuf_tx.unknown <= '1';
end if;
end if;
end if;
TIME_SINCE_LAST_TRG_OUT <= time_since_last_trg_i;
TIME_TICKS_OUT <= time_ticks_i;
- process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)
+ process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,clk)
begin
common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0);
common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12);
end if;
end process;
-end architecture;
\ No newline at end of file
+end architecture;
+
+--
+-- type CTRLBUS_TX is record
+-- data : std_logic_vector(31 downto 0);
+-- ack : std_logic;
+-- wack,rack : std_logic; --for the old-fashioned guys
+-- unknown : std_logic;
+-- nack : std_logic;
+-- end record;
+--
+-- type CTRLBUS_RX is record
+-- data : std_logic_vector(31 downto 0);
+-- addr : std_logic_vector(15 downto 0);
+-- write : std_logic;
+-- read : std_logic;
+-- timeout : std_logic;
+-- end record;
+--
+--
+-- type READOUT_RX is record
+-- data_valid : std_logic;
+-- valid_timing_trg : std_logic;
+-- valid_notiming_trg : std_logic;
+-- invalid_trg : std_logic;
+-- --
+-- trg_type : std_logic_vector( 3 downto 0);
+-- trg_number : std_logic_vector(15 downto 0);
+-- trg_code : std_logic_vector( 7 downto 0);
+-- trg_information : std_logic_vector(23 downto 0);
+-- trg_int_number : std_logic_vector(15 downto 0);
+-- --
+-- trg_multiple : std_logic;
+-- trg_timeout : std_logic;
+-- trg_spurious : std_logic;
+-- trg_missing : std_logic;
+-- trg_spike : std_logic;
+-- --
+-- buffer_almost_full : std_logic;
+-- end record;
+--
+--
+-- type READOUT_TX is record
+-- busy_release : std_logic;
+-- statusbits : std_logic_vector(31 downto 0);
+-- data : std_logic_vector(31 downto 0);
+-- data_write : std_logic;
+-- data_finished : std_logic;
+-- end record;
jspc29 / trbnet.git / commitdiff