#-- Written on Mon Aug 6 18:53:10 2012
+
#project files
-add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd"
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/2.2_x64/cae_library/synthesis/vhdl/machxo2.vhd"
add_file -vhdl -lib work "../..//trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "source/pwm.vhd"
+add_file -vhdl -lib work "cores/pll_shifted_clocks.vhd"
+add_file -vhdl -lib work "cores/fifo_1kx8.vhd"
+add_file -vhdl -lib work "source/ffarray.vhd"
add_file -vhdl -lib work "cores/oddr16.vhd"
entity panda_dirc_wasa is
generic(
PADIWA_FLAVOUR : integer := 3;
- TEMP_CORRECTION: integer := 1
+ TEMP_CORRECTION: integer := c_YES;
+ TDCTEST : integer := c_NO
);
port(
CON : out std_logic_vector(16 downto 1);
signal spi_write_i : std_logic_vector(15 downto 0);
signal buf_SPI_OUT : std_logic;
signal spi_debug_i : std_logic_vector(15 downto 0);
+signal last_spi_channel: std_logic_vector(7 downto 0);
signal pll_lock : std_logic;
signal clk_26 : std_logic;
signal temperature_i_s : std_logic_vector(11 downto 0);
signal comp_setting_s : std_logic_vector(15 downto 0);
+signal ffarr_data : std_logic_vector(15 downto 0);
+signal ffarr_read : std_logic;
+
begin
end process;
-
+gen_ffarr : if TDCTEST = 1 generate
+ THE_FFARR : entity work.ffarray
+ port map(
+ CLK => clk_i,
+ SIGNAL_IN => SPI_IN,
+
+ DATA_OUT => ffarr_data(7 downto 0),
+ READ_IN => ffarr_read,
+ EMPTY_OUT => ffarr_data(12)
+ );
+
+ process begin
+ wait until rising_edge(clk_i);
+ last_spi_channel <= spi_channel_i;
+ if spi_channel_i = x"0a" and last_spi_channel /= x"0a" then
+ ffarr_read <= '1';
+ else
+ ffarr_read <= '0';
+ end if;
+ end process;
+
+end generate;
+
---------------------------------------------------------------------------
-- Temperature Sensor
---------------------------------------------------------------------------
generic map(
USE_TEMPERATURE_READOUT => 1,
PARASITIC_MODE => c_NO,
- CLK_PERIOD => 40
+ CLK_PERIOD => 33
)
port map(
CLK => clk_26,
when x"4" => spi_reg20_i <= inp_invert;
when x"5" => spi_reg20_i <= inp_stretch;
when x"6" => spi_reg20_i <= comp_setting;
+ when x"a" => spi_reg20_i <= ffarr_data;
when others => null;
end case;
else
--- /dev/null
+FREQUENCY NET clk_i_c 133 MHz;
+
+
+
+UGROUP "ffarr0group"
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_0_0
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_1_0
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_1_1
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_1_2
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_2_0
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_2_1
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_2_2
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_3_0
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_3_1
+ BLKNAME gen_ffarr_THE_FFARR/ffarr_3_2
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_1_ffarr_0_1
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_2_ffarr_0_2
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_3_ffarr_0_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_4_ffarr_0_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_5_ffarr_0_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_6_ffarr_0_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_first_7_ffarr_0_7
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_3_ffarr_1_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_4_ffarr_1_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_5_ffarr_1_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_6_ffarr_1_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_1_gen_ffarr_i_7_ffarr_1_7
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_3_ffarr_2_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_4_ffarr_2_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_5_ffarr_2_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_6_ffarr_2_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_2_gen_ffarr_i_7_ffarr_2_7
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_3_ffarr_3_3
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_4_ffarr_3_4
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_5_ffarr_3_5
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_6_ffarr_3_6
+ BLKNAME gen_ffarr_THE_FFARR/gen_ffarr_j_3_gen_ffarr_i_7_ffarr_3_7;
+
+REGION "FFARR0" "R19C26" 2 4 DEVSIZE;
+LOCATE UGROUP "ffarr0group" REGION "FFARR0";
+
+
+USE SECONDARY NET "gen_ffarr_THE_FFARR/CLKa*";
+USE SECONDARY NET "gen_ffarr_THE_FFARR_CLKa*";
\ No newline at end of file
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity ffarray is
+ port(
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic;
+
+ DATA_OUT : out std_logic_vector(7 downto 0);
+ READ_IN : in std_logic := '0';
+ EMPTY_OUT : out std_logic := '0'
+ );
+end entity;
+
+architecture ffarray_arch of ffarray is
+
+signal CLKt : std_logic_vector(3 downto 0);
+signal CLKa : std_logic_vector(7 downto 0);
+
+signal final : std_logic_vector(7 downto 0);
+signal final_t : std_logic_vector(7 downto 0);
+
+type ffarr_t is array(0 to 3) of std_logic_vector(7 downto 0);
+signal ffarr : ffarr_t;
+
+type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0);
+signal ram : ram_t;
+
+signal fifo_write : std_logic;
+
+
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+
+ attribute syn_preserve of CLKa : signal is true;
+ attribute syn_keep of CLKa : signal is true;
+ attribute syn_preserve of CLKt : signal is true;
+ attribute syn_keep of CLKt : signal is true;
+
+
+begin
+
+THE_PLL : entity work.pll_shifted_clocks
+ port map(
+ CLKI => CLK,
+ CLKOP => CLKt(0),
+ CLKOS => CLKt(1),
+ CLKOS2 => CLKt(2),
+ CLKOS3 => CLKt(3)
+ );
+
+CLKa(3 downto 0) <= CLKt(3 downto 0) xor x"0";
+CLKa(7 downto 4) <= not CLKt(3 downto 0);
+
+gen_ffarr_first : for i in 0 to 7 generate
+ ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i));
+end generate;
+
+gen_ffarr_j : for j in 1 to 3 generate
+ gen_ffarr_i : for i in 0 to 7 generate
+ ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2,0)));
+ end generate;
+end generate;
+
+
+process begin
+ wait until rising_edge(CLK);
+ final_t <= ffarr(3);
+ if ((not and_all(final_t) and or_all(final_t)) = '1') then
+ fifo_write <= '1';
+ final <= final_t;
+ else
+ fifo_write <= '0';
+ end if;
+end process;
+
+
+THE_FIFO : entity work.fifo_1kx8
+ port map(
+ Data => final,
+ WrClock => CLK, --wrong!
+ RdClock => CLK,
+ WrEn => fifo_write,
+ RdEn => READ_IN,
+ Reset => '0',
+ RPReset => '0',
+ Q => DATA_OUT,
+ Empty => EMPTY_OUT,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open
+ );
+
+end architecture;
\ No newline at end of file
write_i <= (others => '0');
case state is
when IDLE =>
+ channel_i <= x"ff";
operation_i <= x"7";
if spi_cs_reg = '0' then
state <= WAIT_FOR_CMD;
jspc29 / trb3.git / commitdiff