MAC_RX_STAT_EN_IN : in std_logic;
MAC_RX_EOF_IN : in std_logic;
MAC_RX_ERROR_IN : in std_logic;
-
+ -- FIFO TX stuff
+ FT_TX_DATA_OUT : out std_logic_vector(8 downto 0);
+ FT_TX_WR_OUT : out std_logic;
+ FT_TX_FIFOFULL_IN : in std_logic;
-- CTS interface
CTS_NUMBER_IN : in std_logic_vector(15 downto 0);
CTS_CODE_IN : in std_logic_vector(7 downto 0);
signal ft_data : std_logic_vector(8 downto 0);
signal ft_tx_empty : std_logic;
signal ft_start_of_packet : std_logic;
- signal ft_bsm_init : std_logic_vector(3 downto 0);
- signal ft_bsm_mac : std_logic_vector(3 downto 0);
- signal ft_bsm_trans : std_logic_vector(3 downto 0);
signal gbe_cts_number : std_logic_vector(15 downto 0);
signal gbe_cts_code : std_logic_vector(7 downto 0);
signal dbg_hist, dbg_hist2 : hist_array;
signal monitor_dropped : std_logic_vector(31 downto 0);
- signal dbg_ft : std_logic_vector(63 downto 0);
- signal dbg_q : std_logic_vector(15 downto 0);
signal make_reset : std_logic;
signal frame_pause : std_logic_vector(31 downto 0);
)
port map(
-- ports for user logic
- RESET => global_reset,
- CLK => CLK_SYS_IN,
- LINK_OK_IN => '1',
+ RESET => global_reset,
+ CLK => CLK_SYS_IN,
+ LINK_OK_IN => '1',
--
- WR_EN_IN => fc_wr_en,
- DATA_IN => fc_data,
- START_OF_DATA_IN => fc_sod,
- END_OF_DATA_IN => fc_eod,
- IP_F_SIZE_IN => fc_ip_size,
- UDP_P_SIZE_IN => fc_udp_size,
- HEADERS_READY_OUT => fc_h_ready,
- READY_OUT => fc_ready,
- DEST_MAC_ADDRESS_IN => fc_dest_mac,
- DEST_IP_ADDRESS_IN => fc_dest_ip,
- DEST_UDP_PORT_IN => fc_dest_udp,
- SRC_MAC_ADDRESS_IN => fc_src_mac,
- SRC_IP_ADDRESS_IN => fc_src_ip,
- SRC_UDP_PORT_IN => fc_src_udp,
- FRAME_TYPE_IN => fc_type,
- IHL_VERSION_IN => fc_ihl_version,
- TOS_IN => fc_tos,
- IDENTIFICATION_IN => fc_ident,
- FLAGS_OFFSET_IN => fc_flags_offset,
- TTL_IN => fc_ttl,
- PROTOCOL_IN => fc_protocol,
- FRAME_DELAY_IN => frame_pause, --(others => '0'),
- RD_CLK => CLK_125_IN,
- FT_DATA_OUT => ft_data,
- FT_TX_EMPTY_OUT => ft_tx_empty,
- FT_TX_RD_EN_IN => MAC_TX_READ_IN,
- FT_START_OF_PACKET_OUT => ft_start_of_packet,
- FT_TX_DONE_IN => MAC_TX_DONE_IN,
- FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
- MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
- MONITOR_TX_FRAMES_OUT => monitor_tx_frames
+ WR_EN_IN => fc_wr_en,
+ DATA_IN => fc_data,
+ START_OF_DATA_IN => fc_sod,
+ END_OF_DATA_IN => fc_eod,
+ IP_F_SIZE_IN => fc_ip_size,
+ UDP_P_SIZE_IN => fc_udp_size,
+ HEADERS_READY_OUT => fc_h_ready,
+ READY_OUT => fc_ready,
+ DEST_MAC_ADDRESS_IN => fc_dest_mac,
+ DEST_IP_ADDRESS_IN => fc_dest_ip,
+ DEST_UDP_PORT_IN => fc_dest_udp,
+ SRC_MAC_ADDRESS_IN => fc_src_mac,
+ SRC_IP_ADDRESS_IN => fc_src_ip,
+ SRC_UDP_PORT_IN => fc_src_udp,
+ FRAME_TYPE_IN => fc_type,
+ IHL_VERSION_IN => fc_ihl_version,
+ TOS_IN => fc_tos,
+ IDENTIFICATION_IN => fc_ident,
+ FLAGS_OFFSET_IN => fc_flags_offset,
+ TTL_IN => fc_ttl,
+ PROTOCOL_IN => fc_protocol,
+ FRAME_DELAY_IN => frame_pause,
+ RD_CLK => CLK_125_IN,
+ FT_TX_DATA_OUT => FT_TX_DATA_OUT, -- BUG
+ FT_TX_WR_OUT => FT_TX_WR_OUT, -- BUG
+ FT_TX_FIFOFULL_IN => FT_TX_FIFOFULL_IN, -- BUG
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames
);
frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
- MAC_TX_DATA_OUT <= ft_data(7 downto 0);
-
- dbg_q(15 downto 9) <= (others => '0');
-
- FRAME_TRANSMITTER : trb_net16_gbe_frame_trans
- port map(
- CLK => CLK_SYS_IN,
- RESET => global_reset,
- LINK_OK_IN => link_ok,
- TX_MAC_CLK => CLK_125_IN,
- TX_EMPTY_IN => ft_tx_empty,
- START_OF_PACKET_IN => ft_start_of_packet,
- DATA_ENDFLAG_IN => ft_data(8),
- TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT,
- TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT,
- TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT,
- TX_DONE_IN => MAC_TX_DONE_IN,
- TX_STAT_EN_IN => MAC_TX_STAT_EN_IN,
- TX_STATVEC_IN => MAC_TX_STATS_IN,
- TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN,
- -- Debug
- BSM_INIT_OUT => ft_bsm_init,
- BSM_MAC_OUT => ft_bsm_mac,
- BSM_TRANS_OUT => ft_bsm_trans,
- DBG_RD_DONE_OUT => open,
- DBG_INIT_DONE_OUT => open,
- DBG_ENABLED_OUT => open,
- DEBUG_OUT => dbg_ft
- );
-
rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
port map(
);\r
port( \r
-- ports for user logic\r
- RESET : in std_logic;\r
- CLK : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ LINK_OK_IN : in std_logic; -- gk 03.08.10\r
--\r
- WR_EN_IN : in std_logic;\r
- DATA_IN : in std_logic_vector(7 downto 0);\r
- START_OF_DATA_IN : in std_logic;\r
- END_OF_DATA_IN : in std_logic;\r
- IP_F_SIZE_IN : in std_logic_vector(15 downto 0);\r
- UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation\r
- HEADERS_READY_OUT : out std_logic;\r
- READY_OUT : out std_logic;\r
- DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
- SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
- SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
- FRAME_TYPE_IN : in std_logic_vector(15 downto 0);\r
- IHL_VERSION_IN : in std_logic_vector(7 downto 0);\r
- TOS_IN : in std_logic_vector(7 downto 0);\r
- IDENTIFICATION_IN : in std_logic_vector(15 downto 0);\r
- FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);\r
- TTL_IN : in std_logic_vector(7 downto 0);\r
- PROTOCOL_IN : in std_logic_vector(7 downto 0);\r
- FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10\r
+ WR_EN_IN : in std_logic;\r
+ DATA_IN : in std_logic_vector(7 downto 0);\r
+ START_OF_DATA_IN : in std_logic;\r
+ END_OF_DATA_IN : in std_logic;\r
+ IP_F_SIZE_IN : in std_logic_vector(15 downto 0);\r
+ UDP_P_SIZE_IN : in std_logic_vector(15 downto 0); -- needed for fragmentation\r
+ HEADERS_READY_OUT : out std_logic;\r
+ READY_OUT : out std_logic;\r
+ DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
+ DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
+ DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
+ SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);\r
+ SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);\r
+ SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);\r
+ FRAME_TYPE_IN : in std_logic_vector(15 downto 0);\r
+ IHL_VERSION_IN : in std_logic_vector(7 downto 0);\r
+ TOS_IN : in std_logic_vector(7 downto 0);\r
+ IDENTIFICATION_IN : in std_logic_vector(15 downto 0);\r
+ FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);\r
+ TTL_IN : in std_logic_vector(7 downto 0);\r
+ PROTOCOL_IN : in std_logic_vector(7 downto 0);\r
+ FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10\r
-- ports for packetTransmitter\r
- RD_CLK : in std_logic; -- 125MHz clock!!!\r
- FT_DATA_OUT : out std_logic_vector(8 downto 0);\r
- FT_TX_EMPTY_OUT : out std_logic;\r
- FT_TX_RD_EN_IN : in std_logic;\r
- FT_START_OF_PACKET_OUT : out std_logic;\r
- FT_TX_DONE_IN : in std_logic;\r
- FT_TX_DISCFRM_IN : in std_logic;\r
- \r
+ RD_CLK : in std_logic; -- 125MHz clock!!!\r
+ FT_TX_DATA_OUT : out std_logic_vector(8 downto 0);\r
+ FT_TX_WR_OUT : out std_logic;\r
+ FT_TX_FIFOFULL_IN : in std_logic;\r
+ --\r
MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);\r
MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0)\r
);\r
\r
architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is\r
\r
---attribute HGROUP : string;\r
---attribute HGROUP of trb_net16_gbe_frame_constr : architecture is "GBE_LINK_group";\r
-\r
-component fifo_4096x9 is --fifo_8kx9 is\r
-port( \r
- Data : in std_logic_vector(8 downto 0);\r
- WrClock : in std_logic;\r
- RdClock : in std_logic;\r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic;\r
- RPReset : in std_logic;\r
- Q : out std_logic_vector(8 downto 0);\r
- Empty : out std_logic;\r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
-component fifo_8kx9 is\r
-port( \r
- Data : in std_logic_vector(8 downto 0);\r
- WrClock : in std_logic;\r
- RdClock : in std_logic;\r
- WrEn : in std_logic;\r
- RdEn : in std_logic;\r
- Reset : in std_logic;\r
- RPReset : in std_logic;\r
- Q : out std_logic_vector(8 downto 0);\r
- Empty : out std_logic;\r
- Full : out std_logic\r
-);\r
-end component;\r
-\r
attribute syn_encoding : string;\r
\r
type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
- TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
- SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,\r
- UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
+ TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
+ SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,\r
+ UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
signal constructCurrentState, constructNextState : constructStates;\r
signal bsm_constr : std_logic_vector(7 downto 0);\r
attribute syn_encoding of constructCurrentState: signal is "onehot";\r
\r
-type transmitStates is (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);\r
-signal transmitCurrentState, transmitNextState : transmitStates;\r
-attribute syn_encoding of transmitCurrentState : signal is "onehot";\r
-\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
signal headers_int_counter : integer range 0 to 6;\r
signal fpf_data : std_logic_vector(7 downto 0);\r
signal fpf_empty : std_logic;\r
signal fpf_full : std_logic;\r
signal fpf_wr_en : std_logic;\r
signal fpf_rd_en : std_logic;\r
+signal fpf_rd_en_q : std_logic;\r
signal fpf_q : std_logic_vector(8 downto 0);\r
signal ip_size : std_logic_vector(15 downto 0);\r
signal ip_checksum : std_logic_vector(31 downto 0);\r
signal udp_size : std_logic_vector(15 downto 0);\r
signal udp_checksum : std_logic_vector(15 downto 0);\r
-signal ft_sop : std_logic;\r
signal put_udp_headers : std_logic;\r
-signal ready_frames_ctr : std_logic_vector(15 downto 0) := x"0000";\r
-signal sent_frames_ctr : std_logic_vector(15 downto 0) := x"0000";\r
-signal debug : std_logic_vector(63 downto 0);\r
signal ready : std_logic;\r
signal headers_ready : std_logic;\r
\r
signal cur_max : integer range 0 to 10;\r
\r
-signal ready_frames_ctr_q : std_logic_vector(15 downto 0) := x"0000";\r
signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10\r
\r
signal fpf_reset : std_logic; -- gk 01.01.01\r
\r
-- Fakes\r
udp_checksum <= x"0000"; -- no checksum test needed\r
---debug <= (others => '0');\r
\r
process(CLK)\r
begin\r
- if rising_edge(CLK) then\r
- if constructCurrentState = IDLE then\r
- ready <= '1';\r
- else\r
- ready <= '0';\r
- end if;\r
- \r
- if (constructCurrentState = SAVE_DATA) then\r
- headers_ready <= '1';\r
- else\r
- headers_ready <= '0';\r
- end if;\r
- end if;\r
+if rising_edge(CLK) then\r
+ if constructCurrentState = IDLE then\r
+ ready <= '1';\r
+ else\r
+ ready <= '0';\r
+ end if;\r
+\r
+ if (constructCurrentState = SAVE_DATA) then\r
+ headers_ready <= '1';\r
+ else\r
+ headers_ready <= '0';\r
+ end if;\r
+end if;\r
end process;\r
- \r
+ \r
sizeProc: process(CLK)\r
begin\r
- if rising_edge(CLK) then\r
- if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
- ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
- udp_size <= UDP_P_SIZE_IN + x"8";\r
- else\r
- ip_size <= IP_F_SIZE_IN + x"14";\r
- udp_size <= UDP_P_SIZE_IN;\r
- end if;\r
- end if;\r
+ if rising_edge(CLK) then\r
+ if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then\r
+ ip_size <= IP_F_SIZE_IN + x"14" + x"8";\r
+ udp_size <= UDP_P_SIZE_IN + x"8";\r
+ else\r
+ ip_size <= IP_F_SIZE_IN + x"14";\r
+ udp_size <= UDP_P_SIZE_IN;\r
+ end if;\r
+ end if;\r
end process sizeProc;\r
\r
ipCsProc : process(CLK)\r
end if;\r
end process headersIntProc;\r
\r
-\r
-\r
putUdpHeadersProc : process(CLK)\r
begin\r
if rising_edge(CLK) then\r
end case;\r
end process fpfDataProc;\r
\r
-syncProc : process(CLK)\r
+syncProc : process( CLK )\r
begin\r
- if rising_edge(CLK) then\r
- fpf_data_q <= fpf_data;\r
- fpf_wr_en_q <= fpf_wr_en;\r
- fpf_eod <= END_OF_DATA_IN;\r
- end if;\r
+ if rising_edge(CLK) then\r
+ fpf_data_q <= fpf_data;\r
+ fpf_wr_en_q <= fpf_wr_en;\r
+ fpf_eod <= END_OF_DATA_IN;\r
+ end if;\r
end process syncProc;\r
- \r
-\r
-\r
-readyFramesCtrProc: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- ready_frames_ctr <= (others => '0');\r
- elsif (constructCurrentState = CLEANUP) then\r
- ready_frames_ctr <= ready_frames_ctr + 1;\r
- else\r
- ready_frames_ctr <= ready_frames_ctr;\r
- end if;\r
- end if;\r
-end process readyFramesCtrProc;\r
-\r
-fpfResetProc : process(CLK)\r
-begin\r
- if rising_edge(CLK) then\r
- if (LINK_OK_IN = '0' or RESET = '1') then\r
- fpf_reset <= '1';\r
- else\r
- fpf_reset <= '0';\r
- end if;\r
- end if;\r
-end process fpfResetProc;\r
---fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10\r
-\r
-\r
-fpf_4k_gen : if FRAME_BUFFER_SIZE = 1 generate\r
- FINAL_PACKET_FIFO: fifo_4096x9\r
- port map( \r
- Data(7 downto 0) => fpf_data_q,\r
- Data(8) => fpf_eod, --END_OF_DATA_IN,\r
- WrClock => CLK,\r
- RdClock => RD_CLK,\r
- WrEn => fpf_wr_en_q,\r
- RdEn => fpf_rd_en, --FT_TX_RD_EN_IN,\r
- Reset => fpf_reset,\r
- RPReset => fpf_reset,\r
- Q => fpf_q,\r
- Empty => fpf_empty,\r
- Full => fpf_full\r
- );\r
-end generate fpf_4k_gen;\r
-\r
-fpf_8k_gen : if FRAME_BUFFER_SIZE = 2 generate\r
- FINAL_PACKET_FIFO: fifo_8kx9\r
- port map( \r
- Data(7 downto 0) => fpf_data_q,\r
- Data(8) => fpf_eod, --END_OF_DATA_IN,\r
- WrClock => CLK,\r
- RdClock => RD_CLK,\r
- WrEn => fpf_wr_en_q,\r
- RdEn => fpf_rd_en, --FT_TX_RD_EN_IN,\r
- Reset => fpf_reset,\r
- RPReset => fpf_reset,\r
- Q => fpf_q,\r
- Empty => fpf_empty,\r
- Full => fpf_full\r
- );\r
-end generate fpf_8k_gen;\r
-\r
-fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1'))\r
- or (link_ok_125 = '0') -- clear the fifo if link is down\r
- else '0';\r
-\r
-transferToRdClock : signal_sync\r
- generic map(\r
- DEPTH => 2,\r
- WIDTH => 16\r
- )\r
- port map(\r
- RESET => RESET,\r
- D_IN => ready_frames_ctr,\r
- CLK0 => RD_CLK, --CLK,\r
- CLK1 => RD_CLK,\r
- D_OUT => ready_frames_ctr_q\r
- );\r
-\r
-process(RD_CLK)\r
-begin\r
- if rising_edge(RD_CLK) then\r
- link_ok_q <= LINK_OK_IN;\r
- link_ok_125 <= link_ok_q;\r
- end if;\r
-end process;\r
-\r
-transmitMachineProc: process( RD_CLK, RESET )\r
-begin\r
- if RESET = '1' then\r
- transmitCurrentState <= T_IDLE;\r
- elsif( rising_edge(RD_CLK) ) then\r
- if (link_ok_125 = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
-end process transmitMachineProc;\r
-\r
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN )\r
-begin\r
- case transmitCurrentState is\r
- when T_IDLE =>\r
- bsm_trans <= x"0";\r
- if( (sent_frames_ctr /= ready_frames_ctr_q) ) then\r
- transmitNextState <= T_LOAD;\r
- else\r
- transmitNextState <= T_IDLE;\r
- end if;\r
- when T_LOAD =>\r
- bsm_trans <= x"1";\r
- if( fpf_q(8) = '1' ) then\r
- transmitNextState <= T_TRANSMIT;\r
- else\r
- transmitNextState <= T_LOAD;\r
- end if;\r
- when T_TRANSMIT =>\r
- bsm_trans <= x"2";\r
- -- gk 03.08.10\r
- if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then\r
- transmitNextState <= T_CLEANUP;\r
- elsif (link_ok_125 = '0') then\r
- transmitNextState <= T_PAUSE;\r
- else\r
- transmitNextState <= T_TRANSMIT;\r
- end if;\r
- when T_PAUSE =>\r
- transmitNextState <= T_CLEANUP;\r
- when T_CLEANUP =>\r
- bsm_trans <= x"3";\r
- transmitNextState <= T_IDLE;\r
- when others =>\r
- bsm_trans <= x"f";\r
- transmitNextState <= T_IDLE;\r
- end case;\r
-end process transmitMachine;\r
-\r
-\r
\r
-sopProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if (link_ok_125 = '0') then -- gk 01.10.10\r
- ft_sop <= '0';\r
- elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then\r
- ft_sop <= '1';\r
- else\r
- ft_sop <= '0';\r
- end if;\r
- end if;\r
-end process sopProc;\r
+FT_TX_DATA_OUT(7 downto 0) <= fpf_data_q;\r
+FT_TX_DATA_OUT(8) <= fpf_eod;\r
+FT_TX_WR_OUT <= fpf_wr_en_q;\r
\r
-sentFramesCtrProc: process( RD_CLK )\r
-begin\r
- if rising_edge(RD_CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- sent_frames_ctr <= (others => '0');\r
- mon_sent_frames <= (others => '0');\r
- elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then\r
- sent_frames_ctr <= sent_frames_ctr + 1;\r
- mon_sent_frames <= mon_sent_frames + x"1";\r
- else\r
- sent_frames_ctr <= sent_frames_ctr;\r
- mon_sent_frames <= mon_sent_frames;\r
- end if;\r
- end if;\r
-end process sentFramesCtrProc;\r
-\r
-\r
-\r
-FT_DATA_OUT <= fpf_q;\r
-FT_TX_EMPTY_OUT <= fpf_empty;\r
-FT_START_OF_PACKET_OUT <= ft_sop;\r
READY_OUT <= ready;\r
HEADERS_READY_OUT <= headers_ready;\r
\r
- \r
MONITOR_TX_BYTES_OUT <= mon_sent_bytes;\r
MONITOR_TX_FRAMES_OUT <= mon_sent_frames;\r
\r
end if;\r
end process;\r
\r
-end trb_net16_gbe_frame_constr;
\ No newline at end of file
+end trb_net16_gbe_frame_constr;\r
\r
entity trb_net16_gbe_frame_trans is\r
port (\r
- CLK : in std_logic;\r
- RESET : in std_logic;\r
- LINK_OK_IN : in std_logic; -- gk 03.08.10\r
- TX_MAC_CLK : in std_logic;\r
- TX_EMPTY_IN : in std_logic;\r
- START_OF_PACKET_IN : in std_logic;\r
- DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC\r
-\r
- TX_FIFOAVAIL_OUT : out std_logic;\r
- TX_FIFOEOF_OUT : out std_logic;\r
- TX_FIFOEMPTY_OUT : out std_logic;\r
- TX_DONE_IN : in std_logic;\r
- TX_STAT_EN_IN : in std_logic;\r
- TX_STATVEC_IN : in std_logic_vector(30 downto 0);\r
- TX_DISCFRM_IN : in std_logic;\r
- -- Debug\r
- BSM_INIT_OUT : out std_logic_vector(3 downto 0);\r
- BSM_MAC_OUT : out std_logic_vector(3 downto 0);\r
- BSM_TRANS_OUT : out std_logic_vector(3 downto 0);\r
- DBG_RD_DONE_OUT : out std_logic;\r
- DBG_INIT_DONE_OUT : out std_logic;\r
- DBG_ENABLED_OUT : out std_logic;\r
- DEBUG_OUT : out std_logic_vector(63 downto 0)\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ LINK_OK_IN : in std_logic; -- gk 03.08.10\r
+ TX_MAC_CLK : in std_logic;\r
+ TX_EMPTY_IN : in std_logic;\r
+ START_OF_PACKET_IN : in std_logic;\r
+ DATA_ENDFLAG_IN : in std_logic; -- (8) is end flag, rest is only for TSMAC\r
+ \r
+ TX_FIFOAVAIL_OUT : out std_logic;\r
+ TX_FIFOEOF_OUT : out std_logic;\r
+ TX_FIFOEMPTY_OUT : out std_logic;\r
+ TX_DONE_IN : in std_logic;\r
+ TX_STAT_EN_IN : in std_logic;\r
+ TX_STATVEC_IN : in std_logic_vector(30 downto 0);\r
+ TX_DISCFRM_IN : in std_logic;\r
+ -- Debug\r
+ BSM_INIT_OUT : out std_logic_vector(3 downto 0);\r
+ BSM_MAC_OUT : out std_logic_vector(3 downto 0);\r
+ BSM_TRANS_OUT : out std_logic_vector(3 downto 0);\r
+ DBG_RD_DONE_OUT : out std_logic;\r
+ DBG_INIT_DONE_OUT : out std_logic;\r
+ DBG_ENABLED_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector(63 downto 0)\r
);\r
end trb_net16_gbe_frame_trans;\r
\r
--- FifoRd ?!?\r
-\r
architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is\r
\r
---attribute HGROUP : string;\r
---attribute HGROUP of trb_net16_gbe_frame_trans : architecture is "GBE_BUF_group";\r
-\r
-component mac_init_mem is\r
-port (\r
- Address : in std_logic_vector(5 downto 0); \r
- OutClock : in std_logic; \r
- OutClockEn : in std_logic; \r
- Reset : in std_logic; \r
- Q : out std_logic_vector(7 downto 0)\r
-);\r
-end component;\r
-\r
attribute syn_encoding : string;\r
\r
-type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);\r
-signal macInitState, macInitNextState : macInitStates;\r
-attribute syn_encoding of macInitState: signal is "onehot";\r
-signal bsm_init : std_logic_vector(3 downto 0);\r
- \r
-type macStates is (M_RESETING, M_IDLE, M_INIT);\r
-signal macCurrentState, macNextState : macStates;\r
-attribute syn_encoding of macCurrentState : signal is "onehot";\r
-signal bsm_mac : std_logic_vector(3 downto 0);\r
- \r
type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);\r
signal transmitCurrentState, transmitNextState : transmitStates;\r
attribute syn_encoding of transmitCurrentState: signal is "onehot";\r
-signal bsm_trans : std_logic_vector(3 downto 0);\r
-\r
-signal tx_fifoavail_i : std_logic;\r
-signal tx_fifoeof_i : std_logic;\r
-\r
--- host interface signals\r
-signal hcs_n_i : std_logic;\r
-signal hwrite_n_i : std_logic;\r
-signal hread_n_i : std_logic;\r
-\r
--- MAC INITIALIZATION signals\r
-signal macInitMemAddr : std_logic_vector(5 downto 0);\r
-signal macInitMemQ : std_logic_vector(7 downto 0);\r
-signal macInitMemEn : std_logic;\r
-signal reading_done : std_logic;\r
-signal init_done : std_logic;\r
-signal enabled : std_logic;\r
-signal addrSig : std_logic_vector(5 downto 0);\r
-signal addr2 : std_logic_vector(5 downto 0);\r
-signal resetAddr : std_logic;\r
-\r
-signal FifoEmpty : std_logic;\r
-signal debug : std_logic_vector(63 downto 0);\r
-signal sent_ctr : std_logic_vector(31 downto 0);\r
-signal link_ok_125 : std_logic;\r
+signal bsm_trans : std_logic_vector(3 downto 0);\r
+\r
+signal tx_fifoavail_i : std_logic;\r
+signal tx_fifoeof_i : std_logic;\r
+\r
+signal fifoempty : std_logic;\r
+signal link_ok_125 : std_logic;\r
\r
begin\r
\r
linkOkSync : pulse_sync\r
port map(\r
- CLK_A_IN => CLK,\r
- RESET_A_IN => RESET,\r
- PULSE_A_IN => LINK_OK_IN,\r
- CLK_B_IN => TX_MAC_CLK,\r
- RESET_B_IN => RESET,\r
- PULSE_B_OUT => link_ok_125\r
+ CLK_A_IN => CLK,\r
+ RESET_A_IN => RESET,\r
+ PULSE_A_IN => LINK_OK_IN,\r
+ CLK_B_IN => TX_MAC_CLK,\r
+ RESET_B_IN => RESET,\r
+ PULSE_B_OUT => link_ok_125\r
);\r
\r
--- Fakes\r
-debug(63 downto 32) <= (others => '0');\r
---debug(31 downto 0) <= sent_ctr;\r
-\r
-\r
-TransmitStateMachineProc : process (TX_MAC_CLK, reset)\r
+TransmitStateMachineProc : process( TX_MAC_CLK, RESET )\r
begin\r
- if RESET = '1' then\r
- transmitCurrentState <= T_IDLE;\r
- elsif rising_edge(TX_MAC_CLK) then\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- transmitCurrentState <= T_IDLE;\r
- else\r
- transmitCurrentState <= transmitNextState;\r
- end if;\r
- end if;\r
+ if RESET = '1' then\r
+ transmitCurrentState <= T_IDLE;\r
+ elsif rising_edge(TX_MAC_CLK) then\r
+ if (LINK_OK_IN = '0') then -- gk 01.10.10\r
+ transmitCurrentState <= T_IDLE;\r
+ else\r
+ transmitCurrentState <= transmitNextState;\r
+ end if;\r
+ end if;\r
end process TransmitStatemachineProc;\r
\r
TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN, TX_DISCFRM_IN)\r
end if;\r
end process FifoAvailProc;\r
\r
-FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, LINK_OK_IN)\r
+FifoEmptyProc : process( transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, LINK_OK_IN )\r
begin\r
- if (LINK_OK_IN = '0') then -- gk 01.10.10\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_WAITFORFIFO) then\r
- FifoEmpty <= '1';\r
- elsif (transmitCurrentState = T_TRANSMIT) then\r
- FifoEmpty <= TX_EMPTY_IN;\r
+ if ( LINK_OK_IN = '0' ) then -- gk 01.10.10\r
+ fifoempty <= '1';\r
+ elsif( transmitCurrentState = T_WAITFORFIFO ) then\r
+ fifoempty <= '1';\r
+ elsif( transmitCurrentState = T_TRANSMIT ) then\r
+ fifoempty <= TX_EMPTY_IN;\r
elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then\r
- FifoEmpty <= '0';\r
+ fifoempty <= '0';\r
else\r
- FifoEmpty <= '1';\r
+ fifoempty <= '1';\r
end if;\r
end process FifoEmptyProc;\r
\r
tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) \r
else '0';\r
- \r
-SENT_CTR_PROC : process(TX_MAC_CLK, RESET)\r
-begin\r
- if (RESET = '1') then\r
- sent_ctr <= (others => '0');\r
- elsif rising_edge(TX_MAC_CLK) then\r
- if (TX_DONE_IN = '1') and (TX_STAT_EN_IN = '1') and (TX_STATVEC_IN(0) = '1') then\r
- sent_ctr <= sent_ctr + x"1";\r
- else\r
- sent_ctr <= sent_ctr;\r
- end if;\r
- end if;\r
-end process SENT_CTR_PROC;\r
-\r
-sync1 : signal_sync\r
-generic map(\r
- WIDTH => 32,\r
- DEPTH => 2\r
-)\r
-port map (\r
- RESET => RESET,\r
- CLK0 => CLK,\r
- CLK1 => CLK,\r
- D_IN => sent_ctr,\r
- D_OUT => debug(31 downto 0)\r
-);\r
\r
TX_FIFOAVAIL_OUT <= tx_fifoavail_i;\r
TX_FIFOEOF_OUT <= tx_fifoeof_i;\r
-TX_FIFOEMPTY_OUT <= FifoEmpty;\r
+TX_FIFOEMPTY_OUT <= fifoempty;\r
\r
-BSM_INIT_OUT <= bsm_init;\r
-BSM_MAC_OUT <= bsm_mac;\r
+BSM_INIT_OUT <= (others => '0');\r
+BSM_MAC_OUT <= (others => '0');\r
BSM_TRANS_OUT <= bsm_trans;\r
-DBG_RD_DONE_OUT <= reading_done;\r
-DBG_INIT_DONE_OUT <= init_done;\r
-DBG_ENABLED_OUT <= enabled;\r
-DEBUG_OUT <= debug;\r
+DBG_RD_DONE_OUT <= '0';\r
+DBG_INIT_DONE_OUT <= '0';\r
+DBG_ENABLED_OUT <= '0';\r
+DEBUG_OUT <= (others => '0');\r
\r
end trb_net16_gbe_frame_trans;\r
link_next_state <= INACTIVE;
else
if (link_ok_timeout_ctr = x"ffff") then
- link_next_state <= ENABLE_MAC; --FINALIZE;
+ link_next_state <= ENABLE_MAC;
else
link_next_state <= TIMEOUT;
end if;
if (PCS_AN_COMPLETE_IN = '0') then
link_next_state <= INACTIVE;
elsif (MAC_READY_CONF_IN = '1') then
- link_next_state <= FINALIZE; --INACTIVE;
+ link_next_state <= FINALIZE;
else
link_next_state <= ENABLE_MAC;
end if;
if (PCS_AN_COMPLETE_IN = '0') then
link_next_state <= INACTIVE;
else
- link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
+ link_next_state <= WAIT_FOR_BOOT;
end if;
when WAIT_FOR_BOOT =>
end if;
end process LINK_OK_CTR_PROC;
- link_ok <= '1';
+ link_ok <= '1'; -- BUG - what the fuck?
WAIT_CTR_PROC : process(CLK)
begin
);
end component;
---component trb_net16_gbe_protocol_selector is
---generic(
--- RX_PATH_ENABLE : integer range 0 to 1 := 1;
--- DO_SIMULATION : integer range 0 to 1 := 0;
---
--- INCLUDE_READOUT : std_logic := '0';
--- INCLUDE_SLOWCTRL : std_logic := '0';
--- INCLUDE_DHCP : std_logic := '0';
--- INCLUDE_ARP : std_logic := '0';
--- INCLUDE_PING : std_logic := '0';
---
--- READOUT_BUFFER_SIZE : integer range 1 to 4;
--- SLOWCTRL_BUFFER_SIZE : integer range 1 to 4
--- );
---port (
--- CLK : in std_logic; -- system clock
--- RESET : in std_logic;
--- RESET_FOR_DHCP : in std_logic;
---
----- signals to/from main controller
--- PS_DATA_IN : in std_logic_vector(8 downto 0);
--- PS_WR_EN_IN : in std_logic;
--- PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
--- PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
--- PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
--- PS_RESPONSE_READY_OUT : out std_logic;
---
--- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
--- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
--- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
--- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
--- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
--- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
---
----- singals to/from transmi controller with constructed response
--- TC_DATA_OUT : out std_logic_vector(8 downto 0);
--- TC_RD_EN_IN : in std_logic;
--- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
--- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
--- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
--- TC_IDENT_OUT : out std_logic_vector(15 downto 0);
--- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
--- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
--- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
--- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
--- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
--- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
--- MC_BUSY_IN : in std_logic;
---
--- -- misc signals for response constructors
--- MY_MAC_IN : in std_logic_vector(47 downto 0);
--- MY_IP_OUT : out std_logic_vector(31 downto 0);
--- DHCP_START_IN : in std_logic;
--- DHCP_DONE_OUT : out std_logic;
---
--- GSC_CLK_IN : in std_logic;
--- GSC_INIT_DATAREADY_OUT : out std_logic;
--- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
--- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
--- GSC_INIT_READ_IN : in std_logic;
--- GSC_REPLY_DATAREADY_IN : in std_logic;
--- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
--- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
--- GSC_REPLY_READ_OUT : out std_logic;
--- GSC_BUSY_IN : in std_logic;
---
--- MAKE_RESET_OUT : out std_logic;
---
--- -- signal for data readout
--- -- CTS interface
--- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
--- CTS_CODE_IN : in std_logic_vector (7 downto 0);
--- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
--- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
--- CTS_START_READOUT_IN : in std_logic;
--- CTS_DATA_OUT : out std_logic_vector (31 downto 0);
--- CTS_DATAREADY_OUT : out std_logic;
--- CTS_READOUT_FINISHED_OUT : out std_logic;
--- CTS_READ_IN : in std_logic;
--- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0);
--- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
--- -- Data payload interface
--- FEE_DATA_IN : in std_logic_vector (15 downto 0);
--- FEE_DATAREADY_IN : in std_logic;
--- FEE_READ_OUT : out std_logic;
--- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
--- FEE_BUSY_IN : in std_logic;
--- -- ip configurator
--- SLV_ADDR_IN : in std_logic_vector(7 downto 0);
--- SLV_READ_IN : in std_logic;
--- SLV_WRITE_IN : in std_logic;
--- SLV_BUSY_OUT : out std_logic;
--- SLV_ACK_OUT : out std_logic;
--- SLV_DATA_IN : in std_logic_vector(31 downto 0);
--- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
---
--- CFG_GBE_ENABLE_IN : in std_logic;
--- CFG_IPU_ENABLE_IN : in std_logic;
--- CFG_MULT_ENABLE_IN : in std_logic;
--- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0);
--- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0);
--- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0);
--- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0);
--- CFG_READOUT_CTR_VALID_IN : in std_logic;
--- CFG_INSERT_TTYPE_IN : in std_logic;
--- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0);
--- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0);
--- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0);
--- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0);
---
--- CFG_ADDITIONAL_HDR_IN : in std_logic;
--- CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
---
--- -- input for statistics from outside
--- STAT_DATA_IN : in std_logic_vector(31 downto 0);
--- STAT_ADDR_IN : in std_logic_vector(7 downto 0);
--- STAT_DATA_RDY_IN : in std_logic;
--- STAT_DATA_ACK_OUT : out std_logic;
---
--- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
--- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
---
--- DATA_HIST_OUT : out hist_array;
--- SCTRL_HIST_OUT : out hist_array
---);
---end component;
-
component trb_net16_gbe_mac_control is
port (
CLK : in std_logic; -- system clock
FRAME_DELAY_IN : in std_logic_vector(31 downto 0);
-- ports for packetTransmitter
RD_CLK : in std_logic; -- 125MHz clock!!!
- FT_DATA_OUT : out std_logic_vector(8 downto 0);
- FT_TX_EMPTY_OUT : out std_logic;
- FT_TX_RD_EN_IN : in std_logic;
- FT_START_OF_PACKET_OUT : out std_logic;
- FT_TX_DONE_IN : in std_logic;
- FT_TX_DISCFRM_IN : in std_logic;
+----------------------------
+ FT_TX_DATA_OUT : out std_logic_vector(8 downto 0);
+ FT_TX_WR_OUT : out std_logic;
+ FT_TX_FIFOFULL_IN : in std_logic;
+-- FT_DATA_OUT : out std_logic_vector(8 downto 0);
+-- FT_TX_EMPTY_OUT : out std_logic;
+-- FT_TX_RD_EN_IN : in std_logic;
+-- FT_START_OF_PACKET_OUT : out std_logic;
+-- FT_TX_DONE_IN : in std_logic;
+-- FT_TX_DISCFRM_IN : in std_logic;
MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0);
MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0)
\r
begin\r
\r
- -- FrameActice signal - used to inhibt acceptance of runt frames\r
+ -- FrameActice signal - used to inhibit acceptance of runt frames\r
THE_FRAME_ACTIVE_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
WREN => fifo_wr,\r
RDEN => MAC_TX_READ_IN,\r
RESET => RESET,\r
- Q(8) => mac_fifoeof,\r
+ Q(8) => mac_fifoeof, -- potential bug!!!!\r
Q(7 downto 0) => MAC_TX_DATA_OUT,\r
EMPTY => MAC_FIFOEMPTY_OUT, \r
FULL => open,\r
CLK_125 : in std_logic;
-- FIFO interface RX
FIFO_DATA_OUT : out std_logic_vector(4 * 9 - 1 downto 0);
- FIFO_FULL_IN : in std_logic_vector(3 downto 0);
+ FIFO_FULL_IN : in std_logic_vector(3 downto 0) := (others => '0');
FIFO_WR_OUT : out std_logic_vector(3 downto 0);
- FRAME_REQ_IN : in std_logic_vector(3 downto 0);
+ FRAME_REQ_IN : in std_logic_vector(3 downto 0) := (others => '0');
FRAME_ACK_OUT : out std_logic_vector(3 downto 0);
FRAME_AVAIL_OUT : out std_logic_vector(3 downto 0);
FRAME_START_OUT : out std_logic_vector(3 downto 0);
-- FIFO interface TX
FIFO_FULL_OUT : out std_logic_vector(3 downto 0);
- FIFO_WR_IN : in std_logic_vector(3 downto 0);
- FIFO_DATA_IN : in std_logic_vector(4 * 9 - 1 downto 0);
- FRAME_START_IN : in std_logic_vector(3 downto 0);
+ FIFO_WR_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ FIFO_DATA_IN : in std_logic_vector(4 * 9 - 1 downto 0) := (others => '0');
+ FRAME_START_IN : in std_logic_vector(3 downto 0) := (others => '0');
-- SFP Connection
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0) := (others => '0');
SD_LOS_IN : in std_logic_vector(3 downto 0) := (others => '0');
TX_PCS_RST_IN : in std_logic;
RX_LINK_READY_OUT : out std_logic_vector(3 downto 0);
TX_LINK_READY_IN : in std_logic;
+ PCS_AN_READY_OUT : out std_logic_vector(3 downto 0); -- for internal SCTRL
+ LINK_ACTIVE_OUT : out std_logic_vector(3 downto 0); -- for internal SCTRL
-- Debug
STATUS_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
DEBUG_OUT : out std_logic_vector(63 downto 0)
signal led_activity_x : std_logic_vector(3 downto 0);
signal led_activity : std_logic_vector(4 * 2 - 1 downto 0);
- attribute HGROUP : string;
+-- attribute HGROUP : string;
-- attribute BBOX : string;
- attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
+-- attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
-- attribute BBOX of ddmtd_arch : architecture is "2,2";
begin
--
DEBUG => open
);
+
+ PCS_AN_READY_OUT(i) <= an_complete(i); -- needed for internal SCTRL
+ LINK_ACTIVE_OUT(i) <= link_active(i);
-- LED connections, can be simplified by CE signal, to get rid of local counter instances
led_activity_x(i) <= pcs_rx_en(i) or pcs_tx_en(i);
rx_pcs_rst_q(i) <= '1';
rx_serdes_rst_q(i) <= '1';
+ PCS_AN_READY_OUT(i) <= '0';
+ LINK_ACTIVE_OUT(i) <= '0';
+
-- Status signals
STATUS_OUT(i * 8 + 7) <= '0'; -- unused
STATUS_OUT(i * 8 + 6) <= '0'; -- link is active
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_ARITH.all;
+use IEEE.std_logic_UNSIGNED.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+
+entity gbe_wrapper_fifo is
+ generic(
+ DO_SIMULATION : integer range 0 to 1 := 0;
+ INCLUDE_DEBUG : integer range 0 to 1 := 0;
+ USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
+ USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0; -- only for debugging
+ RX_PATH_ENABLE : integer range 0 to 1 := 1; --
+ FIXED_SIZE_MODE : integer range 0 to 1 := 1; -- only for debugging
+ INCREMENTAL_MODE : integer range 0 to 1 := 0; -- only for debugging
+ FIXED_SIZE : integer range 0 to 65535 := 10; -- only for debugging
+ FIXED_DELAY_MODE : integer range 0 to 1 := 1; -- only for debugging
+ UP_DOWN_MODE : integer range 0 to 1 := 0; -- only for debugging
+ UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; -- only for debugging
+ FIXED_DELAY : integer range 0 to 16777215 := 16777215; -- only for debugging
+ LINK_HAS_PING : std_logic := '1';
+ LINK_HAS_ARP : std_logic := '1';
+ LINK_HAS_DHCP : std_logic := '1';
+ LINK_HAS_READOUT : std_logic := '1';
+ LINK_HAS_SLOWCTRL : std_logic := '1';
+ LINK_HAS_FWD : std_logic := '1'
+ );
+ port(
+ CLK_SYS_IN : in std_logic;
+ CLK_125_IN : in std_logic;
+ RESET : in std_logic;
+ GSR_N : in std_logic;
+ -- we connect to FIFO interface directly
+ -- FIFO interface RX
+ FIFO_DATA_OUT : out std_logic_vector(8 downto 0);
+ FIFO_FULL_IN : in std_logic;
+ FIFO_WR_OUT : out std_logic;
+ FRAME_REQ_IN : in std_logic;
+ FRAME_ACK_OUT : out std_logic;
+ FRAME_AVAIL_OUT : out std_logic;
+ FRAME_START_OUT : out std_logic;
+ -- FIFO interface TX
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_WR_IN : in std_logic;
+ FIFO_DATA_IN : in std_logic_vector(8 downto 0);
+ FRAME_START_IN : in std_logic;
+ --
+ PCS_AN_READY_IN : in std_logic;
+ LINK_ACTIVE_IN : in std_logic;
+ --
+ TRIGGER_IN : in std_logic; -- for debug purpose only
+ -- CTS interface
+ CTS_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ CTS_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ CTS_INFORMATION_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0');
+ CTS_START_READOUT_IN : in std_logic := '0';
+ CTS_DATA_OUT : out std_logic_vector(31 downto 0);
+ CTS_DATAREADY_OUT : out std_logic;
+ CTS_READOUT_FINISHED_OUT : out std_logic;
+ CTS_READ_IN : in std_logic := '0';
+ CTS_LENGTH_OUT : out std_logic_vector(15 downto 0);
+ CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
+ -- Data payload interface
+ FEE_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ FEE_DATAREADY_IN : in std_logic := '0';
+ FEE_READ_OUT : out std_logic;
+ FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FEE_BUSY_IN : in std_logic := '0';
+ -- SlowControl
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0);
+ ISSUE_REBOOT_OUT : out std_logic;
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- IP configuration
+ BUS_IP_RX : in CTRLBUS_RX;
+ BUS_IP_TX : out CTRLBUS_TX;
+ -- Registers config
+ BUS_REG_RX : in CTRLBUS_RX;
+ BUS_REG_TX : out CTRLBUS_TX;
+ -- Forwarder
+ FWD_DST_MAC_IN : in std_logic_vector(47 downto 0) := (others => '0');
+ FWD_DST_IP_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FWD_DST_UDP_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ FWD_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ FWD_DATA_VALID_IN : in std_logic := '0';
+ FWD_SOP_IN : in std_logic := '0';
+ FWD_EOP_IN : in std_logic := '0';
+ FWD_READY_OUT : out std_logic;
+ FWD_FULL_OUT : out std_logic;
+ --
+ MAKE_RESET_OUT : out std_logic;
+ --
+ STATUS_OUT : out std_logic_vector(15 downto 0);
+ DEBUG_OUT : out std_logic_vector(127 downto 0)
+ );
+end entity gbe_wrapper_fifo;
+
+architecture RTL of gbe_wrapper_fifo is
+
+ signal cfg_gbe_enable : std_logic;
+ signal cfg_ipu_enable : std_logic;
+ signal cfg_mult_enable : std_logic;
+ signal cfg_subevent_id : std_logic_vector(31 downto 0);
+ signal cfg_subevent_dec : std_logic_vector(31 downto 0);
+ signal cfg_queue_dec : std_logic_vector(31 downto 0);
+ signal cfg_readout_ctr : std_logic_vector(23 downto 0);
+ signal cfg_readout_ctr_valid : std_logic;
+ signal cfg_insert_ttype : std_logic;
+ signal cfg_max_sub : std_logic_vector(15 downto 0);
+ signal cfg_max_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
+ signal cfg_max_single_sub : std_logic_vector(15 downto 0);
+ signal cfg_additional_hdr : std_logic;
+ signal cfg_soft_rst : std_logic;
+ signal cfg_allow_rx : std_logic;
+ signal cfg_max_frame : std_logic_vector(15 downto 0);
+
+ signal dbg_hist, dbg_hist2 : hist_array;
+
+ signal mac_0 : std_logic_vector(47 downto 0);
+ signal cfg_max_reply : std_logic_vector(31 downto 0);
+
+ signal mlt_cts_number : std_logic_vector(15 downto 0);
+ signal mlt_cts_code : std_logic_vector(7 downto 0);
+ signal mlt_cts_information : std_logic_vector(7 downto 0);
+ signal mlt_cts_readout_type : std_logic_vector(3 downto 0);
+ signal mlt_cts_start_readout : std_logic_vector(0 downto 0);
+ signal mlt_cts_data : std_logic_vector(31 downto 0);
+ signal mlt_cts_dataready : std_logic_vector(0 downto 0);
+ signal mlt_cts_readout_finished : std_logic_vector(0 downto 0);
+ signal mlt_cts_read : std_logic_vector(0 downto 0);
+ signal mlt_cts_length : std_logic_vector(15 downto 0);
+ signal mlt_cts_error_pattern : std_logic_vector(31 downto 0);
+ signal mlt_fee_data : std_logic_vector(15 downto 0);
+ signal mlt_fee_dataready : std_logic_vector(0 downto 0);
+ signal mlt_fee_read : std_logic_vector(0 downto 0);
+ signal mlt_fee_status : std_logic_vector(31 downto 0);
+ signal mlt_fee_busy : std_logic_vector(0 downto 0);
+
+ signal mlt_gsc_clk : std_logic;
+ signal mlt_gsc_init_dataready : std_logic;
+ signal mlt_gsc_init_data : std_logic_vector(15 downto 0);
+ signal mlt_gsc_init_packet : std_logic_vector(2 downto 0);
+ signal mlt_gsc_init_read : std_logic;
+ signal mlt_gsc_reply_dataready : std_logic;
+ signal mlt_gsc_reply_data : std_logic_vector(15 downto 0);
+ signal mlt_gsc_reply_packet : std_logic_vector(2 downto 0);
+ signal mlt_gsc_reply_read : std_logic;
+ signal mlt_gsc_busy : std_logic;
+
+ signal local_cts_number : std_logic_vector(15 downto 0);
+ signal local_cts_code : std_logic_vector(7 downto 0);
+ signal local_cts_information : std_logic_vector(7 downto 0);
+ signal local_cts_readout_type : std_logic_vector(3 downto 0);
+ signal local_cts_start_readout : std_logic;
+ signal local_cts_readout_finished : std_logic;
+ signal local_cts_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_data : std_logic_vector(15 downto 0);
+ signal local_fee_dataready : std_logic;
+ signal local_fee_read : std_logic;
+ signal local_fee_status_bits : std_logic_vector(31 downto 0);
+ signal local_fee_busy : std_logic;
+ signal dhcp_done : std_logic;
+ signal all_links_ready : std_logic;
+ signal monitor_rx_frames : std_logic_vector(31 downto 0);
+ signal monitor_rx_bytes : std_logic_vector(31 downto 0);
+ signal monitor_tx_frames : std_logic_vector(31 downto 0);
+ signal monitor_tx_bytes : std_logic_vector(31 downto 0);
+ signal monitor_tx_packets : std_logic_vector(31 downto 0);
+ signal monitor_dropped : std_logic_vector(31 downto 0);
+ signal sum_rx_frames : std_logic_vector(31 downto 0);
+ signal sum_rx_bytes : std_logic_vector(31 downto 0);
+ signal sum_tx_frames : std_logic_vector(31 downto 0);
+ signal sum_tx_bytes : std_logic_vector(31 downto 0);
+ signal sum_tx_packets : std_logic_vector(31 downto 0);
+ signal sum_dropped : std_logic_vector(31 downto 0);
+
+ signal busip0 : CTRLBUS_TX;
+
+ signal dummy_event : std_logic_vector(15 downto 0);
+ signal dummy_mode : std_logic;
+ signal make_reset0 : std_logic := '0';
+ signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+
+ signal cfg_autothrottle : std_logic;
+ signal cfg_throttle_pause : std_logic_vector(15 downto 0);
+
+ signal issue_reboot : std_logic;
+ signal my_ip : std_logic_vector(127 downto 0);
+ signal debug : std_logic_vector(127 downto 0);
+
+ signal frame_active : std_Logic;
+ signal frame_written : std_logic;
+ signal rx_fifo_wr : std_logic;
+ signal frame_requested : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_data : std_logic_vector(8 downto 0);
+ signal tx_data_read : std_Logic;
+ signal normal_read_ack : std_logic;
+ signal empty_read_ack : std_Logic;
+ signal fifo_wr_int : std_logic;
+ signal sof_int : std_logic;
+ signal tx_done_int : std_logic_vector(7 downto 0);
+
+ signal ft_tx_data : std_logic_vector(8 downto 0);
+ signal ft_tx_wr : std_logic;
+ signal ft_tx_fifofull : std_logic;
+
+begin
+
+ -------------------------------------------------------------------------------------------------
+ -- FrameActice signal - used to inhibit acceptance of runt frames
+ THE_FRAME_ACTIVE_PROC: process( CLK_125_IN )
+ begin
+ if( rising_edge(CLK_125_IN) ) then
+ if ( RESET = '1' ) then
+ frame_active <= '0';
+ elsif( FRAME_START_IN = '1' ) then
+ frame_active <= LINK_ACTIVE_IN;
+ elsif( frame_written = '1' ) then
+ frame_active <= '0';
+ end if;
+ end if;
+ end process THE_FRAME_ACTIVE_PROC;
+
+ -- one frame written to FIFO
+ frame_written <= '1' when (FIFO_DATA_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0';
+
+ rx_fifo_wr <= FIFO_WR_IN and frame_active;
+ -------------------------------------------------------------------------------------------------
+ THE_FRAME_TX: entity rx_rb
+ port map(
+ CLK => CLK_125_IN,
+ RESET => RESET,
+ -- MAC interface (RX)
+ MAC_RX_DATA_IN => ft_tx_data(7 downto 0),
+ MAC_RX_WR_IN => ft_tx_wr,
+ MAC_RX_EOF_IN => ft_tx_data(8),
+ MAC_RX_ERROR_IN => '0',
+ MAC_RX_FIFOFULL_OUT => ft_tx_fifofull,
+ -- FIFO interface (TX)
+ FIFO_FULL_IN => FIFO_FULL_IN,
+ FIFO_WR_OUT => FIFO_WR_OUT,
+ FIFO_Q_OUT => FIFO_DATA_OUT,
+ FRAME_REQ_IN => FRAME_REQ_IN,
+ FRAME_ACK_OUT => FRAME_ACK_OUT,
+ FRAME_AVAIL_OUT => FRAME_AVAIL_OUT,
+ FRAME_START_OUT => FRAME_START_OUT,
+ --
+ DEBUG => open
+ );
+
+ -------------------------------------------------------------------------------------------------
+ -- debug(127 downto 64) are local
+ -- debug(63 downto 0) are media interface
+ DEBUG_OUT <= debug;
+
+ mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+
+ all_links_ready <= '1' when dhcp_done = '1' else '0';
+
+ MAKE_RESET_OUT <= '1' when make_reset0 = '1' else '0';
+
+ ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
+
+ STATUS_OUT(7 downto 0) <= (others => '0');
+ STATUS_OUT(8) <= dhcp_done; -- DHCP has completed
+ STATUS_OUT(15 downto 9) <= (others => '0');
+
+ gbe_inst : entity work.gbe_logic_wrapper
+ generic map(DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+ RX_PATH_ENABLE => RX_PATH_ENABLE,
+ INCLUDE_READOUT => LINK_HAS_READOUT,
+ INCLUDE_SLOWCTRL => LINK_HAS_SLOWCTRL,
+ INCLUDE_DHCP => LINK_HAS_DHCP,
+ INCLUDE_ARP => LINK_HAS_ARP,
+ INCLUDE_PING => LINK_HAS_PING,
+ INCLUDE_FWD => LINK_HAS_FWD,
+ FRAME_BUFFER_SIZE => 1,
+ READOUT_BUFFER_SIZE => 4,
+ SLOWCTRL_BUFFER_SIZE => 2,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY => FIXED_DELAY)
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ CLK_125_IN => CLK_125_IN,
+ CLK_RX_125_IN => CLK_125_IN,
+ RESET => RESET,
+ GSR_N => GSR_N,
+ MY_MAC_IN => mac_0,
+ DHCP_DONE_OUT => dhcp_done,
+ MY_IP_OUT => my_ip(31 downto 0),
+ MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN,
+ ISSUE_REBOOT_OUT => issue_reboot,
+ MAC_READY_CONF_IN => LINK_ACTIVE_IN, -- NEEDED
+ MAC_RECONF_OUT => open, -- NEEDED
+ MAC_AN_READY_IN => PCS_AN_READY_IN, -- NEEDED
+ MAC_FIFOAVAIL_OUT => open, -- NEEDED
+ MAC_FIFOEOF_OUT => open, -- NEEDED
+ MAC_FIFOEMPTY_OUT => open, -- NEEDED
+ MAC_RX_FIFOFULL_OUT => FIFO_FULL_OUT, -- NEEDED -- BUG: check level
+ MAC_TX_DATA_OUT => open, -- NEEDED
+ MAC_TX_READ_IN => '0', -- NEEDED
+ MAC_TX_DISCRFRM_IN => '0', -- NEEDED
+ MAC_TX_STAT_EN_IN => '0', -- NEEDED
+ MAC_TX_STATS_IN => (others => '0'), -- NEEDED
+ MAC_TX_DONE_IN => '0', -- NEEDED
+ MAC_RX_FIFO_ERR_IN => '0', -- NEEDED
+ MAC_RX_STATS_IN => (others => '0'), -- done
+ MAC_RX_DATA_IN => FIFO_DATA_IN(7 downto 0), -- NEEDED
+ MAC_RX_WRITE_IN => rx_fifo_wr, -- NEEDED
+ MAC_RX_STAT_EN_IN => '0', -- NEEDED
+ MAC_RX_EOF_IN => FIFO_DATA_IN(8), -- NEEDED
+ MAC_RX_ERROR_IN => '0', -- NEEDED
+----
+ -- FIFO TX stuff
+ FT_TX_DATA_OUT => ft_tx_data,
+ FT_TX_WR_OUT => ft_tx_wr,
+ FT_TX_FIFOFULL_IN => ft_tx_fifofull,
+----
+ CTS_NUMBER_IN => mlt_cts_number,
+ CTS_CODE_IN => mlt_cts_code,
+ CTS_INFORMATION_IN => mlt_cts_information,
+ CTS_READOUT_TYPE_IN => mlt_cts_readout_type,
+ CTS_START_READOUT_IN => mlt_cts_start_readout(0),
+ CTS_DATA_OUT => mlt_cts_data,
+ CTS_DATAREADY_OUT => mlt_cts_dataready(0),
+ CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
+ CTS_READ_IN => mlt_cts_read(0),
+ CTS_LENGTH_OUT => mlt_cts_length,
+ CTS_ERROR_PATTERN_OUT => mlt_cts_error_pattern,
+ FEE_DATA_IN => mlt_fee_data,
+ FEE_DATAREADY_IN => mlt_fee_dataready(0),
+ FEE_READ_OUT => mlt_fee_read(0),
+ FEE_STATUS_BITS_IN => mlt_fee_status,
+ FEE_BUSY_IN => mlt_fee_busy(0),
+ GSC_CLK_IN => mlt_gsc_clk,
+ GSC_INIT_DATAREADY_OUT => mlt_gsc_init_dataready,
+ GSC_INIT_DATA_OUT => mlt_gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => mlt_gsc_init_packet,
+ GSC_INIT_READ_IN => mlt_gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => mlt_gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => mlt_gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => mlt_gsc_reply_packet,
+ GSC_REPLY_READ_OUT => mlt_gsc_reply_read,
+ GSC_BUSY_IN => mlt_gsc_busy,
+ SLV_ADDR_IN => BUS_IP_RX.addr(7 downto 0),
+ SLV_READ_IN => BUS_IP_RX.read,
+ SLV_WRITE_IN => BUS_IP_RX.write,
+ SLV_BUSY_OUT => busip0.nack,
+ SLV_ACK_OUT => busip0.ack,
+ SLV_DATA_IN => BUS_IP_RX.data,
+ SLV_DATA_OUT => busip0.data,
+ CFG_GBE_ENABLE_IN => cfg_gbe_enable,
+ CFG_IPU_ENABLE_IN => cfg_ipu_enable,
+ CFG_MULT_ENABLE_IN => cfg_mult_enable,
+ CFG_MAX_FRAME_IN => cfg_max_frame,
+ CFG_ALLOW_RX_IN => cfg_allow_rx,
+ CFG_SOFT_RESET_IN => cfg_soft_rst,
+ CFG_SUBEVENT_ID_IN => cfg_subevent_id,
+ CFG_SUBEVENT_DEC_IN => cfg_subevent_dec,
+ CFG_QUEUE_DEC_IN => cfg_queue_dec,
+ CFG_READOUT_CTR_IN => cfg_readout_ctr,
+ CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+ CFG_INSERT_TTYPE_IN => cfg_insert_ttype,
+ CFG_MAX_SUB_IN => cfg_max_sub,
+ CFG_MAX_QUEUE_IN => cfg_max_queue,
+ CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+ CFG_MAX_SINGLE_SUB_IN => cfg_max_single_sub,
+ CFG_ADDITIONAL_HDR_IN => cfg_additional_hdr,
+ CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
+ CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
+ CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+ FWD_DST_MAC_IN => FWD_DST_MAC_IN,
+ FWD_DST_IP_IN => FWD_DST_IP_IN,
+ FWD_DST_UDP_IN => FWD_DST_UDP_IN,
+ FWD_DATA_IN => FWD_DATA_IN,
+ FWD_DATA_VALID_IN => FWD_DATA_VALID_IN,
+ FWD_SOP_IN => FWD_SOP_IN,
+ FWD_EOP_IN => FWD_EOP_IN,
+ FWD_READY_OUT => FWD_READY_OUT,
+ FWD_FULL_OUT => FWD_FULL_OUT,
+ MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
+ MONITOR_RX_BYTES_OUT => monitor_rx_bytes,
+ MONITOR_TX_FRAMES_OUT => monitor_tx_frames,
+ MONITOR_TX_BYTES_OUT => monitor_tx_bytes,
+ MONITOR_TX_PACKETS_OUT => monitor_tx_packets,
+ MONITOR_DROPPED_OUT => monitor_dropped,
+ MONITOR_GEN_DBG_OUT => monitor_gen_dbg,
+ MAKE_RESET_OUT => make_reset0
+ );
+
+ BUS_IP_TX.ack <= busip0.ack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
+ BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
+
+ real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => "000" & LINK_HAS_READOUT,
+ NUMBER_OF_GBE_LINKS => 1
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+ end generate real_ipu_gen;
+
+ dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
+ ipu_mult : entity work.gbe_ipu_multiplexer
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ INCLUDE_DEBUG => INCLUDE_DEBUG,
+ LINK_HAS_READOUT => LINK_HAS_READOUT,
+ NUMBER_OF_GBE_LINKS => 1
+ )
+ port map(
+ CLK_SYS_IN => CLK_SYS_IN,
+ RESET => RESET,
+ CTS_NUMBER_IN => local_cts_number,
+ CTS_CODE_IN => local_cts_code,
+ CTS_INFORMATION_IN => local_cts_information,
+ CTS_READOUT_TYPE_IN => local_cts_readout_type,
+ CTS_START_READOUT_IN => local_cts_start_readout,
+ CTS_DATA_OUT => open,
+ CTS_DATAREADY_OUT => open,
+ CTS_READOUT_FINISHED_OUT => local_cts_readout_finished,
+ CTS_READ_IN => '1',
+ CTS_LENGTH_OUT => open,
+ CTS_ERROR_PATTERN_OUT => local_cts_status_bits,
+ FEE_DATA_IN => local_fee_data,
+ FEE_DATAREADY_IN => local_fee_dataready,
+ FEE_READ_OUT => local_fee_read,
+ FEE_STATUS_BITS_IN => local_fee_status_bits,
+ FEE_BUSY_IN => local_fee_busy,
+ MLT_CTS_NUMBER_OUT => mlt_cts_number,
+ MLT_CTS_CODE_OUT => mlt_cts_code,
+ MLT_CTS_INFORMATION_OUT => mlt_cts_information,
+ MLT_CTS_READOUT_TYPE_OUT => mlt_cts_readout_type,
+ MLT_CTS_START_READOUT_OUT => mlt_cts_start_readout,
+ MLT_CTS_DATA_IN => mlt_cts_data,
+ MLT_CTS_DATAREADY_IN => mlt_cts_dataready,
+ MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+ MLT_CTS_READ_OUT => mlt_cts_read,
+ MLT_CTS_LENGTH_IN => mlt_cts_length,
+ MLT_CTS_ERROR_PATTERN_IN => mlt_cts_error_pattern,
+ MLT_FEE_DATA_OUT => mlt_fee_data,
+ MLT_FEE_DATAREADY_OUT => mlt_fee_dataready,
+ MLT_FEE_READ_IN => mlt_fee_read,
+ MLT_FEE_STATUS_BITS_OUT => mlt_fee_status,
+ MLT_FEE_BUSY_OUT => mlt_fee_busy,
+ DEBUG_OUT => open
+ );
+
+ dummy : entity work.gbe_ipu_dummy
+ generic map(
+ DO_SIMULATION => DO_SIMULATION,
+ FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+ INCREMENTAL_MODE => INCREMENTAL_MODE,
+ FIXED_SIZE => FIXED_SIZE,
+ UP_DOWN_MODE => UP_DOWN_MODE,
+ UP_DOWN_LIMIT => UP_DOWN_LIMIT,
+ FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+ FIXED_DELAY => FIXED_DELAY
+ )
+ port map(
+ clk => CLK_SYS_IN,
+ rst => RESET,
+ GBE_READY_IN => all_links_ready,
+ CFG_EVENT_SIZE_IN => dummy_event,
+ CFG_TRIGGERED_MODE_IN => '0',
+ TRIGGER_IN => TRIGGER_IN,
+ CTS_NUMBER_OUT => local_cts_number,
+ CTS_CODE_OUT => local_cts_code,
+ CTS_INFORMATION_OUT => local_cts_information,
+ CTS_READOUT_TYPE_OUT => local_cts_readout_type,
+ CTS_START_READOUT_OUT => local_cts_start_readout,
+ CTS_DATA_IN => (others => '0'),
+ CTS_DATAREADY_IN => '0',
+ CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
+ CTS_READ_OUT => open,
+ CTS_LENGTH_IN => (others => '0'),
+ CTS_ERROR_PATTERN_IN => local_cts_status_bits,
+ -- Data payload interface
+ FEE_DATA_OUT => local_fee_data,
+ FEE_DATAREADY_OUT => local_fee_dataready,
+ FEE_READ_IN => local_fee_read,
+ FEE_STATUS_BITS_OUT => local_fee_status_bits,
+ FEE_BUSY_OUT => local_fee_busy
+ );
+
+ -- handler for triggers
+ DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
+ port map(
+ CLK_IPU => CLK_SYS_IN,
+ CLK_GBE => CLK_125_IN,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => CTS_DATA_OUT,
+ CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+ CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+ CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => FEE_READ_OUT,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => open,
+ BANK_SELECT_OUT => open,
+ CONFIG_DONE_IN => '1',
+ DATA_GBE_ENABLE_IN => '1',
+ DATA_IPU_ENABLE_IN => '1',
+ MULT_EVT_ENABLE_IN => '1',
+ MAX_SUBEVENT_SIZE_IN => (others => '0'),
+ MAX_QUEUE_SIZE_IN => (others => '0'),
+ MAX_SUBS_IN_QUEUE_IN => (others => '0'),
+ MAX_SINGLE_SUB_SIZE_IN => (others => '0'),
+ READOUT_CTR_IN => (others => '0'),
+ READOUT_CTR_VALID_IN => '0',
+ CFG_AUTO_THROTTLE_IN => '0',
+ CFG_THROTTLE_PAUSE_IN => (others => '0'),
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => open,
+ PC_DATA_OUT => open,
+ PC_READY_IN => '1',
+ PC_SOS_OUT => open,
+ PC_EOS_OUT => open,
+ PC_EOQ_OUT => open,
+ PC_SUB_SIZE_OUT => open,
+ PC_TRIG_NR_OUT => open,
+ PC_TRIGGER_TYPE_OUT => open,
+ MONITOR_OUT => open,
+ DEBUG_OUT => open
+ );
+ end generate dummy_ipu_gen;
+
+ SETUP : gbe_setup
+ port map(
+ CLK => CLK_SYS_IN,
+ RESET => RESET,
+ -- interface to regio bus
+ BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
+ BUS_DATA_IN => BUS_REG_RX.data,
+ BUS_DATA_OUT => BUS_REG_TX.data,
+ BUS_WRITE_EN_IN => BUS_REG_RX.write,
+ BUS_READ_EN_IN => BUS_REG_RX.read,
+ BUS_ACK_OUT => BUS_REG_TX.ack,
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
+ GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
+ GBE_QUEUE_DEC_OUT => cfg_queue_dec,
+ GBE_MAX_FRAME_OUT => cfg_max_frame,
+ GBE_USE_GBE_OUT => cfg_gbe_enable,
+ GBE_USE_TRBNET_OUT => cfg_ipu_enable,
+ GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
+ GBE_READOUT_CTR_OUT => cfg_readout_ctr,
+ GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
+ GBE_ALLOW_RX_OUT => cfg_allow_rx,
+ GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
+ GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
+ GBE_SOFT_RESET_OUT => cfg_soft_rst,
+ GBE_MAX_REPLY_OUT => cfg_max_reply,
+ GBE_MAX_SUB_OUT => cfg_max_sub,
+ GBE_MAX_QUEUE_OUT => cfg_max_queue,
+ GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
+ GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
+ GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
+ GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
+ MONITOR_RX_BYTES_IN => sum_rx_bytes,
+ MONITOR_RX_FRAMES_IN => sum_rx_frames,
+ MONITOR_TX_BYTES_IN => sum_tx_bytes,
+ MONITOR_TX_FRAMES_IN => sum_tx_frames,
+ MONITOR_TX_PACKETS_IN => sum_tx_packets,
+ MONITOR_DROPPED_IN => sum_dropped,
+ MONITOR_SELECT_REC_IN => (others => '0'),
+ MONITOR_SELECT_REC_BYTES_IN => (others => '0'),
+ MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
+ MONITOR_SELECT_SENT_IN => (others => '0'),
+ MONITOR_SELECT_DROP_IN_IN => (others => '0'),
+ MONITOR_SELECT_DROP_OUT_IN => (others => '0'),
+ MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg,
+ MONITOR_IP_IN => my_ip,
+ DUMMY_EVENT_SIZE_OUT => dummy_event,
+ DUMMY_TRIGGERED_MODE_OUT => dummy_mode,
+ DATA_HIST_IN => (others => (others => '0')),
+ SCTRL_HIST_IN => (others => (others => '0'))
+ );
+
+ NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
+ GSC_INIT_DATAREADY_OUT <= '0';
+ GSC_INIT_DATA_OUT <= (others => '0');
+ GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+ GSC_REPLY_READ_OUT <= '1';
+ mlt_gsc_clk <= (others => '0');
+ mlt_gsc_init_read <= (others => '0');
+ mlt_gsc_reply_dataready <= (others => '0');
+ mlt_gsc_reply_data <= (others => '0');
+ mlt_gsc_reply_packet <= (others => '0');
+ mlt_gsc_busy <= (others => '0');
+ end generate NOSCTRL_MAP_GEN;
+
+ SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= '0') generate
+ ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '1') generate
+ mlt_gsc_clk <= GSC_CLK_IN;
+ GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready;
+ GSC_INIT_DATA_OUT <= mlt_gsc_init_data;
+ GSC_INIT_PACKET_NUM_OUT <= mlt_gsc_init_packet;
+ mlt_gsc_init_read <= GSC_INIT_READ_IN;
+ mlt_gsc_reply_dataready <= GSC_REPLY_DATAREADY_IN;
+ mlt_gsc_reply_data <= GSC_REPLY_DATA_IN;
+ mlt_gsc_reply_packet <= GSC_REPLY_PACKET_NUM_IN;
+ GSC_REPLY_READ_OUT <= mlt_gsc_reply_read;
+ mlt_gsc_busy <= GSC_BUSY_IN;
+ end generate ACTIVE_MAP_GEN;
+
+ INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
+ mlt_gsc_clk <= '0';
+ mlt_gsc_init_read <= '0';
+ mlt_gsc_reply_dataready <= '0';
+ mlt_gsc_reply_data <= (others => '0');
+ mlt_gsc_reply_packet <= (others => '0');
+ mlt_gsc_busy <= '0';
+ end generate INACTIVE_MAP_GEN;
+ end generate SCTRL_MAP_GEN;
+
+ sum_rx_bytes <= monitor_rx_bytes;
+ sum_rx_frames <= monitor_rx_frames;
+ sum_tx_bytes <= monitor_tx_bytes;
+ sum_tx_frames <= monitor_tx_frames;
+ sum_tx_packets <= monitor_tx_packets;
+ sum_dropped <= monitor_dropped;
+
+end architecture RTL;
GSR_N : in std_logic;
-- we connect to the MAC of gbe_med_raw directly
-- MAC status and config
- MAC_READY_CONF_IN : in std_logic;
- MAC_RECONF_OUT : out std_logic;
- MAC_AN_READY_IN : in std_logic;
+ MAC_READY_CONF_IN : in std_logic; -- gbe_main_control
+ MAC_RECONF_OUT : out std_logic; -- gbe_main_control
+ MAC_AN_READY_IN : in std_logic; -- gbe_main_control
-- MAC data interface
- MAC_FIFOAVAIL_OUT : out std_logic;
- MAC_FIFOEOF_OUT : out std_logic;
- MAC_FIFOEMPTY_OUT : out std_logic;
- MAC_RX_FIFOFULL_OUT : out std_logic;
+ MAC_FIFOAVAIL_OUT : out std_logic; -- gbe_frame_trans -- frame ready for transmission
+ MAC_FIFOEOF_OUT : out std_logic; -- gbe_frame_trans -- end of transmission frame
+ MAC_FIFOEMPTY_OUT : out std_logic; -- gbe_frame_trans -- frame transmission FIFO empty
+ MAC_RX_FIFOFULL_OUT : out std_logic; -- gbe_frame_receiver --- FIFO full for MAC error handling
-- MAC TX interface
- MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0);
- MAC_TX_READ_IN : in std_logic;
- MAC_TX_DISCRFRM_IN : in std_logic;
- MAC_TX_STAT_EN_IN : in std_logic;
- MAC_TX_STATS_IN : in std_logic_vector(30 downto 0);
- MAC_TX_DONE_IN : in std_logic;
+ MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); -- gbe_frame_constr -- TX frame data
+ MAC_TX_READ_IN : in std_logic; -- gbe_frame_constr -- TX frame data read
+ MAC_TX_DISCRFRM_IN : in std_logic; -- gbe_frame_constr -- end of transmission in case of error
+ -- gbe_frame_trans -- end of transmission in case of error
+ MAC_TX_STATS_IN : in std_logic_vector(30 downto 0); -- gbe_frame_trans -- (0) used for statistics
+ MAC_TX_STAT_EN_IN : in std_logic; -- gbe_frame_trans -- used for statistics
+ MAC_TX_DONE_IN : in std_logic; -- gbe_frame_constr -- end of transmission / statistics
+ -- gbe_frame_trans -- end of transmission / statistics
-- MAC RX interface
- MAC_RX_FIFO_ERR_IN : in std_logic;
- MAC_RX_STATS_IN : in std_logic_vector(31 downto 0);
- MAC_RX_DATA_IN : in std_logic_vector(7 downto 0);
- MAC_RX_WRITE_IN : in std_logic;
- MAC_RX_STAT_EN_IN : in std_logic;
- MAC_RX_EOF_IN : in std_logic;
- MAC_RX_ERROR_IN : in std_logic;
+ MAC_RX_FIFO_ERR_IN : in std_logic; -- gbe_frame_receiver -- UNUSED
+ MAC_RX_STATS_IN : in std_logic_vector(31 downto 0); -- gbe_frame_receiver -- UNUSED
+ MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); -- gbe_frame_receiver -- RX frame data
+ MAC_RX_WRITE_IN : in std_logic; -- gbe_frame_receiver -- data handling
+ MAC_RX_STAT_EN_IN : in std_logic; -- gbe_frame_receiver -- UNUSED
+ MAC_RX_EOF_IN : in std_logic; -- gbe_frame_receiver -- data parsing
+ MAC_RX_ERROR_IN : in std_logic; -- gbe_frame_receiver -- statistics
--
TRIGGER_IN : in std_logic; -- for debug purpose only
-- CTS interface
MAC_TX_DATA_OUT => MAC_TX_DATA_OUT,
MAC_TX_READ_IN => MAC_TX_READ_IN,
MAC_TX_DISCRFRM_IN => MAC_TX_DISCRFRM_IN,
- MAC_TX_STAT_EN_IN => MAC_TX_STAT_EN_IN,
+ MAC_TX_STAT_EN_IN => MAC_TX_STAT_EN_IN, -- BUG: signal not existing!
MAC_TX_STATS_IN => MAC_TX_STATS_IN,
MAC_TX_DONE_IN => MAC_TX_DONE_IN,
MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN,
jspc29 / trbnet.git / commitdiff