changing Diamond Project name to a single letter due to the usual software bugs

diff --git a/default/diamond/LogicBox.ldf b/default/diamond/LogicBox.ldf
index 20a846318ad48a16200836aeecaceb5a41df0672..8e00e2031f4310085226b041fce46aa014fe8498 100644 (file)
--- a/default/diamond/LogicBox.ldf
+++ b/default/diamond/LogicBox.ldf
@@ -1,11 +1,26 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="LogicBox" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="LogicBox">
+<BaliProject version="3.2" title="L" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="L">
     <Options/>
-    <Implementation title="LogicBox" dir="LogicBox" description="LogicBox" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="logicbox"/>
+    <Implementation title="L" dir="L" description="L" synthesis="synplify" default_strategy="Strategy1">
+        <Options  top="logicbox"/>
         <Source name="../logicbox.vhd" type="VHDL" type_short="VHDL">
             <Options top_module="logicbox"/>
         </Source>
+        <Source name="../../../padiwa/source/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../padiwa/amps/version.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../../pinout/logicbox.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>