-const char trbnet_version[] = "$Revision: 2.94 $";
+const char trbnet_version[] = "$Revision: 3.0 $";
#include <stdlib.h>
#include <signal.h>
#include <sys/sem.h>
#include <errno.h>
+#ifdef PEXOR
+#include <pexor_user.h>
+#include <sys/ioctl.h>
+
+#define PCIBAR 0
+static int pexorFileHandle = -1;
+#define PEXOR_DEVICE_NAME "/dev/pexor-0"
+#endif
+
#include <trberror.h>
#include "trbnet.h"
uint16_t F3;
} TRB_Package;
-/* Status-Bit definitions */
-
-typedef enum {
- Status_C_EndReached = 0, /* endpoint reached */
- Status_C_Coll = 1, /* collision detected, */
- Status_C_WordMiss = 2, /* word missing, */
- Status_C_Checksum = 3, /* checksum error, */
- Status_C_DontKnow = 4, /* dont understand, */
- Status_C_BufferMisMatch = 5, /* buffer mismatch */
- Status_C_AnswerMissing = 6 /* answer missing */
-} Status_Common;
-
-typedef enum {
- Status_Ch0_TrigCtr = 0, /* trigger counter mismatch */
- Status_Ch0_TrigMiss = 1, /* timing trigger missing */
- Status_Ch0_BufferHalfFull = 4, /* buffers half full */
- Status_Ch0_BuffersFull = 5, /* buffers almost full */
- Status_Ch0_NotConfig = 6 /* not configured */
-} Status_CH0;
-
-typedef enum {
- Status_Ch1_EvtNum = 0, /* event number mismatch */
- Status_Ch1_TrigCode = 1, /* trigger code / random mismatch */
- Status_Ch1_Length = 2, /* wrong length */
- Status_Ch1_NoAnswer = 3, /* answer missing */
- Status_Ch1_NotFound = 4, /* not found */
- Status_Ch1_DataMiss = 5, /* data missing */
- Status_Ch1_Sync = 6, /* sync error */
- Status_Ch1_EvtBroken = 7 /* event broken */
-} Status_CH1;
-
-typedef enum {
- Status_Ch2_None = -1
-} Status_CH2;
-
-typedef enum {
- Status_Ch3_Address = 0, /* unknown address */
- Status_Ch3_TimeOut = 1, /* timeout */
- Status_Ch3_NoData = 2 /* nomoredata */
-} Status_CH3;
-
/* ------ Internal Functions for FPGA access ------------------------------ */
+
+#ifndef PEXOR /* Etrax-Board */
+
#define FIFO_TOGGLE_BIT 0x10000
static uint32_t fifoToggleBit = 0;
fifoToggleBit = 0;
}
+#else /* PEXOR */
+
+static inline int write32_to_FPGA(uint16_t address, uint32_t value)
+{
+ struct pexor_reg_io descriptor;
+ int status = 0;
+
+ if (pexorFileHandle == -1) {
+ return -1;
+ }
+
+ descriptor.address = address * 4;
+ descriptor.bar = PCIBAR;
+ descriptor.value = value;
+
+ status = ioctl(pexorFileHandle, PEXOR_IOC_WRITE_REGISTER, &descriptor);
+ if(status) {
+ return -1;
+ }
+
+ return 0;
+}
+
+static inline int read32_from_FPGA(uint16_t address, uint32_t* value)
+{
+ struct pexor_reg_io descriptor;
+ int status = 0;
+
+ if (pexorFileHandle == -1) {
+ return -1;
+ }
+
+ descriptor.address = address * 4;
+ descriptor.bar = PCIBAR;
+ descriptor.value = 0;
+
+ status = ioctl(pexorFileHandle, PEXOR_IOC_READ_REGISTER, &descriptor);
+ if(status) {
+ return -1;
+ }
+
+ *value = descriptor.value;
+
+ return 0;
+}
+
+static inline int read32_from_FPGA_dma(uint16_t fifo_address,
+ uint32_t* values,
+ uint32_t size)
+{
+ /* Do Not Used */
+ return -1;
+}
+
+static inline void com_reset_FPGA()
+{
+}
+
+#endif /* End PEXOR */
+
/* ------ Internal Functions -------------------------------------------- */
static void TRB_Package_dump(const TRB_Package* pkg)
static void fifo_flush(uint8_t channel)
{
- uint32_t tmp;
+ uint32_t tmp = 0;
uint32_t fifoAddress;
unsigned int counter = 0;
} while ((tmp & MASK_FIFO_VALID) != 0);
}
+#if 0
static int trb_wait_tx_not_busy(uint8_t channel)
{
uint32_t tmp = 0;
return 0;
}
+#endif
static int trb_init_transfer(uint8_t channel)
{
uint32_t *tmp = dataBuffer;
int dma_size;
- TRB_Package package;
+ TRB_Package package = {0,0,0,0,0};
int headerType = 0;
uint32_t fifoBuffer = 0;
unsigned int counter = 0;
if (timeout >= MAX_TIMEOUT) {
fifo_flush(channel);
- trb_errno = TRB_FIFO_INCOMPLETE;
+ trb_errno = TRB_FIFO_TIMEOUT;
return -1;
}
}
trb_errno = TRB_SEMAPHORE;
return -1;
}
-
+
+#ifndef PEXOR
/* Get FifoToggleBit-Status, needed by read32_from_FPGA ... */
fifoToggleBit = readPC() & FIFO_TOGGLE_BIT;
-
+#endif
+
if (masterLock != 0) master_lock = 1;
return 0;
return 0;
}
-/* ----- Global Functions ----------------------------------------------- */
-
-/* Intit FPGA Interface */
-int init_ports()
+static int init_semaphore()
{
- static const uint32_t GPIO_OFFSET = 0x1a000 / sizeof(uint32_t);
- static const uint32_t GPIOB_OE_PINS = 0x0;
- static const uint32_t GPIOC_OE_PINS = 0x3ffff;
-
- volatile uint32_t* GPIOC_OE_OFFSET = NULL;
- volatile uint32_t* GPIOB_OE_OFFSET = NULL;
- uint32_t* GPIO_PTR = NULL;
-
- int memfd;
- uint32_t *mem = NULL;
+ trb_errno = TRB_NONE;
/* Set signal mask to block ALL signals */
sigfillset(&blockSet);
return -1;
}
}
+
+ return 0;
+}
+
+/* ----- Global Functions ----------------------------------------------- */
+
+#ifndef PEXOR /* Etrax-Board */
+/* Intit FPGA Interface */
+int init_ports()
+{
+ static const uint32_t GPIO_OFFSET = 0x1a000 / sizeof(uint32_t);
+ static const uint32_t GPIOB_OE_PINS = 0x0;
+ static const uint32_t GPIOC_OE_PINS = 0x3ffff;
+
+ volatile uint32_t* GPIOC_OE_OFFSET = NULL;
+ volatile uint32_t* GPIOB_OE_OFFSET = NULL;
+ uint32_t* GPIO_PTR = NULL;
+
+ int memfd;
+ uint32_t *mem = NULL;
+
+ /* Init semaphore and signal handling */
+ if (init_semaphore() == -1) return -1;
+
/* Open shared memory and initialize FIFO pointers */
memfd = open("/dev/mem", O_RDWR);
if (memfd < 0) {
GPIOC_OUT_OFFSET = NULL;
}
+
+#else /* PEXOR */
+
+int init_ports()
+{
+ /* Init semaphore and signal handling */
+ if (init_semaphore() == -1) return -1;
+
+ pexorFileHandle = open(PEXOR_DEVICE_NAME, O_RDWR);
+ if (pexorFileHandle < 0) {
+ fprintf(stderr, "open failed\n");
+ trb_errno = TRB_PEXOR_OPEN;
+ return -1;
+ }
+
+ return 0;
+}
+
+void close_ports()
+{
+ if (pexorFileHandle >= 0) {
+ close(pexorFileHandle);
+ }
+}
+
+#endif /* End Pexor */
+
int trb_fifo_flush(uint8_t channel)
{
trb_errno = TRB_NONE;
jspc29 / trbnettools.git / commitdiff