---Media interface for Lattice ECP3 using PCS at 2.5GHz\r
-\r
-LIBRARY IEEE;\r
-USE IEEE.std_logic_1164.ALL;\r
-USE IEEE.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.med_sync_define.all;\r
-use work.cbmnet_interface_pkg.all;\r
-use work.cbmnet_phy_pkg.all;\r
-\r
-entity cbmnet_phy_ecp3 is\r
- generic(\r
- IS_SYNC_SLAVE : integer := c_YES; --select slave mode\r
- DETERMINISTIC_LATENCY : integer := c_YES; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)\r
- IS_SIMULATED : integer := c_NO;\r
- INCL_DEBUG_AIDS : integer := c_YES\r
- );\r
- port(\r
- CLK : in std_logic; -- *internal* 125 MHz reference clock\r
- RESET : in std_logic; -- synchronous reset\r
- CLEAR : in std_logic; -- asynchronous reset\r
-\r
- --Internal Connection TX\r
- PHY_TXDATA_IN : in std_logic_vector(15 downto 0);\r
- PHY_TXDATA_K_IN : in std_logic_vector( 1 downto 0);\r
-\r
- --Internal Connection RX\r
- PHY_RXDATA_OUT : out std_logic_vector(15 downto 0) := (others => '0');\r
- PHY_RXDATA_K_OUT : out std_logic_vector( 1 downto 0) := (others => '0');\r
-\r
- CLK_RX_HALF_OUT : out std_logic := '0'; -- recovered 125 MHz\r
- CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz\r
- CLK_RX_RESET_OUT : out std_logic := '1';\r
-\r
- LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data\r
- SERDES_ready : out std_logic;\r
-\r
- --SFP Connection\r
- SD_RXD_P_IN : in std_logic := '0';\r
- SD_RXD_N_IN : in std_logic := '0';\r
- SD_TXD_P_OUT : out std_logic := '0';\r
- SD_TXD_N_OUT : out std_logic := '0';\r
-\r
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place,entity '1' = no SFP mounted)\r
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable\r
-\r
- LED_RX_OUT : out std_logic;\r
- LED_TX_OUT : out std_logic;\r
- LED_OK_OUT : out std_logic;\r
- \r
- -- Status and control port\r
- STAT_OP : out std_logic_vector ( 15 downto 0) := (others => '0');\r
- CTRL_OP : in std_logic_vector ( 15 downto 0) := (others => '0');\r
- DEBUG_OUT : out std_logic_vector (511 downto 0) := (others => '0')\r
- );\r
-end entity;\r
-\r
-architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is\r
- -- Placer Directives\r
- attribute HGROUP : string;\r
- -- for whole architecture\r
- attribute HGROUP of cbmnet_phy_ecp3_arch : architecture is "cbmnet_phy_group";\r
- \r
- attribute syn_hier: string;\r
- attribute syn_hier of cbmnet_phy_ecp3_arch : architecture is "hard"; \r
- \r
- \r
- attribute syn_sharing : string;\r
- attribute syn_sharing of cbmnet_phy_ecp3_arch : architecture is "off";\r
-\r
- constant WA_FIXATION : integer := c_YES;\r
- signal DETERMINISTIC_LATENCY_C : std_logic;\r
-\r
--- Clocks and global resets \r
- signal clk_125_local : std_logic; -- local 125 MHz reference clock driven by clock generators\r
- signal rclk_250_i : std_logic; -- recovered word clock\r
- signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word\r
- signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL\r
-\r
- signal clk_tx_half_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL\r
- \r
- signal rst_i : std_logic; -- High-active reset driven by external logic\r
- signal rst_n_i : std_logic; -- Low-active version of rst_i\r
- \r
--- SERDES/PCS \r
- -- status\r
- signal rx_los_low_i : std_logic;\r
- signal rx_cdr_lol_i : std_logic;\r
- signal tx_pll_lol_i : std_logic;\r
- signal lsm_status_i : std_logic;\r
-\r
- signal rx_dec_error_i: std_logic;\r
- signal rx_dec_errors2_i : std_logic_vector(1 downto 0);\r
- signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(1 downto 0);\r
-\r
- signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition"\r
- \r
- -- resets\r
- signal rst_qd_i : std_logic;\r
- signal serdes_rst_qd_i : std_logic;\r
- \r
- signal tx_serdes_rst_i : std_logic;\r
- signal tx_pcs_rst_i : std_logic;\r
- \r
- signal rx_serdes_rst_i : std_logic;\r
- signal rx_pcs_rst_i : std_logic;\r
-\r
- -- data\r
- signal tx_data_to_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES\r
- signal rx_data_from_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES\r
-\r
- -- status & control interface (and obtained info)\r
- signal sci_ch_i : std_logic_vector(3 downto 0);\r
- signal sci_qd_i : std_logic;\r
- signal sci_reg_i : std_logic;\r
- signal sci_addr_i : std_logic_vector(8 downto 0);\r
- signal sci_data_in_i : std_logic_vector(7 downto 0) := (others => '0');\r
- signal sci_data_out_i : std_logic_vector(7 downto 0);\r
- signal sci_read_i : std_logic;\r
- signal sci_write_i : std_logic;\r
- signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
- signal sci_read_shift_i : std_logic_vector(2 downto 0);\r
-\r
- signal wa_position_i : std_logic_vector(15 downto 0) := x"FFFF";\r
- signal barrel_shifter_misaligned_i: std_logic;\r
- \r
--- RESET FSM \r
- signal rx_rst_fsm_state_i : std_logic_vector(3 downto 0);\r
- signal tx_rst_fsm_state_i : std_logic_vector(3 downto 0);\r
- signal tx_rst_fsm_ready_i : std_logic;\r
- signal tx_rst_fsm_ready_buf_i : std_logic;\r
- \r
- signal byte_alignment_to_fsm_i : std_logic;\r
- signal word_alignment_to_fsm_i : std_logic;\r
-\r
- signal rx_rst_fsm_ready_i : std_logic;\r
- \r
- signal serdes_ready_i : std_logic;\r
- \r
--- SCI Logic to obtain the barrel shifter position\r
- type sci_ctrl is (IDLE, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
- signal sci_state : sci_ctrl;\r
- signal sci_timer : unsigned( 7 downto 0) := (others => '0');\r
- signal start_timer : unsigned(18 downto 0) := (others => '0');\r
- \r
--- GEAR\r
- signal gear_to_fsm_rst_i : std_logic;\r
- signal gear_to_rm_rst_i : std_logic; -- gear keeps CBMNet ready manager reset until gear locked successfully\r
- signal gear_to_rm_n_rst_i : std_logic; -- inverted version of above\r
-\r
- signal rx_data_from_gear_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated by gear\r
- \r
- signal rx_data_i : std_logic_vector(17 downto 0); -- in the front end this signal is identical to rx_data_from_gear_i\r
- -- otherwise a clock domain crossing from rclk_125_i to clk_125_local is\r
- -- necessary. this signal will not exhibit a deterministic latency !!!!!!\r
- -- (however, this is no problem, as the clock master will not receive DLMs)\r
-\r
- signal rx_data_debug_i : std_logic_vector(17 downto 0); \r
- \r
- signal tx_data_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated fed to gear\r
- signal tx_gear_reset_i : std_logic;\r
- signal tx_gear_allow_relock_i : std_logic;\r
- \r
- signal tx_gear_ready_i : std_logic;\r
- \r
- signal rx_gear_debug_i : std_logic_vector(31 downto 0);\r
- signal tx_gear_debug_i : std_logic_vector(31 downto 0);\r
- \r
--- CBMNet Ready Managers\r
- signal rm_rx_ready_i : std_logic;\r
- signal rm_rx_almost_ready_i : std_logic;\r
- signal rm_rx_status_for_tx_i : std_logic;\r
- signal rm_rx_see_ready0_i : std_logic;\r
- signal rm_rx_saw_ready1_i : std_logic;\r
- signal rm_rx_valid_char_i : std_logic;\r
- \r
- signal rm_tx_ready_i : std_logic;\r
- signal rm_tx_almost_ready_i : std_logic;\r
- \r
- signal rm_rx_to_gear_reset_i : std_logic;\r
- \r
- signal rm_rx_data_buf_i : std_logic_vector(17 downto 0);\r
- \r
- signal rm_rx_ebtb_code_err_cntr_clr_i : std_logic;\r
- signal rm_rx_ebtb_disp_err_cntr_clr_i : std_logic;\r
- signal rm_rx_ebtb_code_err_cntr_i : std_logic_vector(15 downto 0);\r
- signal rm_rx_ebtb_disp_err_cntr_i : std_logic_vector(15 downto 0);\r
- signal rm_rx_ebtb_code_err_cntr_flag_i : std_logic;\r
- signal rm_rx_ebtb_disp_err_cntr_flag_i : std_logic;\r
- \r
- signal rm_tx_to_rx_reinit_i : std_logic;\r
- \r
- signal rm_rx_see_reinit : std_logic;\r
- signal rm_rx_ebtb_detect_i : std_logic;\r
- signal rm_tx_link_lost_i : std_logic;\r
- \r
- signal rm_tx_pcs_startup_cntr_clr : std_logic;\r
- signal rm_tx_pcs_startup_cntr : std_logic_vector(15 downto 0); -- Counts for link startups\r
- signal rm_tx_pcs_startup_cntr_flag : std_logic; \r
- \r
- signal rm_rx_rxpcs_ready_i : std_logic;\r
-\r
--- LEDs\r
- signal led_ok_i : std_logic;\r
- signal led_tx_i, last_led_tx_i : std_logic;\r
- signal led_rx_i, last_led_rx_i : std_logic;\r
- signal led_timer_i : unsigned(20 downto 0);\r
-\r
--- Stats\r
- signal stat_reconnect_counter_i : unsigned(15 downto 0); -- counts the number of RX-serdes resets since last external reset\r
- signal stat_last_reconnect_duration_i : unsigned(31 downto 0);\r
- signal stat_decode_error_counter_i : unsigned(31 downto 0);\r
- \r
- \r
- signal stat_wa_int_i : std_logic_vector(15 downto 0) := (others => '0');\r
- \r
- signal tx_data_debug_i : std_logic_vector(17 downto 0);\r
- signal tx_data_debug_state_i : std_logic;\r
- \r
- signal low_level_rx_see_dlm0 : std_logic;\r
- signal low_level_tx_see_dlm0 : std_logic;\r
- signal low_level_tx_see_dlm0_125 : std_logic;\r
- \r
- signal stat_dlm_counter_i : unsigned(15 downto 0);\r
- signal stat_init_ack_counter_i : unsigned(15 downto 0);\r
- \r
- signal test_line_i : std_logic_vector(15 downto 0) := x"0001";\r
- \r
- signal rx_stab_i, tx_stab_i : unsigned(15 downto 0);\r
- \r
- signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0);\r
- \r
- --signal see_dlm_lb_i, see_dlm_lb_buf_i : std_logic_vector(15 downto 0) := (others => '0');\r
- --signal see_dlm_lb_aggr_i, see_dlm_hb_i, see_dlm_hb_buf_i : std_logic;\r
- --signal stat_sync_dlm_counter_i, stat_sync_dlm_inv_counter_i : unsigned(7 downto 0);\r
- \r
-begin\r
- assert IS_SYNC_SLAVE = c_YES \r
- report "Support of clock master PHY is not tested anymore and probably broken"\r
- severity failure;\r
- \r
- DETERMINISTIC_LATENCY_C <= '1' when DETERMINISTIC_LATENCY = c_YES else '0';\r
-\r
- clk_125_local <= CLK;\r
- CLK_RX_HALF_OUT <= rclk_125_i;\r
- CLK_RX_FULL_OUT <= rclk_250_i;\r
-\r
- SD_TXDIS_OUT <= '0';\r
-\r
- rst_i <= (CLEAR or CTRL_OP(0));\r
- rst_n_i <= not rst_i;\r
-\r
- ------------------------------------------------- \r
- -- Serdes\r
- ------------------------------------------------- \r
- THE_SERDES : cbmnet_sfp1\r
- port map(\r
- -- SERIAL DATA PORTS\r
- hdinp_ch0 => SD_RXD_P_IN,\r
- hdinn_ch0 => SD_RXD_N_IN,\r
- hdoutp_ch0 => SD_TXD_P_OUT,\r
- hdoutn_ch0 => SD_TXD_N_OUT,\r
- \r
- -- CLOCKS\r
- rx_full_clk_ch0 => rclk_250_i,\r
- rx_half_clk_ch0 => open, -- recovered (and correctly aligned) 125 MHz clock is generated by gear\r
- \r
- tx_full_clk_ch0 => clk_tx_full_i,\r
- tx_half_clk_ch0 => open,\r
- \r
- fpga_rxrefclk_ch0 => clk_125_local,\r
- fpga_txrefclk => rclk_125_i,\r
- txiclk_ch0 => rclk_250_i,\r
-\r
- -- RESETS\r
- rst_qd_c => rst_qd_i,\r
- serdes_rst_qd_c => serdes_rst_qd_i, -- always 0\r
- tx_serdes_rst_c => tx_serdes_rst_i, -- always 0\r
- rx_serdes_rst_ch0_c => rx_serdes_rst_i,\r
- tx_pcs_rst_ch0_c => tx_pcs_rst_i,\r
- rx_pcs_rst_ch0_c => rx_pcs_rst_i,\r
-\r
- tx_pwrup_ch0_c => '1',\r
- rx_pwrup_ch0_c => '1',\r
- \r
- -- TX DATA PORT \r
- txdata_ch0 => tx_data_to_serdes_i(7 downto 0),\r
- tx_k_ch0 => tx_data_to_serdes_i(8),\r
-\r
- tx_force_disp_ch0 => '0',\r
- tx_disp_sel_ch0 => '0',\r
- tx_div2_mode_ch0_c => '0',\r
- \r
- -- RX DATA PORT\r
- rxdata_ch0 => rx_data_from_serdes_i(7 downto 0),\r
- rx_k_ch0 => rx_data_from_serdes_i(8),\r
-\r
- rx_disp_err_ch0 => open,\r
- rx_cv_err_ch0 => rx_dec_error_i,\r
- rx_div2_mode_ch0_c => '0',\r
- \r
- -- LOOPBACK\r
- sb_felb_ch0_c => '0',\r
- sb_felb_rst_ch0_c => '0',\r
-\r
- -- STATUS\r
- tx_pll_lol_qd_s => tx_pll_lol_i,\r
- rx_los_low_ch0_s => rx_los_low_i,\r
- rx_cdr_lol_ch0_s => rx_cdr_lol_i,\r
- lsm_status_ch0_s => lsm_status_i,\r
- \r
- SCI_WRDATA => sci_data_in_i,\r
- SCI_RDDATA => sci_data_out_i,\r
- SCI_ADDR => sci_addr_i(5 downto 0),\r
- SCI_SEL_QUAD => sci_qd_i,\r
- SCI_SEL_CH0 => sci_ch_i(0),\r
- SCI_RD => sci_read_i,\r
- SCI_WRN => sci_write_i\r
- );\r
- \r
- THE_RX_GEAR: CBMNET_PHY_RX_GEAR \r
- generic map (\r
- IS_SYNC_SLAVE => IS_SYNC_SLAVE\r
- ) port map (\r
- -- SERDES PORT\r
- CLK_250_IN => rclk_250_i, -- in std_logic;\r
- PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic;\r
- SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic;\r
- DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0);\r
-\r
- -- RM PORT\r
- RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic;\r
- CLK_125_OUT => rclk_125_i, -- out std_logic;\r
- RESET_OUT => gear_to_rm_rst_i, -- out std_logic;\r
- DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0)\r
- \r
- DEBUG_OUT => rx_gear_debug_i\r
- );\r
- \r
- rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local);\r
- \r
- THE_TX_GEAR: CBMNET_PHY_TX_GEAR\r
- generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)\r
- port map (\r
- CLK_250_IN => clk_tx_full_i, -- in std_logic;\r
- CLK_125_IN => rclk_125_i, -- in std_logic;\r
- CLK_125_OUT => clk_tx_half_i,\r
- \r
- RESET_IN => tx_gear_reset_i, -- in std_logic;\r
- ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic\r
- \r
- TX_READY_OUT => tx_gear_ready_i,\r
- \r
- DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0)\r
- DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0);\r
- );\r
- tx_gear_reset_i <= not tx_rst_fsm_ready_i;\r
- tx_gear_allow_relock_i <= '0';\r
-\r
- \r
- \r
- tx_serdes_rst_i <= '0'; --no function\r
- serdes_rst_qd_i <= '0'; --included in rst_qd_i\r
- \r
- ------------------------------------------------- \r
- -- Reset FSM & Link states\r
- ------------------------------------------------- \r
- THE_RX_FSM : cbmnet_phy_ecp3_rx_reset_fsm\r
- generic map (\r
- IS_SIMULATED => IS_SIMULATED\r
- )\r
- port map(\r
- RST_N => rst_n_i,\r
- RX_REFCLK => clk_125_local,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_i,\r
- RX_CDR_LOL_CH_S => rx_cdr_lol_i,\r
- RX_LOS_LOW_CH_S => rx_los_low_i,\r
- \r
- RM_RESET_IN => CTRL_OP(4), --rx_reset_from_rm_i,\r
- PROPER_BYTE_ALIGN_IN=> byte_alignment_to_fsm_i,\r
- PROPER_WORD_ALIGN_IN=> word_alignment_to_fsm_i,\r
- \r
- RX_SERDES_RST_CH_C => rx_serdes_rst_i,\r
- RX_PCS_RST_CH_C => rx_pcs_rst_i,\r
- STATE_OUT => rx_rst_fsm_state_i\r
- );\r
- byte_alignment_to_fsm_i <= not (DETERMINISTIC_LATENCY_C and barrel_shifter_misaligned_i) or CTRL_OP(3);\r
- word_alignment_to_fsm_i <= not (gear_to_fsm_rst_i or AND_ALL(rx_error_delay)) or CTRL_OP(5);\r
- \r
- \r
- -- decode error\r
- rx_dec_error_125_i <= rx_dec_error_125_i(0) & rx_dec_error_i when rising_edge(rclk_250_i);\r
- rx_dec_error_125_buf_i <= rx_dec_error_125_i when rising_edge(clk_125_local);\r
- \r
- rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);\r
- process is \r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- if RESET='1' then\r
- stat_decode_error_counter_i <= (others => '0');\r
- elsif rx_dec_error_125_buf_i = "11" then\r
- stat_decode_error_counter_i <= stat_decode_error_counter_i + 2;\r
- elsif rx_dec_error_125_buf_i = "10" or rx_dec_error_125_buf_i = "01" then\r
- stat_decode_error_counter_i <= stat_decode_error_counter_i + 1;\r
- end if;\r
- end process;\r
- \r
- \r
- THE_TX_FSM : cbmnet_phy_ecp3_tx_reset_fsm\r
- generic map (\r
- IS_SIMULATED => IS_SIMULATED\r
- )\r
- port map(\r
- RST_N => rst_n_i,\r
- TX_REFCLK => clk_125_local,\r
- TX_PLL_LOL_QD_S => tx_pll_lol_i,\r
- RST_QD_C => rst_qd_i,\r
- TX_PCS_RST_CH_C => tx_pcs_rst_i,\r
- STATE_OUT => tx_rst_fsm_state_i\r
- );\r
- \r
- proc_rst_fsms_ready: process is begin\r
- wait until rising_edge(clk_125_local);\r
- rx_rst_fsm_ready_i <= '0';\r
- if rx_rst_fsm_state_i = x"6" then\r
- rx_rst_fsm_ready_i <= '1';\r
- end if;\r
-\r
- tx_rst_fsm_ready_i <= '0';\r
- if tx_rst_fsm_state_i = x"5" then\r
- tx_rst_fsm_ready_i <= '1';\r
- end if;\r
- end process;\r
- \r
- ------------------------------------------------- \r
- -- CBMNet Ready Modules\r
- ------------------------------------------------- \r
- THE_RX_READY: cn_rx_pcs_wrapper\r
- generic map (\r
- SIMULATION => 0,\r
- USE_BS => 0,\r
- SYNC_SIGNALS => 1,\r
- INCL_8B10B_DEC => 0\r
- )\r
- port map ( \r
- rx_clk => rclk_125_i, -- in std_logic;\r
- res_n_rx => gear_to_rm_n_rst_i, -- in std_logic;\r
- rxpcs_reinit => rm_tx_to_rx_reinit_i, -- in std_logic; -- Reinit RXPCS \r
- rxdata_in(17 downto 0) => rx_data_i,\r
- rxdata_in(19 downto 18) => "00",\r
- reset_rx_cdr => rm_rx_to_gear_reset_i, -- out std_logic; -- Reset RX CDR to align\r
- rxpcs_almost_ready => rm_rx_almost_ready_i, -- out std_logic; -- Ready1 detected, only waiting for break\r
- rxpcs_ready => rm_rx_rxpcs_ready_i, -- out std_logic; -- RXPCS initialization done\r
- see_reinit => rm_rx_see_reinit, -- out std_logic; -- Initialization pattern detected although ready\r
- bs_position => open, -- out std_logic_vector(4 downto 0); -- Number of bit-shifts necessary for word-alignment\r
- rxdata_out => rm_rx_data_buf_i, -- out std_logic_vector(17 downto 0);\r
- ebtb_detect => rm_rx_ebtb_detect_i, -- out std_logic; -- Depends on the FSM state, alignment done\r
- \r
- --diagnostics\r
- ebtb_code_err_cntr_clr => '0', -- in std_logic;\r
- ebtb_disp_err_cntr_clr => '0', -- in std_logic;\r
- ebtb_code_err_cntr => open, -- out std_logic_vector(15 downto 0); -- Counts for code errors if ebtb_detect is true\r
- ebtb_disp_err_cntr => open, -- out std_logic_vector(15 downto 0); -- Counts for disparity errors if ebtb_detect is true\r
- ebtb_code_err_cntr_flag => open,-- out std_logic;\r
- ebtb_disp_err_cntr_flag => open -- out std_logic\r
- );\r
-\r
- PHY_RXDATA_OUT <= rx_data_i(15 downto 0);\r
- PHY_RXDATA_K_OUT <= rx_data_i(17 downto 16);\r
- gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(rclk_125_i);\r
- \r
- \r
- THE_TX_READY: cn_tx_pcs_wrapper \r
- generic map (\r
- REVERSE_OUTPUT => 0, --integer range 0 to 1 := 1;\r
- LINK_MASTER => 0, --integer range 0 to 1 := 1;\r
- SYNC_SIGNALS => 1, --integer range 0 to 1 := 1;\r
-\r
- INCL_8B10B_ENC => 0 --integer range 0 to 1 := 1\r
- ) port map (\r
- tx_clk => rclk_125_i, --in std_logic;\r
- res_n_tx => tx_rst_fsm_ready_buf_i, --in std_logic;\r
- pcs_restart => CTRL_OP(14), --in std_logic; -- restart pcs layer\r
- pma_ready => tx_gear_ready_i, --in std_logic;\r
- ebtb_detect => rm_rx_ebtb_detect_i, --in std_logic; -- alignment done and valid 8b10b stream detected\r
- see_reinit => rm_rx_see_reinit, --in std_logic;\r
- rxpcs_almost_ready => rm_rx_almost_ready_i, --in std_logic;\r
- txdata_in(15 downto 0) => PHY_TXDATA_IN, --in std_logic_vector(17 downto 0);\r
- txdata_in(17 downto 16)=> PHY_TXDATA_K_IN,\r
- \r
- txpcs_ready => rm_tx_ready_i, --out std_logic;\r
- link_lost => rm_tx_link_lost_i, --out std_logic;\r
- reset_out => open, --out std_logic;\r
- rxpcs_reinit => rm_tx_to_rx_reinit_i, --out std_logic; -- Reinit the RXPCS FSM\r
- txdata_out => tx_data_i, --out std_logic_vector(17 downto 0); -- tx data to transceiver\r
- txdata_out_coded => open, --out std_logic_vector(19 downto 0); -- tx data to transceiver already 8b10b coded\r
- \r
- --diagnostics\r
- pcs_startup_cntr_clr => rm_tx_pcs_startup_cntr_clr, --in std_logic;\r
- pcs_startup_cntr => rm_tx_pcs_startup_cntr, --out std_logic_vector(15 downto 0); -- Counts for link startups\r
- pcs_startup_cntr_flag => rm_tx_pcs_startup_cntr_flag --out std_logic;\r
- );\r
-\r
- \r
- rm_rx_status_for_tx_i <= rm_rx_almost_ready_i or rm_rx_ready_i;\r
- \r
- -- clock domain crossing from clk_125_local to rclk_125_i\r
- PROC_SYNC_FSM_READY: process is begin\r
- wait until rising_edge(rclk_125_i);\r
- \r
- if IS_SYNC_SLAVE = c_YES then\r
- tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i and not gear_to_rm_rst_i;\r
- \r
- else\r
- tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i;\r
- \r
- end if;\r
- end process;\r
- \r
- serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(rclk_125_i);\r
- led_ok_i <= serdes_ready_i;\r
- SERDES_ready <= serdes_ready_i;\r
- \r
- ------------------------------------------------- \r
- -- SCI\r
- ------------------------------------------------- \r
- -- gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
- -- upon retrival the barrel shifter is checked and - if necessary - a serdes reset is issued\r
- PROC_SCI_CTRL: process \r
- variable cnt : integer range 0 to 4 := 0;\r
- begin\r
- wait until rising_edge(clk_125_local);\r
- \r
- case sci_state is\r
- when IDLE =>\r
- sci_ch_i <= x"0";\r
- sci_qd_i <= '0';\r
- sci_reg_i <= '0';\r
- sci_read_i <= '0';\r
- sci_write_i <= '0';\r
- sci_timer <= sci_timer + 1;\r
- if sci_timer(sci_timer'left) = '1' then\r
- sci_timer <= (others => '0');\r
- sci_state <= GET_WA;\r
- end if; \r
-\r
- when GET_WA =>\r
- if cnt = 4 then\r
- cnt := 0;\r
- sci_state <= IDLE;\r
- \r
- else\r
- sci_state <= GET_WA_WAIT;\r
- sci_addr_i <= '0' & x"22";\r
- sci_ch_i <= x"0";\r
- sci_ch_i(cnt) <= '1';\r
- sci_read_i <= '1';\r
- end if;\r
- \r
- when GET_WA_WAIT =>\r
- sci_state <= GET_WA_WAIT2;\r
- \r
- when GET_WA_WAIT2 =>\r
- sci_state <= GET_WA_FINISH;\r
- \r
- when GET_WA_FINISH =>\r
- wa_position_i(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
- sci_state <= GET_WA; \r
- cnt := cnt + 1;\r
- \r
- end case;\r
- end process;\r
- \r
- process is begin\r
- wait until rising_edge(clk_125_local);\r
- barrel_shifter_misaligned_i <= '0';\r
- if lsm_status_i = '1' and wa_position_i(3 downto 0) /= x"0" then\r
- barrel_shifter_misaligned_i <= '1';\r
- end if;\r
- end process;\r
- \r
- -- Produce 1us reset pulse for external logic\r
- PROC_CLK_RESET: process is\r
- variable counter : unsigned(8 downto 0) := (others => '0');\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- CLK_RX_RESET_OUT <= '1';\r
- \r
- if serdes_ready_i = '0' then\r
- counter := (others => '0');\r
- \r
- elsif counter(counter'high) = '0' then\r
- counter := counter + 1;\r
- \r
- else\r
- CLK_RX_RESET_OUT <= '0';\r
- \r
- end if;\r
- end process;\r
-\r
- \r
- GEN_DEBUG: if INCL_DEBUG_AIDS = c_YES generate\r
- proc_stat: process is\r
- variable last_rx_serdes_rst_i : std_logic;\r
- begin\r
- wait until rising_edge(clk_125_local);\r
- \r
- if rst_n_i = '0' then\r
- stat_reconnect_counter_i <= (others => '0');\r
- stat_last_reconnect_duration_i <= (others => '0');\r
- stat_wa_int_i <= (others => '0');\r
- else\r
- if rx_serdes_rst_i = '1' and last_rx_serdes_rst_i = '0' then\r
- stat_reconnect_counter_i <= stat_reconnect_counter_i + TO_UNSIGNED(1,1);\r
- end if;\r
- \r
- if serdes_ready_i = '0' then\r
- stat_last_reconnect_duration_i <= stat_last_reconnect_duration_i + TO_UNSIGNED(1,1);\r
- end if;\r
- \r
- stat_wa_int_i <= stat_wa_int_i or wa_position_i;\r
- end if;\r
- \r
- last_rx_serdes_rst_i := rx_serdes_rst_i;\r
- end process;\r
- \r
- PROC_SENSE_TX_DLM125: process is\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- \r
- low_level_tx_see_dlm0_125 <= '0';\r
- if tx_data_i = "10" & x"fb6a" then\r
- low_level_tx_see_dlm0_125 <= '1';\r
- end if;\r
- end process;\r
- \r
- process is\r
- variable rx_v, tx_v : std_logic_vector(17 downto 0);\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
-\r
- if reset = '1' or rx_v /= rx_data_i then rx_stab_i <= (others => '0');\r
- else rx_stab_i <= rx_stab_i + 1; end if;\r
-\r
- if reset = '1' or tx_v /= tx_data_i then tx_stab_i <= (others => '0');\r
- else tx_stab_i <= tx_stab_i + 1; end if;\r
-\r
- rx_v := rx_data_i;\r
- tx_v := tx_data_i;\r
- end process;\r
- \r
- \r
- PROC_SENSE_DLMS: process begin\r
- wait until rising_edge(rclk_125_i);\r
- \r
- if serdes_ready_i = '0' then\r
- stat_dlm_counter_i <= (others => '0');\r
- elsif rx_data_i(17) = '1' and rx_data_i(15 downto 8) = K277 then\r
- stat_dlm_counter_i <= stat_dlm_counter_i + TO_UNSIGNED(1,1);\r
- end if;\r
- end process;\r
-\r
--- DEBUG_OUT_BEGIN \r
- DEBUG_OUT(19 downto 0) <= "00" & tx_data_i(17 downto 0);\r
- DEBUG_OUT(23 downto 20) <= "0" & tx_pll_lol_i & rx_los_low_i & rx_cdr_lol_i;\r
-\r
- DEBUG_OUT(27 downto 24) <= gear_to_fsm_rst_i & barrel_shifter_misaligned_i & SD_PRSNT_N_IN & SD_LOS_IN;\r
- DEBUG_OUT(31 downto 28) <= rst_qd_i & rx_serdes_rst_i & tx_pcs_rst_i & rx_pcs_rst_i;\r
- \r
- DEBUG_OUT( 51 downto 32) <= "00" & rx_data_i(17 downto 0);\r
- DEBUG_OUT( 59 downto 52) <= rx_rst_fsm_state_i(3 downto 0) & tx_rst_fsm_state_i(3 downto 0);\r
- \r
- DEBUG_OUT( 63 downto 60) <= serdes_ready_i & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i;\r
- \r
- DEBUG_OUT( 79 downto 64) <= rx_gear_debug_i(15 downto 0);\r
- DEBUG_OUT( 95 downto 80) <= tx_gear_debug_i(15 downto 0);\r
- \r
- DEBUG_OUT( 99 downto 96) <= rm_rx_almost_ready_i & rm_rx_rxpcs_ready_i & rm_rx_see_reinit & rm_rx_ebtb_detect_i;\r
- DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0);\r
- DEBUG_OUT(107 downto 104) <= word_alignment_to_fsm_i & byte_alignment_to_fsm_i & rm_rx_to_gear_reset_i & gear_to_rm_rst_i;\r
-\r
- DEBUG_OUT(123 downto 108) <= tx_stab_i(15 downto 0);\r
-\r
- DEBUG_OUT(139 downto 124) <= rx_stab_i(15 downto 0);\r
- DEBUG_OUT(147 downto 140) <= stat_init_ack_counter_i(7 downto 0);\r
- DEBUG_OUT(179 downto 148) <= stat_last_reconnect_duration_i(31 downto 0);\r
-\r
- DEBUG_OUT(195 downto 180) <= stat_reconnect_counter_i(15 downto 0);\r
- DEBUG_OUT(211 downto 196) <= stat_dlm_counter_i(15 downto 0);\r
- DEBUG_OUT(243 downto 212) <= rm_rx_ebtb_code_err_cntr_i(15 downto 0) & rm_rx_ebtb_disp_err_cntr_i(15 downto 0);\r
-\r
- DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0);\r
- \r
- DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);\r
- --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i);\r
- --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i); \r
- \r
-\r
- \r
- --DEBUG_OUT(255 downto 170) <= (others => '0');\r
- \r
--- DEBUG_OUT_END\r
- \r
- process is\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- if rx_data_i /= "10" & x"fcc3" then\r
- rx_data_sp_i0 <= rx_data_i;\r
- rx_data_sp_i1 <= rx_data_sp_i0;\r
- rx_data_sp_i2 <= rx_data_sp_i1;\r
- rx_data_sp_i3 <= rx_data_sp_i2;\r
- end if;\r
- end process;\r
- \r
- --PROC_SEE_FAST_DLM: process is\r
- --variable saw_lb_v, saw_hb_v : std_logic;\r
- --begin\r
- --wait until rising_edge(rclk_250_i);\r
- \r
- --see_dlm_hb_i <= '0' ;\r
- --if rx_data_from_serdes_i = '1' & K277 then\r
- --see_dlm_hb_i <= '1';\r
- --end if;\r
- --see_dlm_hb_buf_i <= see_dlm_hb_i;\r
- \r
- --see_dlm_lb_aggr_i <= '0';\r
- --if rx_data_from_serdes_i = '1' & K277 then\r
- --see_dlm_lb_aggr_i <= OR_ALL(see_dlm_lb_buf_i);\r
- --end if;\r
- \r
-\r
- \r
- --if rst_i = '1' then\r
- --stat_sync_dlm_counter_i <= (others => '0');\r
- --stat_sync_dlm_inv_counter_i <= (others => '0');\r
- --saw_lb_v := '0';\r
- --saw_hb_v := '0';\r
- \r
- --else\r
- --if see_dlm_hb_buf_i = '1' and saw_lb_v = '1' then\r
- --stat_sync_dlm_counter_i <= stat_sync_dlm_counter_i + 1;\r
- --end if;\r
- \r
- --if see_dlm_lb_aggr_i = '1' and saw_hb_v = '1' then\r
- --stat_sync_dlm_inv_counter_i <= stat_sync_dlm_inv_counter_i + 1;\r
- --end if;\r
- \r
- --saw_lb_v := see_dlm_lb_aggr_i;\r
- --saw_hb_v := see_dlm_hb_buf_i;\r
- --end if;\r
- --end process;\r
- \r
- --see_dlm_lb_i(0) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(10, 3) else '0';\r
- --see_dlm_lb_i(1) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 1) else '0';\r
- --see_dlm_lb_i(2) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 1) else '0';\r
- --see_dlm_lb_i(3) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 6) else '0';\r
- \r
- --see_dlm_lb_i(4) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(22, 3) else '0';\r
- --see_dlm_lb_i(5) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 2) else '0';\r
- --see_dlm_lb_i(6) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 5) else '0';\r
- --see_dlm_lb_i(7) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(06, 2) else '0';\r
- \r
- --see_dlm_lb_i(8) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 6) else '0';\r
- --see_dlm_lb_i(9) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 1) else '0';\r
- --see_dlm_lb_i(10)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(11, 2) else '0';\r
- --see_dlm_lb_i(11)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 2) else '0';\r
- \r
- --see_dlm_lb_i(12)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(25, 3) else '0';\r
- --see_dlm_lb_i(13)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 5) else '0';\r
- --see_dlm_lb_i(14)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 6) else '0';\r
- --see_dlm_lb_i(15)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 5, 3) else '0';\r
-\r
- --see_dlm_lb_buf_i <= see_dlm_lb_i when rising_edge(rclk_250_i);\r
- \r
- \r
- end generate;\r
+--Media interface for Lattice ECP3 using PCS at 2.5GHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+use work.cbmnet_interface_pkg.all;
+use work.cbmnet_phy_pkg.all;
+
+entity cbmnet_phy_ecp3 is
+ generic(
+ IS_SYNC_SLAVE : integer := c_YES; --select slave mode
+ DETERMINISTIC_LATENCY : integer := c_YES; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)
+ IS_SIMULATED : integer := c_NO;
+ INCL_DEBUG_AIDS : integer := c_YES
+ );
+ port(
+ CLK : in std_logic; -- *internal* 125 MHz reference clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+
+ --Internal Connection TX
+ PHY_TXDATA_IN : in std_logic_vector(15 downto 0);
+ PHY_TXDATA_K_IN : in std_logic_vector( 1 downto 0);
+
+ --Internal Connection RX
+ PHY_RXDATA_OUT : out std_logic_vector(15 downto 0) := (others => '0');
+ PHY_RXDATA_K_OUT : out std_logic_vector( 1 downto 0) := (others => '0');
+
+ CLK_RX_HALF_OUT : out std_logic := '0'; -- recovered 125 MHz
+ CLK_RX_FULL_OUT : out std_logic := '0'; -- recovered 250 MHz
+ CLK_RX_RESET_OUT : out std_logic := '1';
+
+ LINK_ACTIVE_OUT : out std_logic; -- link is active and can send and receive data
+ SERDES_ready : out std_logic;
+
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic := '0';
+ SD_RXD_N_IN : in std_logic := '0';
+ SD_TXD_P_OUT : out std_logic := '0';
+ SD_TXD_N_OUT : out std_logic := '0';
+
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place,entity '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
+
+ LED_RX_OUT : out std_logic;
+ LED_TX_OUT : out std_logic;
+ LED_OK_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_OP : out std_logic_vector ( 15 downto 0) := (others => '0');
+ CTRL_OP : in std_logic_vector ( 15 downto 0) := (others => '0');
+ DEBUG_OUT : out std_logic_vector (511 downto 0) := (others => '0')
+ );
+end entity;
+
+architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of cbmnet_phy_ecp3_arch : architecture is "cbmnet_phy_group";
+
+ attribute syn_hier: string;
+ attribute syn_hier of cbmnet_phy_ecp3_arch : architecture is "hard";
+
+
+ attribute syn_sharing : string;
+ attribute syn_sharing of cbmnet_phy_ecp3_arch : architecture is "off";
+
+ constant WA_FIXATION : integer := c_YES;
+ signal DETERMINISTIC_LATENCY_C : std_logic;
+
+-- Clocks and global resets
+ signal clk_125_local : std_logic; -- local 125 MHz reference clock driven by clock generators
+ signal rclk_250_i : std_logic; -- recovered word clock
+ signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word
+ signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL
+
+ signal clk_tx_half_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL
+
+ signal rst_i : std_logic; -- High-active reset driven by external logic
+ signal rst_n_i : std_logic; -- Low-active version of rst_i
+
+-- SERDES/PCS
+ -- status
+ signal rx_los_low_i : std_logic;
+ signal rx_cdr_lol_i : std_logic;
+ signal tx_pll_lol_i : std_logic;
+ signal lsm_status_i : std_logic;
+
+ signal rx_dec_error_i: std_logic;
+ signal rx_dec_error_delayed_i : std_logic;
+ signal rx_dec_error_250_i : std_logic_vector(1 downto 0);
+ signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(3 downto 0);
+
+ signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition"
+
+ -- resets
+ signal rst_qd_i : std_logic;
+ signal serdes_rst_qd_i : std_logic;
+
+ signal tx_serdes_rst_i : std_logic;
+ signal tx_pcs_rst_i : std_logic;
+
+ signal rx_serdes_rst_i : std_logic;
+ signal rx_pcs_rst_i : std_logic;
+
+ -- data
+ signal tx_data_to_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES
+ signal rx_data_from_serdes_i : std_logic_vector( 8 downto 0); -- received by SERDES
+
+ -- status & control interface (and obtained info)
+ signal sci_ch_i : std_logic_vector(3 downto 0);
+ signal sci_qd_i : std_logic;
+ signal sci_reg_i : std_logic;
+ signal sci_addr_i : std_logic_vector(8 downto 0);
+ signal sci_data_in_i : std_logic_vector(7 downto 0) := (others => '0');
+ signal sci_data_out_i : std_logic_vector(7 downto 0);
+ signal sci_read_i : std_logic;
+ signal sci_write_i : std_logic;
+ signal sci_write_shift_i : std_logic_vector(2 downto 0);
+ signal sci_read_shift_i : std_logic_vector(2 downto 0);
+
+ signal wa_position_i : std_logic_vector(15 downto 0) := x"FFFF";
+ signal barrel_shifter_misaligned_i: std_logic;
+
+-- RESET FSM
+ signal rx_rst_fsm_state_i : std_logic_vector(3 downto 0);
+ signal tx_rst_fsm_state_i : std_logic_vector(3 downto 0);
+ signal tx_rst_fsm_ready_i : std_logic;
+ signal tx_rst_fsm_ready_buf_i : std_logic;
+
+ signal byte_alignment_to_fsm_i : std_logic;
+ signal word_alignment_to_fsm_i : std_logic;
+
+ signal rx_rst_fsm_ready_i : std_logic;
+
+ signal serdes_ready_i : std_logic;
+
+-- SCI Logic to obtain the barrel shifter position
+ type sci_ctrl is (IDLE, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+ signal sci_state : sci_ctrl;
+ signal sci_timer : unsigned( 7 downto 0) := (others => '0');
+ signal start_timer : unsigned(18 downto 0) := (others => '0');
+
+-- GEAR
+ signal gear_to_fsm_rst_i : std_logic;
+ signal gear_to_rm_rst_i : std_logic; -- gear keeps CBMNet ready manager reset until gear locked successfully
+ signal gear_to_rm_n_rst_i : std_logic; -- inverted version of above
+
+ signal rx_data_from_gear_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated by gear
+
+ signal rx_data_i : std_logic_vector(17 downto 0); -- in the front end this signal is identical to rx_data_from_gear_i
+ -- otherwise a clock domain crossing from rclk_125_i to clk_125_local is
+ -- necessary. this signal will not exhibit a deterministic latency !!!!!!
+ -- (however, this is no problem, as the clock master will not receive DLMs)
+
+ signal rx_data_debug_i : std_logic_vector(17 downto 0);
+
+ signal tx_data_i : std_logic_vector(17 downto 0); -- 16(+2) bit word generated fed to gear
+ signal tx_gear_reset_i : std_logic;
+ signal tx_gear_allow_relock_i : std_logic;
+
+ signal tx_gear_ready_i : std_logic;
+
+ signal rx_gear_debug_i : std_logic_vector(31 downto 0);
+ signal tx_gear_debug_i : std_logic_vector(31 downto 0);
+
+-- CBMNet Ready Managers
+ signal rm_rx_ready_i : std_logic;
+ signal rm_rx_almost_ready_i : std_logic;
+ signal rm_rx_status_for_tx_i : std_logic;
+ signal rm_rx_see_ready0_i : std_logic;
+ signal rm_rx_saw_ready1_i : std_logic;
+ signal rm_rx_valid_char_i : std_logic;
+
+ signal rm_tx_ready_i : std_logic;
+ signal rm_tx_almost_ready_i : std_logic;
+
+ signal rm_rx_to_gear_reset_i : std_logic;
+
+ signal rm_rx_data_buf_i : std_logic_vector(17 downto 0);
+
+ signal rm_rx_ebtb_code_err_cntr_clr_i : std_logic;
+ signal rm_rx_ebtb_disp_err_cntr_clr_i : std_logic;
+ signal rm_rx_ebtb_code_err_cntr_i : std_logic_vector(15 downto 0);
+ signal rm_rx_ebtb_disp_err_cntr_i : std_logic_vector(15 downto 0);
+ signal rm_rx_ebtb_code_err_cntr_flag_i : std_logic;
+ signal rm_rx_ebtb_disp_err_cntr_flag_i : std_logic;
+
+ signal rm_tx_to_rx_reinit_i : std_logic;
+
+ signal rm_rx_see_reinit : std_logic;
+ signal rm_rx_ebtb_detect_i : std_logic;
+ signal rm_tx_link_lost_i : std_logic;
+
+ signal rm_tx_pcs_startup_cntr_clr : std_logic;
+ signal rm_tx_pcs_startup_cntr : std_logic_vector(15 downto 0); -- Counts for link startups
+ signal rm_tx_pcs_startup_cntr_flag : std_logic;
+
+ signal rm_rx_rxpcs_ready_i : std_logic;
+
+-- LEDs
+ signal led_ok_i : std_logic;
+ signal led_tx_i, last_led_tx_i : std_logic;
+ signal led_rx_i, last_led_rx_i : std_logic;
+ signal led_timer_i : unsigned(20 downto 0);
+
+-- Stats
+ signal stat_reconnect_counter_i : unsigned(15 downto 0); -- counts the number of RX-serdes resets since last external reset
+ signal stat_last_reconnect_duration_i : unsigned(31 downto 0);
+ signal stat_decode_error_counter_i : unsigned(31 downto 0);
+
+
+ signal stat_wa_int_i : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal tx_data_debug_i : std_logic_vector(17 downto 0);
+ signal tx_data_debug_state_i : std_logic;
+
+ signal low_level_rx_see_dlm0 : std_logic;
+ signal low_level_tx_see_dlm0 : std_logic;
+ signal low_level_tx_see_dlm0_125 : std_logic;
+
+ signal stat_dlm_counter_i : unsigned(15 downto 0);
+ signal stat_init_ack_counter_i : unsigned(15 downto 0);
+
+ signal test_line_i : std_logic_vector(15 downto 0) := x"0001";
+
+ signal rx_stab_i, tx_stab_i : unsigned(15 downto 0);
+
+ signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0);
+
+ --signal see_dlm_lb_i, see_dlm_lb_buf_i : std_logic_vector(15 downto 0) := (others => '0');
+ --signal see_dlm_lb_aggr_i, see_dlm_hb_i, see_dlm_hb_buf_i : std_logic;
+ --signal stat_sync_dlm_counter_i, stat_sync_dlm_inv_counter_i : unsigned(7 downto 0);
+
+begin
+ assert IS_SYNC_SLAVE = c_YES
+ report "Support of clock master PHY is not tested anymore and probably broken"
+ severity failure;
+
+ DETERMINISTIC_LATENCY_C <= '1' when DETERMINISTIC_LATENCY = c_YES else '0';
+
+ clk_125_local <= CLK;
+ CLK_RX_HALF_OUT <= rclk_125_i;
+ CLK_RX_FULL_OUT <= rclk_250_i;
+
+ SD_TXDIS_OUT <= '0';
+
+ rst_i <= (CLEAR or CTRL_OP(0));
+ rst_n_i <= not rst_i;
+
+ -------------------------------------------------
+ -- Serdes
+ -------------------------------------------------
+ THE_SERDES : cbmnet_sfp1
+ port map(
+ -- SERIAL DATA PORTS
+ hdinp_ch0 => SD_RXD_P_IN,
+ hdinn_ch0 => SD_RXD_N_IN,
+ hdoutp_ch0 => SD_TXD_P_OUT,
+ hdoutn_ch0 => SD_TXD_N_OUT,
+
+ -- CLOCKS
+ rx_full_clk_ch0 => rclk_250_i,
+ rx_half_clk_ch0 => open, -- recovered (and correctly aligned) 125 MHz clock is generated by gear
+
+ tx_full_clk_ch0 => clk_tx_full_i,
+ tx_half_clk_ch0 => open,
+
+ fpga_rxrefclk_ch0 => clk_125_local,
+ fpga_txrefclk => rclk_125_i,
+ txiclk_ch0 => rclk_250_i,
+
+ -- RESETS
+ rst_qd_c => rst_qd_i,
+ serdes_rst_qd_c => serdes_rst_qd_i, -- always 0
+ tx_serdes_rst_c => tx_serdes_rst_i, -- always 0
+ rx_serdes_rst_ch0_c => rx_serdes_rst_i,
+ tx_pcs_rst_ch0_c => tx_pcs_rst_i,
+ rx_pcs_rst_ch0_c => rx_pcs_rst_i,
+
+ tx_pwrup_ch0_c => '1',
+ rx_pwrup_ch0_c => '1',
+
+ -- TX DATA PORT
+ txdata_ch0 => tx_data_to_serdes_i(7 downto 0),
+ tx_k_ch0 => tx_data_to_serdes_i(8),
+
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ tx_div2_mode_ch0_c => '0',
+
+ -- RX DATA PORT
+ rxdata_ch0 => rx_data_from_serdes_i(7 downto 0),
+ rx_k_ch0 => rx_data_from_serdes_i(8),
+
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_dec_error_i,
+ rx_div2_mode_ch0_c => '0',
+
+ -- LOOPBACK
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+
+ -- STATUS
+ tx_pll_lol_qd_s => tx_pll_lol_i,
+ rx_los_low_ch0_s => rx_los_low_i,
+ rx_cdr_lol_ch0_s => rx_cdr_lol_i,
+ lsm_status_ch0_s => lsm_status_i,
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_qd_i,
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i
+ );
+
+ THE_RX_GEAR: CBMNET_PHY_RX_GEAR
+ generic map (
+ IS_SYNC_SLAVE => IS_SYNC_SLAVE
+ ) port map (
+ -- SERDES PORT
+ CLK_250_IN => rclk_250_i, -- in std_logic;
+ PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic;
+ SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic;
+ DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0);
+
+ -- RM PORT
+ RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic;
+ CLK_125_OUT => rclk_125_i, -- out std_logic;
+ RESET_OUT => gear_to_rm_rst_i, -- out std_logic;
+ DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0)
+
+ DEBUG_OUT => rx_gear_debug_i
+ );
+
+ rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local);
+
+ THE_TX_GEAR: CBMNET_PHY_TX_GEAR
+ generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)
+ port map (
+ CLK_250_IN => clk_tx_full_i, -- in std_logic;
+ CLK_125_IN => rclk_125_i, -- in std_logic;
+ CLK_125_OUT => clk_tx_half_i,
+
+ RESET_IN => tx_gear_reset_i, -- in std_logic;
+ ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic
+
+ TX_READY_OUT => tx_gear_ready_i,
+
+ DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0)
+ DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0);
+ );
+ tx_gear_reset_i <= not tx_rst_fsm_ready_i;
+ tx_gear_allow_relock_i <= '0';
+
+
+
+ tx_serdes_rst_i <= '0'; --no function
+ serdes_rst_qd_i <= '0'; --included in rst_qd_i
+
+ -------------------------------------------------
+ -- Reset FSM & Link states
+ -------------------------------------------------
+ THE_RX_FSM : cbmnet_phy_ecp3_rx_reset_fsm
+ generic map (
+ IS_SIMULATED => IS_SIMULATED
+ )
+ port map(
+ RST_N => rst_n_i,
+ RX_REFCLK => clk_125_local,
+ TX_PLL_LOL_QD_S => tx_pll_lol_i,
+ RX_CDR_LOL_CH_S => rx_cdr_lol_i,
+ RX_LOS_LOW_CH_S => rx_los_low_i,
+
+ RM_RESET_IN => CTRL_OP(4), --rx_reset_from_rm_i,
+ PROPER_BYTE_ALIGN_IN=> byte_alignment_to_fsm_i,
+ PROPER_WORD_ALIGN_IN=> word_alignment_to_fsm_i,
+
+ RX_SERDES_RST_CH_C => rx_serdes_rst_i,
+ RX_PCS_RST_CH_C => rx_pcs_rst_i,
+ STATE_OUT => rx_rst_fsm_state_i
+ );
+ byte_alignment_to_fsm_i <= not (DETERMINISTIC_LATENCY_C and barrel_shifter_misaligned_i) or CTRL_OP(3);
+ word_alignment_to_fsm_i <= not (gear_to_fsm_rst_i or AND_ALL(rx_error_delay)) or CTRL_OP(5);
+
+
+-- -- decode error
+-- rx_dec_error_delayed_i <= rx_dec_error_delayed_i when rising_edge(rclk_250_i);
+-- rx_dec_error_250_i <= rx_dec_error_i & rx_dec_error_delayed_i when rising_edge(rclk_250_i);
+--
+-- rx_dec_error_125_i <= rx_dec_error_125_i(0) & rx_dec_error_i when rising_edge(clk_125_local);
+-- rx_dec_error_125_buf_i <= rx_dec_error_125_i when rising_edge(clk_125_local);
+--
+-- rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);
+-- process is
+-- begin
+-- wait until rising_edge(rclk_125_i);
+-- if RESET='1' then
+-- stat_decode_error_counter_i <= (others => '0');
+-- elsif rx_dec_error_125_buf_i = "11" then
+-- stat_decode_error_counter_i <= stat_decode_error_counter_i + 2;
+-- elsif rx_dec_error_125_buf_i = "10" or rx_dec_error_125_buf_i = "01" then
+-- stat_decode_error_counter_i <= stat_decode_error_counter_i + 1;
+-- end if;
+-- end process;
+
+
+ THE_TX_FSM : cbmnet_phy_ecp3_tx_reset_fsm
+ generic map (
+ IS_SIMULATED => IS_SIMULATED
+ )
+ port map(
+ RST_N => rst_n_i,
+ TX_REFCLK => clk_125_local,
+ TX_PLL_LOL_QD_S => tx_pll_lol_i,
+ RST_QD_C => rst_qd_i,
+ TX_PCS_RST_CH_C => tx_pcs_rst_i,
+ STATE_OUT => tx_rst_fsm_state_i
+ );
+
+ proc_rst_fsms_ready: process is begin
+ wait until rising_edge(clk_125_local);
+ rx_rst_fsm_ready_i <= '0';
+ if rx_rst_fsm_state_i = x"6" then
+ rx_rst_fsm_ready_i <= '1';
+ end if;
+
+ tx_rst_fsm_ready_i <= '0';
+ if tx_rst_fsm_state_i = x"5" then
+ tx_rst_fsm_ready_i <= '1';
+ end if;
+ end process;
+
+ -------------------------------------------------
+ -- CBMNet Ready Modules
+ -------------------------------------------------
+ THE_RX_READY: cn_rx_pcs_wrapper
+ generic map (
+ SIMULATION => 0,
+ USE_BS => 0,
+ SYNC_SIGNALS => 1,
+ INCL_8B10B_DEC => 0
+ )
+ port map (
+ rx_clk => rclk_125_i, -- in std_logic;
+ res_n_rx => gear_to_rm_n_rst_i, -- in std_logic;
+ rxpcs_reinit => rm_tx_to_rx_reinit_i, -- in std_logic; -- Reinit RXPCS
+ rxdata_in(17 downto 0) => rx_data_i,
+ rxdata_in(19 downto 18) => "00",
+ reset_rx_cdr => rm_rx_to_gear_reset_i, -- out std_logic; -- Reset RX CDR to align
+ rxpcs_almost_ready => rm_rx_almost_ready_i, -- out std_logic; -- Ready1 detected, only waiting for break
+ rxpcs_ready => rm_rx_rxpcs_ready_i, -- out std_logic; -- RXPCS initialization done
+ see_reinit => rm_rx_see_reinit, -- out std_logic; -- Initialization pattern detected although ready
+ bs_position => open, -- out std_logic_vector(4 downto 0); -- Number of bit-shifts necessary for word-alignment
+ rxdata_out => rm_rx_data_buf_i, -- out std_logic_vector(17 downto 0);
+ ebtb_detect => rm_rx_ebtb_detect_i, -- out std_logic; -- Depends on the FSM state, alignment done
+
+ --diagnostics
+ ebtb_code_err_cntr_clr => '0', -- in std_logic;
+ ebtb_disp_err_cntr_clr => '0', -- in std_logic;
+ ebtb_code_err_cntr => open, -- out std_logic_vector(15 downto 0); -- Counts for code errors if ebtb_detect is true
+ ebtb_disp_err_cntr => open, -- out std_logic_vector(15 downto 0); -- Counts for disparity errors if ebtb_detect is true
+ ebtb_code_err_cntr_flag => open,-- out std_logic;
+ ebtb_disp_err_cntr_flag => open -- out std_logic
+ );
+
+ PHY_RXDATA_OUT <= rx_data_i(15 downto 0);
+ PHY_RXDATA_K_OUT <= rx_data_i(17 downto 16);
+ gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(rclk_125_i);
+
+
+ THE_TX_READY: cn_tx_pcs_wrapper
+ generic map (
+ REVERSE_OUTPUT => 0, --integer range 0 to 1 := 1;
+ LINK_MASTER => 0, --integer range 0 to 1 := 1;
+ SYNC_SIGNALS => 1, --integer range 0 to 1 := 1;
+
+ INCL_8B10B_ENC => 0 --integer range 0 to 1 := 1
+ ) port map (
+ tx_clk => rclk_125_i, --in std_logic;
+ res_n_tx => tx_rst_fsm_ready_buf_i, --in std_logic;
+ pcs_restart => CTRL_OP(14), --in std_logic; -- restart pcs layer
+ pma_ready => tx_gear_ready_i, --in std_logic;
+ ebtb_detect => rm_rx_ebtb_detect_i, --in std_logic; -- alignment done and valid 8b10b stream detected
+ see_reinit => rm_rx_see_reinit, --in std_logic;
+ rxpcs_almost_ready => rm_rx_almost_ready_i, --in std_logic;
+ txdata_in(15 downto 0) => PHY_TXDATA_IN, --in std_logic_vector(17 downto 0);
+ txdata_in(17 downto 16)=> PHY_TXDATA_K_IN,
+
+ txpcs_ready => rm_tx_ready_i, --out std_logic;
+ link_lost => rm_tx_link_lost_i, --out std_logic;
+ reset_out => open, --out std_logic;
+ rxpcs_reinit => rm_tx_to_rx_reinit_i, --out std_logic; -- Reinit the RXPCS FSM
+ txdata_out => tx_data_i, --out std_logic_vector(17 downto 0); -- tx data to transceiver
+ txdata_out_coded => open, --out std_logic_vector(19 downto 0); -- tx data to transceiver already 8b10b coded
+
+ --diagnostics
+ pcs_startup_cntr_clr => rm_tx_pcs_startup_cntr_clr, --in std_logic;
+ pcs_startup_cntr => rm_tx_pcs_startup_cntr, --out std_logic_vector(15 downto 0); -- Counts for link startups
+ pcs_startup_cntr_flag => rm_tx_pcs_startup_cntr_flag --out std_logic;
+ );
+
+
+ rm_rx_status_for_tx_i <= rm_rx_almost_ready_i or rm_rx_ready_i;
+
+ -- clock domain crossing from clk_125_local to rclk_125_i
+ PROC_SYNC_FSM_READY: process is begin
+ wait until rising_edge(rclk_125_i);
+
+ if IS_SYNC_SLAVE = c_YES then
+ tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i and not gear_to_rm_rst_i;
+
+ else
+ tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i;
+
+ end if;
+ end process;
+
+ serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(rclk_125_i);
+ led_ok_i <= serdes_ready_i;
+ SERDES_ready <= serdes_ready_i;
+
+ -------------------------------------------------
+ -- SCI
+ -------------------------------------------------
+ -- gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+ -- upon retrival the barrel shifter is checked and - if necessary - a serdes reset is issued
+ PROC_SCI_CTRL: process
+ variable cnt : integer range 0 to 4 := 0;
+ begin
+ wait until rising_edge(clk_125_local);
+
+ case sci_state is
+ when IDLE =>
+ sci_ch_i <= x"0";
+ sci_qd_i <= '0';
+ sci_reg_i <= '0';
+ sci_read_i <= '0';
+ sci_write_i <= '0';
+ sci_timer <= sci_timer + 1;
+ if sci_timer(sci_timer'left) = '1' then
+ sci_timer <= (others => '0');
+ sci_state <= GET_WA;
+ end if;
+
+ when GET_WA =>
+ if cnt = 4 then
+ cnt := 0;
+ sci_state <= IDLE;
+
+ else
+ sci_state <= GET_WA_WAIT;
+ sci_addr_i <= '0' & x"22";
+ sci_ch_i <= x"0";
+ sci_ch_i(cnt) <= '1';
+ sci_read_i <= '1';
+ end if;
+
+ when GET_WA_WAIT =>
+ sci_state <= GET_WA_WAIT2;
+
+ when GET_WA_WAIT2 =>
+ sci_state <= GET_WA_FINISH;
+
+ when GET_WA_FINISH =>
+ wa_position_i(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+ sci_state <= GET_WA;
+ cnt := cnt + 1;
+
+ end case;
+ end process;
+
+ process is begin
+ wait until rising_edge(clk_125_local);
+ barrel_shifter_misaligned_i <= '0';
+ if lsm_status_i = '1' and wa_position_i(3 downto 0) /= x"0" then
+ barrel_shifter_misaligned_i <= '1';
+ end if;
+ end process;
+
+ -- Produce 1us reset pulse for external logic
+ PROC_CLK_RESET: process is
+ variable counter : unsigned(8 downto 0) := (others => '0');
+ begin
+ wait until rising_edge(rclk_125_i);
+ CLK_RX_RESET_OUT <= '1';
+
+ if serdes_ready_i = '0' then
+ counter := (others => '0');
+
+ elsif counter(counter'high) = '0' then
+ counter := counter + 1;
+
+ else
+ CLK_RX_RESET_OUT <= '0';
+
+ end if;
+ end process;
+
+
+ GEN_DEBUG: if INCL_DEBUG_AIDS = c_YES generate
+ proc_stat: process is
+ variable last_rx_serdes_rst_i : std_logic;
+ begin
+ wait until rising_edge(clk_125_local);
+
+ if rst_n_i = '0' then
+ stat_reconnect_counter_i <= (others => '0');
+ stat_last_reconnect_duration_i <= (others => '0');
+ stat_wa_int_i <= (others => '0');
+ else
+ if rx_serdes_rst_i = '1' and last_rx_serdes_rst_i = '0' then
+ stat_reconnect_counter_i <= stat_reconnect_counter_i + TO_UNSIGNED(1,1);
+ end if;
+
+ if serdes_ready_i = '0' then
+ stat_last_reconnect_duration_i <= stat_last_reconnect_duration_i + TO_UNSIGNED(1,1);
+ end if;
+
+ stat_wa_int_i <= stat_wa_int_i or wa_position_i;
+ end if;
+
+ last_rx_serdes_rst_i := rx_serdes_rst_i;
+ end process;
+
+ PROC_SENSE_TX_DLM125: process is
+ begin
+ wait until rising_edge(rclk_125_i);
+
+ low_level_tx_see_dlm0_125 <= '0';
+ if tx_data_i = "10" & x"fb6a" then
+ low_level_tx_see_dlm0_125 <= '1';
+ end if;
+ end process;
+
+ process is
+ variable rx_v, tx_v : std_logic_vector(17 downto 0);
+ begin
+ wait until rising_edge(rclk_125_i);
+
+ if reset = '1' or rx_v /= rx_data_i then rx_stab_i <= (others => '0');
+ else rx_stab_i <= rx_stab_i + 1; end if;
+
+ if reset = '1' or tx_v /= tx_data_i then tx_stab_i <= (others => '0');
+ else tx_stab_i <= tx_stab_i + 1; end if;
+
+ rx_v := rx_data_i;
+ tx_v := tx_data_i;
+ end process;
+
+
+ PROC_SENSE_DLMS: process begin
+ wait until rising_edge(rclk_125_i);
+
+ if serdes_ready_i = '0' then
+ stat_dlm_counter_i <= (others => '0');
+ elsif rx_data_i(17) = '1' and rx_data_i(15 downto 8) = K277 then
+ stat_dlm_counter_i <= stat_dlm_counter_i + TO_UNSIGNED(1,1);
+ end if;
+ end process;
+
+-- DEBUG_OUT_BEGIN
+ DEBUG_OUT(19 downto 0) <= "00" & tx_data_i(17 downto 0);
+ DEBUG_OUT(23 downto 20) <= "0" & tx_pll_lol_i & rx_los_low_i & rx_cdr_lol_i;
+
+ DEBUG_OUT(27 downto 24) <= gear_to_fsm_rst_i & barrel_shifter_misaligned_i & SD_PRSNT_N_IN & SD_LOS_IN;
+ DEBUG_OUT(31 downto 28) <= rst_qd_i & rx_serdes_rst_i & tx_pcs_rst_i & rx_pcs_rst_i;
+
+ DEBUG_OUT( 51 downto 32) <= "00" & rx_data_i(17 downto 0);
+ DEBUG_OUT( 59 downto 52) <= rx_rst_fsm_state_i(3 downto 0) & tx_rst_fsm_state_i(3 downto 0);
+
+ DEBUG_OUT( 63 downto 60) <= serdes_ready_i & rm_rx_ready_i & rm_tx_ready_i & rm_tx_almost_ready_i;
+
+ DEBUG_OUT( 79 downto 64) <= rx_gear_debug_i(15 downto 0);
+ DEBUG_OUT( 95 downto 80) <= tx_gear_debug_i(15 downto 0);
+
+ DEBUG_OUT( 99 downto 96) <= rm_rx_almost_ready_i & rm_rx_rxpcs_ready_i & rm_rx_see_reinit & rm_rx_ebtb_detect_i;
+ DEBUG_OUT(103 downto 100) <= wa_position_i(3 downto 0);
+ DEBUG_OUT(107 downto 104) <= word_alignment_to_fsm_i & byte_alignment_to_fsm_i & rm_rx_to_gear_reset_i & gear_to_rm_rst_i;
+
+ DEBUG_OUT(123 downto 108) <= tx_stab_i(15 downto 0);
+
+ DEBUG_OUT(139 downto 124) <= rx_stab_i(15 downto 0);
+ DEBUG_OUT(147 downto 140) <= stat_init_ack_counter_i(7 downto 0);
+ DEBUG_OUT(179 downto 148) <= stat_last_reconnect_duration_i(31 downto 0);
+
+ DEBUG_OUT(195 downto 180) <= stat_reconnect_counter_i(15 downto 0);
+ DEBUG_OUT(211 downto 196) <= stat_dlm_counter_i(15 downto 0);
+ DEBUG_OUT(243 downto 212) <= rm_rx_ebtb_code_err_cntr_i(15 downto 0) & rm_rx_ebtb_disp_err_cntr_i(15 downto 0);
+
+ DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0);
+
+ DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);
+ --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i);
+ --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i);
+
+
+
+ --DEBUG_OUT(255 downto 170) <= (others => '0');
+
+-- DEBUG_OUT_END
+
+ process is
+ begin
+ wait until rising_edge(rclk_125_i);
+ if rx_data_i /= "10" & x"fcc3" then
+ rx_data_sp_i0 <= rx_data_i;
+ rx_data_sp_i1 <= rx_data_sp_i0;
+ rx_data_sp_i2 <= rx_data_sp_i1;
+ rx_data_sp_i3 <= rx_data_sp_i2;
+ end if;
+ end process;
+
+ --PROC_SEE_FAST_DLM: process is
+ --variable saw_lb_v, saw_hb_v : std_logic;
+ --begin
+ --wait until rising_edge(rclk_250_i);
+
+ --see_dlm_hb_i <= '0' ;
+ --if rx_data_from_serdes_i = '1' & K277 then
+ --see_dlm_hb_i <= '1';
+ --end if;
+ --see_dlm_hb_buf_i <= see_dlm_hb_i;
+
+ --see_dlm_lb_aggr_i <= '0';
+ --if rx_data_from_serdes_i = '1' & K277 then
+ --see_dlm_lb_aggr_i <= OR_ALL(see_dlm_lb_buf_i);
+ --end if;
+
+
+
+ --if rst_i = '1' then
+ --stat_sync_dlm_counter_i <= (others => '0');
+ --stat_sync_dlm_inv_counter_i <= (others => '0');
+ --saw_lb_v := '0';
+ --saw_hb_v := '0';
+
+ --else
+ --if see_dlm_hb_buf_i = '1' and saw_lb_v = '1' then
+ --stat_sync_dlm_counter_i <= stat_sync_dlm_counter_i + 1;
+ --end if;
+
+ --if see_dlm_lb_aggr_i = '1' and saw_hb_v = '1' then
+ --stat_sync_dlm_inv_counter_i <= stat_sync_dlm_inv_counter_i + 1;
+ --end if;
+
+ --saw_lb_v := see_dlm_lb_aggr_i;
+ --saw_hb_v := see_dlm_hb_buf_i;
+ --end if;
+ --end process;
+
+ --see_dlm_lb_i(0) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(10, 3) else '0';
+ --see_dlm_lb_i(1) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 1) else '0';
+ --see_dlm_lb_i(2) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 1) else '0';
+ --see_dlm_lb_i(3) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 6) else '0';
+
+ --see_dlm_lb_i(4) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(22, 3) else '0';
+ --see_dlm_lb_i(5) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 2) else '0';
+ --see_dlm_lb_i(6) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 5) else '0';
+ --see_dlm_lb_i(7) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(06, 2) else '0';
+
+ --see_dlm_lb_i(8) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 6) else '0';
+ --see_dlm_lb_i(9) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 1) else '0';
+ --see_dlm_lb_i(10)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(11, 2) else '0';
+ --see_dlm_lb_i(11)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 2) else '0';
+
+ --see_dlm_lb_i(12)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(25, 3) else '0';
+ --see_dlm_lb_i(13)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 5) else '0';
+ --see_dlm_lb_i(14)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 6) else '0';
+ --see_dlm_lb_i(15)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 5, 3) else '0';
+
+ --see_dlm_lb_buf_i <= see_dlm_lb_i when rising_edge(rclk_250_i);
+
+
+ end generate;
end architecture;
\ No newline at end of file
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.trb3_components.all;\r
-use work.version.all;\r
-\r
-use work.cbmnet_interface_pkg.all;\r
-use work.cbmnet_phy_pkg.all;\r
-\r
-\r
-entity trb3_periph_cbmnet is\r
- generic (\r
- CBM_FEE_MODE : integer := CBM_FEE_MODE_C; -- in FEE mode, logic will run on recovered clock and (for now) listen only to data received\r
- -- in Master mode, logic will run on internal clock and regularly send dlms\r
- INCLUDE_TRBNET : integer := INCLUDE_TRBNET_C\r
- );\r
- port(\r
- --Clocks\r
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz\r
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA\r
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
-\r
- --Trigger\r
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out\r
- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out\r
-\r
- --Serdes\r
- CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible\r
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems\r
- SERDES_INT_TX : out std_logic_vector(3 downto 0);\r
- SERDES_INT_RX : in std_logic_vector(3 downto 0);\r
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);\r
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);\r
-\r
- --Inter-FPGA Communication\r
- FPGA5_COMM : inout std_logic_vector(11 downto 0);\r
- --Bit 0/1 input, serial link RX active\r
- --Bit 2/3 output, serial link TX active\r
- --others yet undefined\r
- --Connection to AddOn\r
- LED_LINKOK : out std_logic_vector(6 downto 1);\r
- LED_RX : out std_logic_vector(6 downto 1); \r
- LED_TX : out std_logic_vector(6 downto 1);\r
-\r
- SFP_MOD0 : in std_logic_vector(6 downto 1);\r
- SFP_TXDIS : out std_logic_vector(6 downto 1); \r
- SFP_LOS : in std_logic_vector(6 downto 1);\r
- SFP_MOD1 : out std_logic_vector(6 downto 1); \r
- SFP_MOD2 : inout std_logic_vector(6 downto 1); \r
-\r
- SFP_RATESEL: out std_logic_vector(6 downto 1); \r
- SFP_TXFAULT: in std_logic_vector(6 downto 1);\r
-\r
- --Flash ROM & Reboot\r
- FLASH_CLK : out std_logic;\r
- FLASH_CS : out std_logic;\r
- FLASH_DIN : out std_logic;\r
- FLASH_DOUT : in std_logic;\r
- PROGRAMN : out std_logic; --reboot FPGA\r
-\r
- --Misc\r
- TEMPSENS : inout std_logic; --Temperature Sensor\r
- CODE_LINE : in std_logic_vector(1 downto 0);\r
- LED_GREEN : out std_logic;\r
- LED_ORANGE : out std_logic;\r
- LED_RED : out std_logic;\r
- LED_YELLOW : out std_logic;\r
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads\r
-\r
- --Test Connectors\r
- TEST_LINE : out std_logic_vector(15 downto 0); \r
- --TEST_LVDS_LINE : out std_logic_vector(1 downto 0);\r
-\r
- -- PCS Core TODO: Suppose this is necessary only for simulation\r
- SD_RXD_N_IN : in std_logic;\r
- SD_RXD_P_IN : in std_logic;\r
- SD_TXD_N_OUT : out std_logic;\r
- SD_TXD_P_OUT : out std_logic\r
- );\r
- \r
- attribute syn_useioff : boolean;\r
- --no IO-FF for LEDs relaxes timing constraints\r
- attribute syn_useioff of LED_GREEN : signal is false;\r
- attribute syn_useioff of LED_ORANGE : signal is false;\r
- attribute syn_useioff of LED_RED : signal is false;\r
- attribute syn_useioff of LED_YELLOW : signal is false;\r
- attribute syn_useioff of TEMPSENS : signal is false;\r
- attribute syn_useioff of PROGRAMN : signal is false;\r
- attribute syn_useioff of CODE_LINE : signal is false;\r
- attribute syn_useioff of TRIGGER_LEFT : signal is false;\r
- attribute syn_useioff of TRIGGER_RIGHT : signal is false;\r
- attribute syn_useioff of LED_LINKOK : signal is false;\r
- attribute syn_useioff of LED_RX : signal is false;\r
- attribute syn_useioff of LED_TX : signal is false;\r
-\r
- --important signals _with_ IO-FF\r
- attribute syn_useioff of FLASH_CLK : signal is true;\r
- attribute syn_useioff of FLASH_CS : signal is true;\r
- attribute syn_useioff of FLASH_DIN : signal is true;\r
- attribute syn_useioff of FLASH_DOUT : signal is true;\r
- attribute syn_useioff of FPGA5_COMM : signal is true;\r
- attribute syn_useioff of TEST_LINE : signal is true;\r
-\r
- attribute nopad : string;\r
- attribute nopad of SD_RXD_N_IN, SD_RXD_P_IN, SD_TXD_N_OUT, SD_TXD_P_OUT : signal is "true";\r
- \r
- attribute syn_keep : boolean;\r
- attribute syn_keep of CLK_GPLL_LEFT, CLK_GPLL_RIGHT, CLK_PCLK_LEFT, CLK_PCLK_RIGHT, TRIGGER_LEFT, TRIGGER_RIGHT : signal is true;\r
- attribute syn_preserve : boolean;\r
- \r
-end entity;\r
-\r
-architecture trb3_periph_arch of trb3_periph_cbmnet is\r
---Constants\r
- constant REGIO_NUM_STAT_REGS : integer := 2;\r
- constant REGIO_NUM_CTRL_REGS : integer := 2;\r
-\r
-\r
- --Clock / Reset\r
- signal clk_125_i : std_logic; -- clock reference for CBMNet serdes\r
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL\r
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.\r
- signal pll_lock1, pll_lock2 : std_logic;\r
- signal clear_i : std_logic;\r
- signal reset_i : std_logic;\r
- signal GSR_N : std_logic;\r
-\r
- attribute syn_keep of GSR_N : signal is true;\r
- attribute syn_preserve of GSR_N : signal is true;\r
-\r
-\r
- signal rclk_125_i : std_logic; -- recovered clock \r
- signal rreset_i : std_logic; -- reset for recovered clock ~ 1us after clock becomes stable\r
-\r
-\r
- --Media Interface\r
- signal med_stat_op : std_logic_vector (1*16-1 downto 0) := (others => '0');\r
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);\r
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);\r
- signal med_data_out : std_logic_vector (1*16-1 downto 0);\r
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);\r
- signal med_dataready_out : std_logic;\r
- signal med_read_out : std_logic;\r
- signal med_data_in : std_logic_vector (1*16-1 downto 0);\r
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);\r
- signal med_dataready_in : std_logic;\r
- signal med_read_in : std_logic;\r
-\r
- --LVL1 channel\r
- signal timing_trg_received_i : std_logic;\r
- signal trg_data_valid_i : std_logic;\r
- signal trg_timing_valid_i : std_logic;\r
- signal trg_notiming_valid_i : std_logic;\r
- signal trg_invalid_i : std_logic;\r
- signal trg_type_i : std_logic_vector(3 downto 0);\r
- signal trg_number_i : std_logic_vector(15 downto 0);\r
- signal trg_code_i : std_logic_vector(7 downto 0);\r
- signal trg_information_i : std_logic_vector(23 downto 0);\r
- signal trg_int_number_i : std_logic_vector(15 downto 0);\r
- signal trg_multiple_trg_i : std_logic;\r
- signal trg_timeout_detected_i: std_logic;\r
- signal trg_spurious_trg_i : std_logic;\r
- signal trg_missing_tmg_trg_i : std_logic;\r
- signal trg_spike_detected_i : std_logic;\r
-\r
- --Data channel\r
- signal fee_trg_release_i : std_logic;\r
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);\r
- signal fee_data_i : std_logic_vector(31 downto 0);\r
- signal fee_data_write_i : std_logic;\r
- signal fee_data_finished_i : std_logic;\r
- signal fee_almost_full_i : std_logic;\r
-\r
- --Slow Control channel\r
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);\r
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);\r
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);\r
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);\r
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
-\r
- --RegIO\r
- signal my_address : std_logic_vector (15 downto 0);\r
- signal regio_addr_out : std_logic_vector (15 downto 0);\r
- signal regio_read_enable_out : std_logic;\r
- signal regio_write_enable_out : std_logic;\r
- signal regio_data_out : std_logic_vector (31 downto 0);\r
- signal regio_data_in : std_logic_vector (31 downto 0);\r
- signal regio_dataready_in : std_logic;\r
- signal regio_no_more_data_in : std_logic;\r
- signal regio_write_ack_in : std_logic;\r
- signal regio_unknown_addr_in : std_logic;\r
- signal regio_timeout_out : std_logic;\r
-\r
- --Timer\r
- signal global_time : std_logic_vector(31 downto 0);\r
- signal local_time : std_logic_vector(7 downto 0);\r
- signal time_since_last_trg : std_logic_vector(31 downto 0);\r
- signal timer_ticks : std_logic_vector(1 downto 0);\r
-\r
- --Flash\r
- signal spictrl_read_en : std_logic;\r
- signal spictrl_write_en : std_logic;\r
- signal spictrl_data_in : std_logic_vector(31 downto 0);\r
- signal spictrl_addr : std_logic;\r
- signal spictrl_data_out : std_logic_vector(31 downto 0);\r
- signal spictrl_ack : std_logic;\r
- signal spictrl_busy : std_logic;\r
- signal spimem_read_en : std_logic;\r
- signal spimem_write_en : std_logic;\r
- signal spimem_data_in : std_logic_vector(31 downto 0);\r
- signal spimem_addr : std_logic_vector(5 downto 0);\r
- signal spimem_data_out : std_logic_vector(31 downto 0);\r
- signal spimem_ack : std_logic;\r
-\r
- signal debug_read_en : std_logic;\r
- signal debug_write_en : std_logic;\r
- signal debug_data_in : std_logic_vector(31 downto 0);\r
- signal debug_addr : std_logic_vector(5 downto 0);\r
- signal debug_data_out : std_logic_vector(31 downto 0);\r
- signal debug_ack : std_logic;\r
- \r
- \r
- signal spi_bram_addr : std_logic_vector(7 downto 0);\r
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_we : std_logic;\r
-\r
- --FPGA Test\r
- signal time_counter : unsigned(31 downto 0);\r
-\r
- -- CBMNet signals\r
- constant NUM_LANES : integer := 1;\r
- signal cbm_res_n : std_logic; -- Active low reset; can be changed by define\r
- signal cbm_link_active : std_logic; -- link is active and can send and receive data\r
-\r
- signal cbm_ctrl2send_stop : std_logic := '0'; -- send control interface\r
- signal cbm_ctrl2send_start : std_logic := '0';\r
- signal cbm_ctrl2send_end : std_logic := '0';\r
- signal cbm_ctrl2send : std_logic_vector(15 downto 0) := (others => '0');\r
-\r
- signal cbm_data2send_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); -- send data interface\r
- signal cbm_data2send_start : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');\r
- signal cbm_data2send_end : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');\r
- signal cbm_data2send : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0');\r
-\r
- signal cbm_dlm2send_va : std_logic := '0'; -- send dlm interface\r
- signal cbm_dlm2send : std_logic_vector(3 downto 0) := (others => '0');\r
-\r
- signal cbm_dlm_rec_type : std_logic_vector(3 downto 0) := (others => '0'); -- receive dlm interface\r
- signal cbm_dlm_rec_va : std_logic := '0';\r
-\r
- signal cbm_data_rec : std_logic_vector((16*NUM_LANES)-1 downto 0); -- receive data interface\r
- signal cbm_data_rec_start : std_logic_vector(NUM_LANES-1 downto 0);\r
- signal cbm_data_rec_end : std_logic_vector(NUM_LANES-1 downto 0); \r
- signal cbm_data_rec_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others =>'0'); \r
-\r
- signal cbm_ctrl_rec : std_logic_vector(15 downto 0); -- receive control interface\r
- signal cbm_ctrl_rec_start : std_logic;\r
- signal cbm_ctrl_rec_end : std_logic; \r
- signal cbm_ctrl_rec_stop : std_logic;\r
-\r
- signal cbm_data_from_link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY\r
- signal cbm_data2link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY\r
-\r
- signal cbm_link_activeovr : std_logic := '0'; -- Overrides; set 0 by default\r
- signal cbm_link_readyovr : std_logic := '0';\r
-\r
- signal cbm_SERDES_ready : std_logic; -- signalize when PHY ready\r
-\r
- signal phy_stat_op, phy_ctrl_op : std_logic_vector(15 downto 0) := (others => '0');\r
- signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0');\r
- \r
- signal phy_debug_i : std_logic_vector (511 downto 0) := (others => '0');\r
- signal phy_debug_i_buf : std_logic_vector (511 downto 0);\r
- \r
-\r
--- Link Tester\r
- signal link_tester_ctrl_en :std_logic;\r
- signal link_tester_dlm_en :std_logic;\r
- signal link_tester_data_en :std_logic;\r
- \r
- signal link_tester_data_stop :std_logic;\r
- signal link_tester_ctrl_stop :std_logic;\r
- \r
- signal link_tester_data_valid:std_logic;\r
- signal link_tester_ctrl_valid:std_logic;\r
- signal link_tester_dlm_valid :std_logic;\r
-\r
-\r
- signal link_tester_ctrl : std_logic_vector(31 downto 0) := (others => '0');\r
- signal link_tester_stat : std_logic_vector(31 downto 0) := (others => '0');\r
- \r
- signal dummy : std_logic;\r
- \r
- type SEND_FSM_T is (START, SEND_HEADER, SEND_PACK_NUM, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT);\r
- signal send_fsm_i : SEND_FSM_T;\r
- signal send_length_i : unsigned(4 downto 0);\r
- signal send_num_pack_counter_i : unsigned(15 downto 0); \r
- signal send_enabled_i : std_logic := '0';\r
- \r
- signal send_wait_counter_i : std_logic_vector(31 downto 0);\r
- signal send_wait_threshold_i : std_logic_vector(31 downto 0);\r
- \r
- signal dlm_counter_i : unsigned(31 downto 0);\r
- signal dlm_glob_counter_i : unsigned(31 downto 0);\r
- \r
- \r
- -- diagnostics Lane0\r
- signal cbm_crc_error_cntr_flag_0 : std_logic;\r
- signal cbm_retrans_cntr_flag_0 : std_logic;\r
- signal cbm_retrans_error_cntr_flag_0 : std_logic;\r
- signal cbm_crc_error_cntr_0 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_cntr_0 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_error_cntr_0 : std_logic_vector(15 downto 0);\r
- signal cbm_crc_error_cntr_clr_0 : std_logic;\r
- signal cbm_retrans_cntr_clr_0 : std_logic;\r
- signal cbm_retrans_error_cntr_clr_0 : std_logic;\r
-\r
- -- diagnostics Lane1\r
- signal cbm_crc_error_cntr_flag_1 : std_logic;\r
- signal cbm_retrans_cntr_flag_1 : std_logic;\r
- signal cbm_retrans_error_cntr_flag_1 : std_logic;\r
- signal cbm_crc_error_cntr_1 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_cntr_1 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_error_cntr_1 : std_logic_vector(15 downto 0);\r
- signal cbm_crc_error_cntr_clr_1 : std_logic; \r
- signal cbm_retrans_cntr_clr_1 : std_logic; \r
- signal cbm_retrans_error_cntr_clr_1 : std_logic; \r
-\r
- -- diagnostics Lane2\r
- signal cbm_crc_error_cntr_flag_2 : std_logic;\r
- signal cbm_retrans_cntr_flag_2 : std_logic;\r
- signal cbm_retrans_error_cntr_flag_2 : std_logic;\r
- signal cbm_crc_error_cntr_2 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_cntr_2 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_error_cntr_2 : std_logic_vector(15 downto 0);\r
- signal cbm_crc_error_cntr_clr_2 : std_logic; \r
- signal cbm_retrans_cntr_clr_2 : std_logic; \r
- signal cbm_retrans_error_cntr_clr_2 : std_logic; \r
-\r
- -- diagnostics Lane3\r
- signal cbm_crc_error_cntr_flag_3 : std_logic;\r
- signal cbm_retrans_cntr_flag_3 : std_logic;\r
- signal cbm_retrans_error_cntr_flag_3 : std_logic;\r
- signal cbm_crc_error_cntr_3 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_cntr_3 : std_logic_vector(15 downto 0);\r
- signal cbm_retrans_error_cntr_3 : std_logic_vector(15 downto 0);\r
- signal cbm_crc_error_cntr_clr_3 : std_logic; \r
- signal cbm_retrans_cntr_clr_3 : std_logic; \r
- signal cbm_retrans_error_cntr_clr_3 : std_logic;\r
- \r
- signal cbm_debug_overrides_i : std_logic_vector(1 downto 0) := "00";\r
- \r
-begin\r
- clk_125_i <= CLK_GPLL_LEFT; \r
-\r
- assert(INCLUDE_TRBNET = c_YES);\r
- \r
----------------------------------------------------------------------------\r
--- CBMNet and PHY\r
---------------------------------------------------------------------------- \r
- THE_CBM_PHY: cbmnet_phy_ecp3\r
- generic map (IS_SYNC_SLAVE => CBM_FEE_MODE)\r
- port map (\r
- CLK => clk_125_i,\r
- RESET => reset_i,\r
- CLEAR => '0',\r
- \r
- --Internal Connection TX\r
- PHY_TXDATA_IN => cbm_data2link(15 downto 0),\r
- PHY_TXDATA_K_IN => cbm_data2link(17 downto 16),\r
- \r
- --Internal Connection RX\r
- PHY_RXDATA_OUT => cbm_data_from_link(15 downto 0),\r
- PHY_RXDATA_K_OUT => cbm_data_from_link(17 downto 16),\r
- \r
- CLK_RX_HALF_OUT => rclk_125_i,\r
- CLK_RX_FULL_OUT => open,\r
- CLK_RX_RESET_OUT => rreset_i,\r
-\r
- LINK_ACTIVE_OUT => open,\r
- SERDES_ready => cbm_SERDES_ready,\r
- \r
- --SFP Connection\r
- SD_RXD_P_IN => SD_RXD_P_IN,\r
- SD_RXD_N_IN => SD_RXD_N_IN,\r
- SD_TXD_P_OUT => SD_TXD_P_OUT,\r
- SD_TXD_N_OUT => SD_TXD_N_OUT,\r
-\r
- SD_PRSNT_N_IN => SFP_MOD0(1),\r
- SD_LOS_IN => SFP_LOS(1),\r
- SD_TXDIS_OUT => SFP_TXDIS(1),\r
- \r
- LED_RX_OUT => LED_RX(1),\r
- LED_TX_OUT => LED_TX(1),\r
- LED_OK_OUT => LED_LINKOK(1),\r
- \r
- -- Status and control port\r
- STAT_OP => phy_stat_op,\r
- CTRL_OP => phy_ctrl_op,\r
- DEBUG_OUT => phy_debug_i\r
- );\r
-\r
- TEST_LINE <= phy_stat_op;\r
- \r
- SFP_RATESEL <= (others => '1');\r
- \r
- --TEST_LINE(1 downto 0) <= cbm_dlm2send_va & cbm_dlm_rec_va;\r
-\r
--- process is\r
--- variable counter_v : unsigned(20 downto 0); \r
--- begin\r
--- wait until rising_edge(rclk_125_i);\r
--- counter_v := counter_v + to_unsigned(1,1);\r
--- cbm_dlm2send_va <= '0';\r
--- if counter_v = 0 then\r
--- cbm_dlm2send_va <= '1';\r
--- end if;\r
--- end process;\r
--- \r
- \r
--- cbm_data2link <= "00" & x"dead";\r
- THE_CBM_ENDPOINT: lp_top \r
- generic map (\r
- NUM_LANES => 1,\r
- TX_SLAVE => 1\r
- )\r
- port map (\r
- -- Clk & Reset\r
- clk => rclk_125_i,\r
- res_n => cbm_res_n,\r
-\r
- -- Phy\r
- data_from_link => cbm_data_from_link,\r
- data2link => cbm_data2link,\r
- link_activeovr => cbm_debug_overrides_i(0),\r
- link_readyovr => cbm_debug_overrides_i(1),\r
- SERDES_ready => cbm_SERDES_ready,\r
-\r
- -- CBMNet Interface\r
- link_active => cbm_link_active,\r
- ctrl2send_stop => cbm_ctrl2send_stop,\r
- ctrl2send_start => cbm_ctrl2send_start,\r
- ctrl2send_end => cbm_ctrl2send_end,\r
- ctrl2send => cbm_ctrl2send,\r
- \r
- data2send_stop => cbm_data2send_stop,\r
- data2send_start => cbm_data2send_start,\r
- data2send_end => cbm_data2send_end,\r
- data2send => cbm_data2send,\r
- \r
- dlm2send_va => cbm_dlm2send_va,\r
- dlm2send => cbm_dlm2send,\r
- \r
- dlm_rec_type => cbm_dlm_rec_type,\r
- dlm_rec_va => cbm_dlm_rec_va,\r
-\r
- data_rec => cbm_data_rec,\r
- data_rec_start => cbm_data_rec_start,\r
- data_rec_end => cbm_data_rec_end,\r
- data_rec_stop => cbm_data_rec_stop,\r
- \r
- ctrl_rec => cbm_ctrl_rec,\r
- ctrl_rec_start => cbm_ctrl_rec_start,\r
- ctrl_rec_end => cbm_ctrl_rec_end,\r
- ctrl_rec_stop => cbm_ctrl_rec_stop,\r
- \r
- -- diagnostics Lane0\r
- crc_error_cntr_flag_0 => cbm_crc_error_cntr_flag_0, -- out std_logic;\r
- retrans_cntr_flag_0 => cbm_retrans_cntr_flag_0, -- out std_logic;\r
- retrans_error_cntr_flag_0 => cbm_retrans_error_cntr_flag_0, -- out std_logic;\r
- crc_error_cntr_0 => cbm_crc_error_cntr_0, -- out std_logic_vector(15 downto 0);\r
- retrans_cntr_0 => cbm_retrans_cntr_0, -- out std_logic_vector(15 downto 0);\r
- retrans_error_cntr_0 => cbm_retrans_error_cntr_0, -- out std_logic_vector(15 downto 0);\r
- crc_error_cntr_clr_0 => cbm_crc_error_cntr_clr_0, -- in std_logic;\r
- retrans_cntr_clr_0 => cbm_retrans_cntr_clr_0, -- in std_logic;\r
- retrans_error_cntr_clr_0 => cbm_retrans_error_cntr_clr_0, -- in std_logic;\r
-\r
- -- diagnostics Lane1\r
- crc_error_cntr_flag_1 => cbm_crc_error_cntr_flag_1, -- out std_logic;\r
- retrans_cntr_flag_1 => cbm_retrans_cntr_flag_1, -- out std_logic;\r
- retrans_error_cntr_flag_1 => cbm_retrans_error_cntr_flag_1, -- out std_logic;\r
- crc_error_cntr_1 => cbm_crc_error_cntr_1, -- out std_logic_vector(15 downto 0);\r
- retrans_cntr_1 => cbm_retrans_cntr_1, -- out std_logic_vector(15 downto 0);\r
- retrans_error_cntr_1 => cbm_retrans_error_cntr_1, -- out std_logic_vector(15 downto 0);\r
- crc_error_cntr_clr_1 => cbm_crc_error_cntr_clr_1, -- in std_logic; \r
- retrans_cntr_clr_1 => cbm_retrans_cntr_clr_1, -- in std_logic; \r
- retrans_error_cntr_clr_1 => cbm_retrans_error_cntr_clr_1, -- in std_logic; \r
-\r
- -- diagnostics Lane2\r
- crc_error_cntr_flag_2 => cbm_crc_error_cntr_flag_2, -- out std_logic;\r
- retrans_cntr_flag_2 => cbm_retrans_cntr_flag_2, -- out std_logic;\r
- retrans_error_cntr_flag_2 => cbm_retrans_error_cntr_flag_2, -- out std_logic;\r
- crc_error_cntr_2 => cbm_crc_error_cntr_2, -- out std_logic_vector(15 downto 0);\r
- retrans_cntr_2 => cbm_retrans_cntr_2, -- out std_logic_vector(15 downto 0);\r
- retrans_error_cntr_2 => cbm_retrans_error_cntr_2, -- out std_logic_vector(15 downto 0);\r
- crc_error_cntr_clr_2 => cbm_crc_error_cntr_clr_2, -- in std_logic; \r
- retrans_cntr_clr_2 => cbm_retrans_cntr_clr_2, -- in std_logic; \r
- retrans_error_cntr_clr_2 => cbm_retrans_error_cntr_clr_2, -- in std_logic; \r
-\r
- -- diagnostics Lane3\r
- crc_error_cntr_flag_3 => cbm_crc_error_cntr_flag_3, -- out std_logic;\r
- retrans_cntr_flag_3 => cbm_retrans_cntr_flag_3, -- out std_logic;\r
- retrans_error_cntr_flag_3 => cbm_retrans_error_cntr_flag_3, -- out std_logic;\r
- crc_error_cntr_3 => cbm_crc_error_cntr_3, -- out std_logic_vector(15 downto 0);\r
- retrans_cntr_3 => cbm_retrans_cntr_3, -- out std_logic_vector(15 downto 0);\r
- retrans_error_cntr_3 => cbm_retrans_error_cntr_3, -- out std_logic_vector(15 downto 0);\r
- crc_error_cntr_clr_3 => cbm_crc_error_cntr_clr_3, -- in std_logic; \r
- retrans_cntr_clr_3 => cbm_retrans_cntr_clr_3, -- in std_logic; \r
- retrans_error_cntr_clr_3 => cbm_retrans_error_cntr_clr_3 -- in std_logic\r
- \r
- \r
- );\r
- cbm_res_n <= not rreset_i;\r
-\r
- cbm_crc_error_cntr_clr_0 <= reset_i;\r
- cbm_retrans_cntr_clr_0 <= reset_i;\r
- cbm_retrans_error_cntr_clr_0 <= reset_i;\r
- cbm_crc_error_cntr_clr_1 <= reset_i;\r
- cbm_retrans_cntr_clr_1 <= reset_i;\r
- cbm_retrans_error_cntr_clr_1 <= reset_i;\r
- cbm_crc_error_cntr_clr_2 <= reset_i;\r
- cbm_retrans_cntr_clr_2 <= reset_i;\r
- cbm_retrans_error_cntr_clr_2 <= reset_i;\r
- cbm_crc_error_cntr_clr_3 <= reset_i;\r
- cbm_retrans_cntr_clr_3 <= reset_i;\r
- cbm_retrans_error_cntr_clr_3 <= reset_i;\r
- \r
- THE_DLM_REFLECT: dlm_reflect port map (\r
- clk => rclk_125_i, -- in std_logic;\r
- res_n => cbm_res_n, -- in std_logic;\r
- dlm_rec_in => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0);\r
- dlm_rec_va_in => cbm_dlm_rec_va, -- in std_logic;\r
- dlm_rec_out => open, -- out std_logic_vector(3 downto 0);\r
- dlm_rec_va_out => open, -- out std_logic;\r
- dlm2send_va => cbm_dlm2send_va, -- out std_logic;\r
- dlm2send => cbm_dlm2send -- out std_logic_vector(3 downto 0)\r
- );\r
- \r
- \r
- PROC_DATA_SEND: process begin\r
- wait until rising_edge(rclk_125_i);\r
- \r
- cbm_data2send <= (others => '0');\r
- cbm_data2send_start <= "0";\r
- cbm_data2send_end <= "0";\r
-\r
- if reset_i = '1' or send_enabled_i = '0' then\r
- send_fsm_i <= START;\r
- send_num_pack_counter_i <= (others => '0');\r
- \r
- else\r
- case(send_fsm_i) is\r
- when START =>\r
- if cbm_link_active='1' and cbm_data2send_stop = "0" then\r
- send_fsm_i <= SEND_HEADER;\r
- send_num_pack_counter_i <= send_num_pack_counter_i + 1;\r
- send_length_i <= "0" & send_num_pack_counter_i(3 downto 0);\r
- end if;\r
- \r
- when SEND_HEADER =>\r
- cbm_data2send <= x"f123";\r
- cbm_data2send_start <= "1";\r
- send_fsm_i <= SEND_PACK_NUM;\r
- \r
- when SEND_PACK_NUM =>\r
- cbm_data2send <= send_num_pack_counter_i;\r
- send_fsm_i <= SEND_LENGTH;\r
- \r
- when SEND_LENGTH =>\r
- cbm_data2send(send_length_i'range) <= send_length_i;\r
- send_fsm_i <= SEND_DATA;\r
- \r
- when SEND_DATA =>\r
- send_length_i <= send_length_i - 1;\r
- cbm_data2send(15 downto 8) <= "0" & std_logic_vector(send_length_i(2 downto 0)) & std_logic_vector(send_length_i(3 downto 0));\r
- cbm_data2send(send_length_i'high + 0 downto 0) <= send_length_i;\r
- \r
- if send_length_i = TO_UNSIGNED(1, send_length_i'length) then\r
- send_fsm_i <= SEND_FOOTER;\r
- end if;\r
- \r
- when SEND_FOOTER =>\r
- cbm_data2send <= x"f321";\r
- cbm_data2send_end <= "1";\r
- \r
- send_wait_counter_i <= (others => '0');\r
- send_fsm_i <= AFTER_SEND_WAIT;\r
-\r
- when AFTER_SEND_WAIT =>\r
- send_wait_counter_i <= STD_LOGIC_VECTOR( UNSIGNED(send_wait_counter_i) + 1 );\r
- if send_wait_counter_i >= send_wait_threshold_i then\r
- send_fsm_i <= START;\r
- end if;\r
- \r
- when others =>\r
- send_fsm_i <= START;\r
- \r
- end case;\r
- end if;\r
- end process;\r
- \r
- PROC_DLM_COUNTER: process is\r
- variable dlm_type_v : integer range 15 downto 0;\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- \r
- if reset_i = '1' then\r
- dlm_counter_i <= (others => '0');\r
- dlm_glob_counter_i <= (others => '0');\r
- elsif cbm_dlm_rec_va = '1' then\r
- dlm_glob_counter_i <= dlm_glob_counter_i + TO_UNSIGNED(1,1);\r
- \r
- dlm_type_v := to_integer(unsigned(cbm_dlm_rec_type));\r
- for i in 0 to 15 loop\r
- if dlm_type_v = i then\r
- dlm_counter_i(1+i*2 downto i*2) <= dlm_counter_i(1+i*2 downto i*2) + TO_UNSIGNED(1,1);\r
- end if;\r
- end loop;\r
- end if;\r
- end process;\r
- \r
- phy_debug_i_buf <= phy_debug_i when rising_edge(clk_100_i);\r
-\r
-\r
- PROC_REGIO_DEBUG: process is \r
- variable address : integer range 0 to 255;\r
- begin\r
- wait until rising_edge(clk_100_i);\r
- address := to_integer(unsigned(debug_addr));\r
- \r
- debug_data_out <= x"00000000";\r
- \r
- debug_ack <= debug_read_en or debug_write_en;\r
- case address is\r
- when 16#0# => debug_data_out <= x"0000" & phy_stat_op;\r
- when 16#1# => debug_data_out <= x"0000" & phy_ctrl_op;\r
- when 16#2# => debug_data_out <= phy_stat_debug(31 downto 0);\r
- when 16#3# => debug_data_out <= phy_stat_debug(63 downto 32);\r
- when 16#4# => debug_data_out <= phy_ctrl_debug(31 downto 0);\r
- when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32);\r
- when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32));\r
- \r
- when 16#20# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0);\r
- when 16#21# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1);\r
- when 16#22# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2);\r
- when 16#23# => debug_data_out <= phy_debug_i_buf(31+32*3 downto 32*3); \r
- when 16#24# => debug_data_out <= phy_debug_i_buf(31+32*4 downto 32*4);\r
- when 16#25# => debug_data_out <= phy_debug_i_buf(31+32*5 downto 32*5);\r
- when 16#26# => debug_data_out <= phy_debug_i_buf(31+32*6 downto 32*6);\r
- when 16#27# => debug_data_out <= phy_debug_i_buf(31+32*7 downto 32*7); \r
- when 16#28# => debug_data_out <= phy_debug_i_buf(31+32*8 downto 32*8);\r
- when 16#29# => debug_data_out <= phy_debug_i_buf(31+32*9 downto 32*9);\r
- when 16#2a# => debug_data_out <= phy_debug_i_buf(31+32*10 downto 32*10);\r
- when 16#2b# => debug_data_out <= phy_debug_i_buf(31+32*11 downto 32*11); \r
- when 16#2c# => debug_data_out <= phy_debug_i_buf(31+32*12 downto 32*12);\r
- when 16#2d# => debug_data_out <= phy_debug_i_buf(31+32*13 downto 32*13);\r
- when 16#2e# => debug_data_out <= phy_debug_i_buf(31+32*14 downto 32*14);\r
- when 16#2f# => debug_data_out <= phy_debug_i_buf(31+32*15 downto 32*15); \r
- \r
- \r
- when 16#10# => debug_data_out <= send_wait_threshold_i;\r
- when 16#11# => debug_data_out(20 downto 0) <= cbm_res_n & "00" & cbm_data_from_link;\r
- \r
- when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i);\r
- when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i);\r
- when 16#14# =>\r
- debug_data_out(21 downto 20) <= cbm_debug_overrides_i;\r
- debug_data_out(19 downto 16) <= "0" & send_enabled_i & cbm_data2send_stop & cbm_link_active;\r
- debug_data_out(15 downto 0) <= STD_LOGIC_VECTOR(send_num_pack_counter_i);\r
- \r
- \r
- when 16#15# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_0;\r
- when 16#16# => debug_data_out <= cbm_retrans_error_cntr_0 & cbm_retrans_cntr_0;\r
- when 16#17# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_1;\r
- when 16#18# => debug_data_out <= cbm_retrans_error_cntr_1 & cbm_retrans_cntr_1;\r
- when 16#19# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_2;\r
- when 16#1a# => debug_data_out <= cbm_retrans_error_cntr_2 & cbm_retrans_cntr_2;\r
- when 16#1b# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_3;\r
- when 16#1c# => debug_data_out <= cbm_retrans_error_cntr_3 & cbm_retrans_cntr_3;\r
- \r
- when others => debug_ack <= '0';\r
- end case;\r
- \r
- if debug_write_en = '1' then\r
- case (address) is\r
- when 16#1# => phy_ctrl_op <= debug_data_in(15 downto 0);\r
- when 16#4# => phy_ctrl_debug(31 downto 0) <= debug_data_in;\r
- when 16#5# => phy_ctrl_debug(63 downto 32) <= debug_data_in;\r
- when 16#10# => send_wait_threshold_i <= debug_data_in;\r
- when 16#14# => \r
- send_enabled_i <= debug_data_in(18);\r
- cbm_debug_overrides_i <= debug_data_in(21 downto 20);\r
- \r
-\r
- when others => debug_ack <= '0';\r
- end case;\r
- end if;\r
- end process;\r
- \r
- \r
- \r
- \r
----------------------------------------------------------------------------\r
--- Reset Generation\r
----------------------------------------------------------------------------\r
- GSR_N <= pll_lock;\r
-\r
- THE_RESET_HANDLER : trb_net_reset_handler\r
- generic map(\r
- RESET_DELAY => x"FEEE"\r
- )\r
- port map(\r
- CLEAR_IN => '0', -- reset input (high active, async)\r
- CLEAR_N_IN => '1', -- reset input (low active, async)\r
- CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!\r
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock\r
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)\r
- RESET_IN => '0', -- general reset signal (SYSCLK)\r
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)\r
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!\r
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)\r
- DEBUG_OUT => open\r
- ); \r
-\r
-\r
----------------------------------------------------------------------------\r
--- Clock Handling\r
----------------------------------------------------------------------------\r
-\r
- THE_MAIN_PLL : pll_in200_out100\r
- port map(\r
- CLK => CLK_GPLL_RIGHT,\r
- CLKOP => clk_100_i,\r
- CLKOK => clk_200_i,\r
- CLKOS => open,\r
- LOCK => pll_lock1\r
- );\r
- \r
- pll_lock <= pll_lock1; -- and pll_lock2;\r
-\r
--- GEN_TRBNET: if INCLUDE_TRBNET = c_YES generate\r
----------------------------------------------------------------------------\r
--- The TrbNet media interface (to other FPGA)\r
----------------------------------------------------------------------------\r
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp\r
- generic map(\r
- SERDES_NUM => 1, --number of serdes in quad\r
- EXT_CLOCK => c_NO, --use internal clock\r
- USE_200_MHZ => c_YES, --run on 200 MHz clock\r
- USE_125_MHZ => c_NO,\r
- USE_CTC => c_NO\r
- )\r
- port map(\r
- CLK => clk_200_i,\r
- SYSCLK => clk_100_i,\r
- RESET => reset_i,\r
- CLEAR => clear_i,\r
- CLK_EN => '1',\r
- --Internal Connection\r
- MED_DATA_IN => med_data_out,\r
- MED_PACKET_NUM_IN => med_packet_num_out,\r
- MED_DATAREADY_IN => med_dataready_out,\r
- MED_READ_OUT => med_read_in,\r
- MED_DATA_OUT => med_data_in,\r
- MED_PACKET_NUM_OUT => med_packet_num_in,\r
- MED_DATAREADY_OUT => med_dataready_in,\r
- MED_READ_IN => med_read_out,\r
- REFCLK2CORE_OUT => open,\r
- --SFP Connection\r
- SD_RXD_P_IN => SERDES_INT_RX(2),\r
- SD_RXD_N_IN => SERDES_INT_RX(3),\r
- SD_TXD_P_OUT => SERDES_INT_TX(2),\r
- SD_TXD_N_OUT => SERDES_INT_TX(3),\r
- SD_REFCLK_P_IN => open,\r
- SD_REFCLK_N_IN => open,\r
- SD_PRSNT_N_IN => FPGA5_COMM(0),\r
- SD_LOS_IN => FPGA5_COMM(0),\r
- SD_TXDIS_OUT => FPGA5_COMM(2),\r
- -- Status and control port\r
- STAT_OP => med_stat_op,\r
- CTRL_OP => med_ctrl_op,\r
- STAT_DEBUG => med_stat_debug,\r
- CTRL_DEBUG => (others => '0'),\r
- \r
- sci_ack => open,\r
- clk_rx_full_out => open,\r
- clk_rx_half_out => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- Endpoint\r
----------------------------------------------------------------------------\r
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler\r
- generic map(\r
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg\r
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg\r
- ADDRESS_MASK => x"FFFF",\r
- BROADCAST_BITMASK => x"FF",\r
- BROADCAST_SPECIAL_ADDR => x"45",\r
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),\r
- REGIO_HARDWARE_VERSION => x"91000001",\r
- REGIO_INIT_ADDRESS => x"f301",\r
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,\r
- CLOCK_FREQUENCY => 100,\r
- TIMING_TRIGGER_RAW => c_YES,\r
- --Configure data handler\r
- DATA_INTERFACE_NUMBER => 1,\r
- DATA_BUFFER_DEPTH => 13, --13\r
- DATA_BUFFER_WIDTH => 32,\r
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024\r
- TRG_RELEASE_AFTER_DATA => c_YES,\r
- HEADER_BUFFER_DEPTH => 9,\r
- HEADER_BUFFER_FULL_THRESH => 2**9-16\r
- )\r
- port map(\r
- CLK => clk_100_i,\r
- RESET => reset_i,\r
- CLK_EN => '1',\r
- MED_DATAREADY_OUT => med_dataready_out, -- open, --\r
- MED_DATA_OUT => med_data_out, -- open, --\r
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --\r
- MED_READ_IN => med_read_in,\r
- MED_DATAREADY_IN => med_dataready_in,\r
- MED_DATA_IN => med_data_in,\r
- MED_PACKET_NUM_IN => med_packet_num_in,\r
- MED_READ_OUT => med_read_out, -- open, --\r
- MED_STAT_OP_IN => med_stat_op,\r
- MED_CTRL_OP_OUT => med_ctrl_op,\r
-\r
- --Timing trigger in\r
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,\r
- --LVL1 trigger to FEE\r
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,\r
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,\r
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,\r
- LVL1_INVALID_TRG_OUT => trg_invalid_i,\r
-\r
- LVL1_TRG_TYPE_OUT => trg_type_i,\r
- LVL1_TRG_NUMBER_OUT => trg_number_i,\r
- LVL1_TRG_CODE_OUT => trg_code_i,\r
- LVL1_TRG_INFORMATION_OUT => trg_information_i,\r
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,\r
-\r
- --Information about trigger handler errors\r
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,\r
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,\r
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,\r
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,\r
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,\r
- \r
- --Response from FEE\r
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,\r
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,\r
- FEE_DATA_IN => fee_data_i,\r
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,\r
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,\r
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,\r
-\r
- -- Slow Control Data Port\r
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,\r
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,\r
- REGIO_STAT_REG_IN => stat_reg, --start 0x80\r
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0\r
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,\r
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,\r
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,\r
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),\r
-\r
- BUS_ADDR_OUT => regio_addr_out,\r
- BUS_READ_ENABLE_OUT => regio_read_enable_out,\r
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,\r
- BUS_DATA_OUT => regio_data_out,\r
- BUS_DATA_IN => regio_data_in,\r
- BUS_DATAREADY_IN => regio_dataready_in,\r
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,\r
- BUS_WRITE_ACK_IN => regio_write_ack_in,\r
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
- BUS_TIMEOUT_OUT => regio_timeout_out,\r
- ONEWIRE_INOUT => TEMPSENS,\r
- ONEWIRE_MONITOR_OUT => open,\r
-\r
- TIME_GLOBAL_OUT => global_time,\r
- TIME_LOCAL_OUT => local_time,\r
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,\r
- TIME_TICKS_OUT => timer_ticks,\r
-\r
- STAT_DEBUG_IPU => open,\r
- STAT_DEBUG_1 => open,\r
- STAT_DEBUG_2 => open,\r
- STAT_DEBUG_DATA_HANDLER_OUT => open,\r
- STAT_DEBUG_IPU_HANDLER_OUT => open,\r
- STAT_TRIGGER_OUT => open,\r
- CTRL_MPLEX => (others => '0'),\r
- IOBUF_CTRL_GEN => (others => '0'),\r
- STAT_ONEWIRE => open,\r
- STAT_ADDR_DEBUG => open,\r
- DEBUG_LVL1_HANDLER_OUT => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- Bus Handler\r
----------------------------------------------------------------------------\r
- THE_BUS_HANDLER : trb_net16_regio_bus_handler\r
- generic map(\r
- PORT_NUMBER => 3,\r
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", others => x"0000"),\r
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, others => 0)\r
- )\r
- port map(\r
- CLK => clk_100_i,\r
- RESET => reset_i,\r
-\r
- DAT_ADDR_IN => regio_addr_out,\r
- DAT_DATA_IN => regio_data_out,\r
- DAT_DATA_OUT => regio_data_in,\r
- DAT_READ_ENABLE_IN => regio_read_enable_out,\r
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,\r
- DAT_TIMEOUT_IN => regio_timeout_out,\r
- DAT_DATAREADY_OUT => regio_dataready_in,\r
- DAT_WRITE_ACK_OUT => regio_write_ack_in,\r
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,\r
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,\r
-\r
- --Bus Handler (SPI CTRL)\r
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,\r
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,\r
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,\r
- BUS_ADDR_OUT(0*16) => spictrl_addr,\r
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,\r
- BUS_TIMEOUT_OUT(0) => open,\r
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,\r
- BUS_DATAREADY_IN(0) => spictrl_ack,\r
- BUS_WRITE_ACK_IN(0) => spictrl_ack,\r
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,\r
- BUS_UNKNOWN_ADDR_IN(0) => '0',\r
- \r
- --Bus Handler (SPI Memory)\r
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,\r
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,\r
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,\r
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,\r
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,\r
- BUS_TIMEOUT_OUT(1) => open,\r
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,\r
- BUS_DATAREADY_IN(1) => spimem_ack,\r
- BUS_WRITE_ACK_IN(1) => spimem_ack,\r
- BUS_NO_MORE_DATA_IN(1) => '0',\r
- BUS_UNKNOWN_ADDR_IN(1) => '0',\r
-\r
- --Bus Handler (SPI CTRL)\r
- BUS_READ_ENABLE_OUT(2) => debug_read_en,\r
- BUS_WRITE_ENABLE_OUT(2) => debug_write_en,\r
- BUS_DATA_OUT(2*32+31 downto 2*32) => debug_data_in,\r
- BUS_ADDR_OUT(2*16+5 downto 2*16) => debug_addr,\r
- BUS_ADDR_OUT(2*16+15 downto 2*16+6) => open,\r
- BUS_TIMEOUT_OUT(2) => open,\r
- BUS_DATA_IN(2*32+31 downto 2*32) => debug_data_out,\r
- BUS_DATAREADY_IN(2) => debug_ack,\r
- BUS_WRITE_ACK_IN(2) => debug_ack,\r
- BUS_NO_MORE_DATA_IN(2) => '0',\r
- BUS_UNKNOWN_ADDR_IN(2) => '0',\r
- \r
- \r
- STAT_DEBUG => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- SPI / Flash\r
----------------------------------------------------------------------------\r
-\r
- THE_SPI_MASTER : spi_master\r
- port map(\r
- CLK_IN => clk_100_i,\r
- RESET_IN => reset_i,\r
- -- Slave bus\r
- BUS_READ_IN => spictrl_read_en,\r
- BUS_WRITE_IN => spictrl_write_en,\r
- BUS_BUSY_OUT => spictrl_busy,\r
- BUS_ACK_OUT => spictrl_ack,\r
- BUS_ADDR_IN(0) => spictrl_addr,\r
- BUS_DATA_IN => spictrl_data_in,\r
- BUS_DATA_OUT => spictrl_data_out,\r
- -- SPI connections\r
- SPI_CS_OUT => FLASH_CS,\r
- SPI_SDI_IN => FLASH_DOUT,\r
- SPI_SDO_OUT => FLASH_DIN,\r
- SPI_SCK_OUT => FLASH_CLK,\r
- -- BRAM for read/write data\r
- BRAM_A_OUT => spi_bram_addr,\r
- BRAM_WR_D_IN => spi_bram_wr_d,\r
- BRAM_RD_D_OUT => spi_bram_rd_d,\r
- BRAM_WE_OUT => spi_bram_we,\r
- -- Status lines\r
- STAT => open\r
- );\r
-\r
--- data memory for SPI accesses\r
- THE_SPI_MEMORY : spi_databus_memory\r
- port map(\r
- CLK_IN => clk_100_i,\r
- RESET_IN => reset_i,\r
- -- Slave bus\r
- BUS_ADDR_IN => spimem_addr,\r
- BUS_READ_IN => spimem_read_en,\r
- BUS_WRITE_IN => spimem_write_en,\r
- BUS_ACK_OUT => spimem_ack,\r
- BUS_DATA_IN => spimem_data_in,\r
- BUS_DATA_OUT => spimem_data_out,\r
- -- state machine connections\r
- BRAM_ADDR_IN => spi_bram_addr,\r
- BRAM_WR_D_OUT => spi_bram_wr_d,\r
- BRAM_RD_D_IN => spi_bram_rd_d,\r
- BRAM_WE_IN => spi_bram_we,\r
- -- Status lines\r
- STAT => open\r
- );\r
-\r
----------------------------------------------------------------------------\r
--- Reboot FPGA\r
----------------------------------------------------------------------------\r
- THE_FPGA_REBOOT : fpga_reboot\r
- port map(\r
- CLK => clk_100_i,\r
- RESET => reset_i,\r
- DO_REBOOT => common_ctrl_reg(15),\r
- PROGRAMN => PROGRAMN\r
- );\r
-\r
-\r
-\r
----------------------------------------------------------------------------\r
--- LED\r
----------------------------------------------------------------------------\r
- LED_GREEN <= not med_stat_op(9);\r
- LED_ORANGE <= not med_stat_op(10);\r
- LED_RED <= not time_counter(26);\r
- LED_YELLOW <= not med_stat_op(11);\r
-\r
--- end generate;\r
-\r
-\r
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+use work.cbmnet_interface_pkg.all;
+use work.cbmnet_phy_pkg.all;
+
+
+entity trb3_periph_cbmnet is
+ generic (
+ CBM_FEE_MODE : integer := CBM_FEE_MODE_C; -- in FEE mode, logic will run on recovered clock and (for now) listen only to data received
+ -- in Master mode, logic will run on internal clock and regularly send dlms
+ INCLUDE_TRBNET : integer := INCLUDE_TRBNET_C
+ );
+ port(
+ --Clocks
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+
+ --Serdes
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+ SERDES_INT_TX : out std_logic_vector(3 downto 0);
+ SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
+
+ --Inter-FPGA Communication
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+ SFP_MOD1 : out std_logic_vector(6 downto 1);
+ SFP_MOD2 : inout std_logic_vector(6 downto 1);
+
+ SFP_RATESEL: out std_logic_vector(6 downto 1);
+ SFP_TXFAULT: in std_logic_vector(6 downto 1);
+
+ --Flash ROM & Reboot
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
+ --Misc
+ TEMPSENS : inout std_logic; --Temperature Sensor
+ CODE_LINE : in std_logic_vector(1 downto 0);
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0);
+ --TEST_LVDS_LINE : out std_logic_vector(1 downto 0);
+
+ -- PCS Core TODO: Suppose this is necessary only for simulation
+ SD_RXD_N_IN : in std_logic;
+ SD_RXD_P_IN : in std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_TXD_P_OUT : out std_logic
+ );
+
+ attribute syn_useioff : boolean;
+ --no IO-FF for LEDs relaxes timing constraints
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+
+ --important signals _with_ IO-FF
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_DIN : signal is true;
+ attribute syn_useioff of FLASH_DOUT : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is true;
+
+ attribute nopad : string;
+ attribute nopad of SD_RXD_N_IN, SD_RXD_P_IN, SD_TXD_N_OUT, SD_TXD_P_OUT : signal is "true";
+
+ attribute syn_keep : boolean;
+ attribute syn_keep of CLK_GPLL_LEFT, CLK_GPLL_RIGHT, CLK_PCLK_LEFT, CLK_PCLK_RIGHT, TRIGGER_LEFT, TRIGGER_RIGHT : signal is true;
+ attribute syn_preserve : boolean;
+
+end entity;
+
+architecture trb3_periph_arch of trb3_periph_cbmnet is
+--Constants
+ constant REGIO_NUM_STAT_REGS : integer := 2;
+ constant REGIO_NUM_CTRL_REGS : integer := 2;
+
+
+ --Clock / Reset
+ signal clk_125_i : std_logic; -- clock reference for CBMNet serdes
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal pll_lock1, pll_lock2 : std_logic;
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+
+
+ signal rclk_125_i : std_logic; -- recovered clock
+ signal rreset_i : std_logic; -- reset for recovered clock ~ 1us after clock becomes stable
+
+
+ --Media Interface
+ signal med_stat_op : std_logic_vector (1*16-1 downto 0) := (others => '0');
+ signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
+ signal med_data_out : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_out : std_logic;
+ signal med_read_out : std_logic;
+ signal med_data_in : std_logic_vector (1*16-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
+ signal med_dataready_in : std_logic;
+ signal med_read_in : std_logic;
+
+ --LVL1 channel
+ signal timing_trg_received_i : std_logic;
+ signal trg_data_valid_i : std_logic;
+ signal trg_timing_valid_i : std_logic;
+ signal trg_notiming_valid_i : std_logic;
+ signal trg_invalid_i : std_logic;
+ signal trg_type_i : std_logic_vector(3 downto 0);
+ signal trg_number_i : std_logic_vector(15 downto 0);
+ signal trg_code_i : std_logic_vector(7 downto 0);
+ signal trg_information_i : std_logic_vector(23 downto 0);
+ signal trg_int_number_i : std_logic_vector(15 downto 0);
+ signal trg_multiple_trg_i : std_logic;
+ signal trg_timeout_detected_i: std_logic;
+ signal trg_spurious_trg_i : std_logic;
+ signal trg_missing_tmg_trg_i : std_logic;
+ signal trg_spike_detected_i : std_logic;
+
+ --Data channel
+ signal fee_trg_release_i : std_logic;
+ signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+ signal fee_data_i : std_logic_vector(31 downto 0);
+ signal fee_data_write_i : std_logic;
+ signal fee_data_finished_i : std_logic;
+ signal fee_almost_full_i : std_logic;
+
+ --Slow Control channel
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+ --RegIO
+ signal my_address : std_logic_vector (15 downto 0);
+ signal regio_addr_out : std_logic_vector (15 downto 0);
+ signal regio_read_enable_out : std_logic;
+ signal regio_write_enable_out : std_logic;
+ signal regio_data_out : std_logic_vector (31 downto 0);
+ signal regio_data_in : std_logic_vector (31 downto 0);
+ signal regio_dataready_in : std_logic;
+ signal regio_no_more_data_in : std_logic;
+ signal regio_write_ack_in : std_logic;
+ signal regio_unknown_addr_in : std_logic;
+ signal regio_timeout_out : std_logic;
+
+ --Timer
+ signal global_time : std_logic_vector(31 downto 0);
+ signal local_time : std_logic_vector(7 downto 0);
+ signal time_since_last_trg : std_logic_vector(31 downto 0);
+ signal timer_ticks : std_logic_vector(1 downto 0);
+
+ --Flash
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal debug_read_en : std_logic;
+ signal debug_write_en : std_logic;
+ signal debug_data_in : std_logic_vector(31 downto 0);
+ signal debug_addr : std_logic_vector(5 downto 0);
+ signal debug_data_out : std_logic_vector(31 downto 0);
+ signal debug_ack : std_logic;
+
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ --FPGA Test
+ signal time_counter : unsigned(31 downto 0);
+
+ -- CBMNet signals
+ constant NUM_LANES : integer := 1;
+ signal cbm_res_n : std_logic; -- Active low reset; can be changed by define
+ signal cbm_link_active : std_logic; -- link is active and can send and receive data
+
+ signal cbm_ctrl2send_stop : std_logic := '0'; -- send control interface
+ signal cbm_ctrl2send_start : std_logic := '0';
+ signal cbm_ctrl2send_end : std_logic := '0';
+ signal cbm_ctrl2send : std_logic_vector(15 downto 0) := (others => '0');
+
+ signal cbm_data2send_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0'); -- send data interface
+ signal cbm_data2send_start : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+ signal cbm_data2send_end : std_logic_vector(NUM_LANES-1 downto 0) := (others => '0');
+ signal cbm_data2send : std_logic_vector((16*NUM_LANES)-1 downto 0) := (others => '0');
+
+ signal cbm_dlm2send_va : std_logic := '0'; -- send dlm interface
+ signal cbm_dlm2send : std_logic_vector(3 downto 0) := (others => '0');
+
+ signal cbm_dlm_rec_type : std_logic_vector(3 downto 0) := (others => '0'); -- receive dlm interface
+ signal cbm_dlm_rec_va : std_logic := '0';
+
+ signal cbm_data_rec : std_logic_vector((16*NUM_LANES)-1 downto 0); -- receive data interface
+ signal cbm_data_rec_start : std_logic_vector(NUM_LANES-1 downto 0);
+ signal cbm_data_rec_end : std_logic_vector(NUM_LANES-1 downto 0);
+ signal cbm_data_rec_stop : std_logic_vector(NUM_LANES-1 downto 0) := (others =>'0');
+
+ signal cbm_ctrl_rec : std_logic_vector(15 downto 0); -- receive control interface
+ signal cbm_ctrl_rec_start : std_logic;
+ signal cbm_ctrl_rec_end : std_logic;
+ signal cbm_ctrl_rec_stop : std_logic;
+
+ signal cbm_data_from_link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface from the PHY
+ signal cbm_data2link : std_logic_vector((18*NUM_LANES)-1 downto 0); -- interface to the PHY
+
+ signal cbm_link_activeovr : std_logic := '0'; -- Overrides; set 0 by default
+ signal cbm_link_readyovr : std_logic := '0';
+
+ signal cbm_SERDES_ready : std_logic; -- signalize when PHY ready
+
+ signal phy_stat_op, phy_ctrl_op : std_logic_vector(15 downto 0) := (others => '0');
+ signal phy_stat_debug, phy_ctrl_debug : std_logic_vector(63 downto 0) := (others => '0');
+
+ signal phy_debug_i : std_logic_vector (511 downto 0) := (others => '0');
+ signal phy_debug_i_buf : std_logic_vector (511 downto 0);
+
+
+-- Link Tester
+ signal link_tester_ctrl_en :std_logic;
+ signal link_tester_dlm_en :std_logic;
+ signal link_tester_data_en :std_logic;
+
+ signal link_tester_data_stop :std_logic;
+ signal link_tester_ctrl_stop :std_logic;
+
+ signal link_tester_data_valid:std_logic;
+ signal link_tester_ctrl_valid:std_logic;
+ signal link_tester_dlm_valid :std_logic;
+
+
+ signal link_tester_ctrl : std_logic_vector(31 downto 0) := (others => '0');
+ signal link_tester_stat : std_logic_vector(31 downto 0) := (others => '0');
+
+ signal dummy : std_logic;
+
+ type SEND_FSM_T is (START, SEND_HEADER, SEND_PACK_NUM, SEND_LENGTH, SEND_DATA, SEND_FOOTER, AFTER_SEND_WAIT);
+ signal send_fsm_i : SEND_FSM_T;
+ signal send_length_i : unsigned(4 downto 0);
+ signal send_num_pack_counter_i : unsigned(15 downto 0);
+ signal send_enabled_i : std_logic := '0';
+
+ signal send_wait_counter_i : std_logic_vector(31 downto 0);
+ signal send_wait_threshold_i : std_logic_vector(31 downto 0);
+
+ signal dlm_counter_i : unsigned(31 downto 0);
+ signal dlm_glob_counter_i : unsigned(31 downto 0);
+
+
+ -- diagnostics Lane0
+ signal cbm_crc_error_cntr_flag_0 : std_logic;
+ signal cbm_retrans_cntr_flag_0 : std_logic;
+ signal cbm_retrans_error_cntr_flag_0 : std_logic;
+ signal cbm_crc_error_cntr_0 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_cntr_0 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_error_cntr_0 : std_logic_vector(15 downto 0);
+ signal cbm_crc_error_cntr_clr_0 : std_logic;
+ signal cbm_retrans_cntr_clr_0 : std_logic;
+ signal cbm_retrans_error_cntr_clr_0 : std_logic;
+
+ -- diagnostics Lane1
+ signal cbm_crc_error_cntr_flag_1 : std_logic;
+ signal cbm_retrans_cntr_flag_1 : std_logic;
+ signal cbm_retrans_error_cntr_flag_1 : std_logic;
+ signal cbm_crc_error_cntr_1 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_cntr_1 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_error_cntr_1 : std_logic_vector(15 downto 0);
+ signal cbm_crc_error_cntr_clr_1 : std_logic;
+ signal cbm_retrans_cntr_clr_1 : std_logic;
+ signal cbm_retrans_error_cntr_clr_1 : std_logic;
+
+ -- diagnostics Lane2
+ signal cbm_crc_error_cntr_flag_2 : std_logic;
+ signal cbm_retrans_cntr_flag_2 : std_logic;
+ signal cbm_retrans_error_cntr_flag_2 : std_logic;
+ signal cbm_crc_error_cntr_2 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_cntr_2 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_error_cntr_2 : std_logic_vector(15 downto 0);
+ signal cbm_crc_error_cntr_clr_2 : std_logic;
+ signal cbm_retrans_cntr_clr_2 : std_logic;
+ signal cbm_retrans_error_cntr_clr_2 : std_logic;
+
+ -- diagnostics Lane3
+ signal cbm_crc_error_cntr_flag_3 : std_logic;
+ signal cbm_retrans_cntr_flag_3 : std_logic;
+ signal cbm_retrans_error_cntr_flag_3 : std_logic;
+ signal cbm_crc_error_cntr_3 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_cntr_3 : std_logic_vector(15 downto 0);
+ signal cbm_retrans_error_cntr_3 : std_logic_vector(15 downto 0);
+ signal cbm_crc_error_cntr_clr_3 : std_logic;
+ signal cbm_retrans_cntr_clr_3 : std_logic;
+ signal cbm_retrans_error_cntr_clr_3 : std_logic;
+
+ signal cbm_debug_overrides_i : std_logic_vector(1 downto 0) := "00";
+
+begin
+ clk_125_i <= CLK_GPLL_LEFT;
+
+ assert(INCLUDE_TRBNET = c_YES);
+
+---------------------------------------------------------------------------
+-- CBMNet and PHY
+---------------------------------------------------------------------------
+ THE_CBM_PHY: cbmnet_phy_ecp3
+ generic map (IS_SYNC_SLAVE => CBM_FEE_MODE)
+ port map (
+ CLK => clk_125_i,
+ RESET => reset_i,
+ CLEAR => '0',
+
+ --Internal Connection TX
+ PHY_TXDATA_IN => cbm_data2link(15 downto 0),
+ PHY_TXDATA_K_IN => cbm_data2link(17 downto 16),
+
+ --Internal Connection RX
+ PHY_RXDATA_OUT => cbm_data_from_link(15 downto 0),
+ PHY_RXDATA_K_OUT => cbm_data_from_link(17 downto 16),
+
+ CLK_RX_HALF_OUT => rclk_125_i,
+ CLK_RX_FULL_OUT => open,
+ CLK_RX_RESET_OUT => rreset_i,
+
+ LINK_ACTIVE_OUT => open,
+ SERDES_ready => cbm_SERDES_ready,
+
+ --SFP Connection
+ SD_RXD_P_IN => SD_RXD_P_IN,
+ SD_RXD_N_IN => SD_RXD_N_IN,
+ SD_TXD_P_OUT => SD_TXD_P_OUT,
+ SD_TXD_N_OUT => SD_TXD_N_OUT,
+
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TXDIS(1),
+
+ LED_RX_OUT => LED_RX(1),
+ LED_TX_OUT => LED_TX(1),
+ LED_OK_OUT => LED_LINKOK(1),
+
+ -- Status and control port
+ STAT_OP => phy_stat_op,
+ CTRL_OP => phy_ctrl_op,
+ DEBUG_OUT => phy_debug_i
+ );
+
+ TEST_LINE <= phy_stat_op;
+
+ SFP_RATESEL <= (others => '1');
+
+ --TEST_LINE(1 downto 0) <= cbm_dlm2send_va & cbm_dlm_rec_va;
+
+-- process is
+-- variable counter_v : unsigned(20 downto 0);
+-- begin
+-- wait until rising_edge(rclk_125_i);
+-- counter_v := counter_v + to_unsigned(1,1);
+-- cbm_dlm2send_va <= '0';
+-- if counter_v = 0 then
+-- cbm_dlm2send_va <= '1';
+-- end if;
+-- end process;
+--
+
+-- cbm_data2link <= "00" & x"dead";
+ THE_CBM_ENDPOINT: lp_top
+ generic map (
+ NUM_LANES => 1,
+ TX_SLAVE => 1
+ )
+ port map (
+ -- Clk & Reset
+ clk => rclk_125_i,
+ res_n => cbm_res_n,
+
+ -- Phy
+ data_from_link => cbm_data_from_link,
+ data2link => cbm_data2link,
+ link_activeovr => cbm_debug_overrides_i(0),
+ link_readyovr => cbm_debug_overrides_i(1),
+ SERDES_ready => cbm_SERDES_ready,
+
+ -- CBMNet Interface
+ link_active => cbm_link_active,
+ ctrl2send_stop => cbm_ctrl2send_stop,
+ ctrl2send_start => cbm_ctrl2send_start,
+ ctrl2send_end => cbm_ctrl2send_end,
+ ctrl2send => cbm_ctrl2send,
+
+ data2send_stop => cbm_data2send_stop,
+ data2send_start => cbm_data2send_start,
+ data2send_end => cbm_data2send_end,
+ data2send => cbm_data2send,
+
+ dlm2send_va => cbm_dlm2send_va,
+ dlm2send => cbm_dlm2send,
+
+ dlm_rec_type => cbm_dlm_rec_type,
+ dlm_rec_va => cbm_dlm_rec_va,
+
+ data_rec => cbm_data_rec,
+ data_rec_start => cbm_data_rec_start,
+ data_rec_end => cbm_data_rec_end,
+ data_rec_stop => cbm_data_rec_stop,
+
+ ctrl_rec => cbm_ctrl_rec,
+ ctrl_rec_start => cbm_ctrl_rec_start,
+ ctrl_rec_end => cbm_ctrl_rec_end,
+ ctrl_rec_stop => cbm_ctrl_rec_stop,
+
+ -- diagnostics Lane0
+ crc_error_cntr_flag_0 => cbm_crc_error_cntr_flag_0, -- out std_logic;
+ retrans_cntr_flag_0 => cbm_retrans_cntr_flag_0, -- out std_logic;
+ retrans_error_cntr_flag_0 => cbm_retrans_error_cntr_flag_0, -- out std_logic;
+ crc_error_cntr_0 => cbm_crc_error_cntr_0, -- out std_logic_vector(15 downto 0);
+ retrans_cntr_0 => cbm_retrans_cntr_0, -- out std_logic_vector(15 downto 0);
+ retrans_error_cntr_0 => cbm_retrans_error_cntr_0, -- out std_logic_vector(15 downto 0);
+ crc_error_cntr_clr_0 => cbm_crc_error_cntr_clr_0, -- in std_logic;
+ retrans_cntr_clr_0 => cbm_retrans_cntr_clr_0, -- in std_logic;
+ retrans_error_cntr_clr_0 => cbm_retrans_error_cntr_clr_0, -- in std_logic;
+
+ -- diagnostics Lane1
+ crc_error_cntr_flag_1 => cbm_crc_error_cntr_flag_1, -- out std_logic;
+ retrans_cntr_flag_1 => cbm_retrans_cntr_flag_1, -- out std_logic;
+ retrans_error_cntr_flag_1 => cbm_retrans_error_cntr_flag_1, -- out std_logic;
+ crc_error_cntr_1 => cbm_crc_error_cntr_1, -- out std_logic_vector(15 downto 0);
+ retrans_cntr_1 => cbm_retrans_cntr_1, -- out std_logic_vector(15 downto 0);
+ retrans_error_cntr_1 => cbm_retrans_error_cntr_1, -- out std_logic_vector(15 downto 0);
+ crc_error_cntr_clr_1 => cbm_crc_error_cntr_clr_1, -- in std_logic;
+ retrans_cntr_clr_1 => cbm_retrans_cntr_clr_1, -- in std_logic;
+ retrans_error_cntr_clr_1 => cbm_retrans_error_cntr_clr_1, -- in std_logic;
+
+ -- diagnostics Lane2
+ crc_error_cntr_flag_2 => cbm_crc_error_cntr_flag_2, -- out std_logic;
+ retrans_cntr_flag_2 => cbm_retrans_cntr_flag_2, -- out std_logic;
+ retrans_error_cntr_flag_2 => cbm_retrans_error_cntr_flag_2, -- out std_logic;
+ crc_error_cntr_2 => cbm_crc_error_cntr_2, -- out std_logic_vector(15 downto 0);
+ retrans_cntr_2 => cbm_retrans_cntr_2, -- out std_logic_vector(15 downto 0);
+ retrans_error_cntr_2 => cbm_retrans_error_cntr_2, -- out std_logic_vector(15 downto 0);
+ crc_error_cntr_clr_2 => cbm_crc_error_cntr_clr_2, -- in std_logic;
+ retrans_cntr_clr_2 => cbm_retrans_cntr_clr_2, -- in std_logic;
+ retrans_error_cntr_clr_2 => cbm_retrans_error_cntr_clr_2, -- in std_logic;
+
+ -- diagnostics Lane3
+ crc_error_cntr_flag_3 => cbm_crc_error_cntr_flag_3, -- out std_logic;
+ retrans_cntr_flag_3 => cbm_retrans_cntr_flag_3, -- out std_logic;
+ retrans_error_cntr_flag_3 => cbm_retrans_error_cntr_flag_3, -- out std_logic;
+ crc_error_cntr_3 => cbm_crc_error_cntr_3, -- out std_logic_vector(15 downto 0);
+ retrans_cntr_3 => cbm_retrans_cntr_3, -- out std_logic_vector(15 downto 0);
+ retrans_error_cntr_3 => cbm_retrans_error_cntr_3, -- out std_logic_vector(15 downto 0);
+ crc_error_cntr_clr_3 => cbm_crc_error_cntr_clr_3, -- in std_logic;
+ retrans_cntr_clr_3 => cbm_retrans_cntr_clr_3, -- in std_logic;
+ retrans_error_cntr_clr_3 => cbm_retrans_error_cntr_clr_3 -- in std_logic
+
+
+ );
+ cbm_res_n <= not rreset_i when rising_edge(rclk_125_i);
+
+ cbm_crc_error_cntr_clr_0 <= reset_i;
+ cbm_retrans_cntr_clr_0 <= reset_i;
+ cbm_retrans_error_cntr_clr_0 <= reset_i;
+ cbm_crc_error_cntr_clr_1 <= reset_i;
+ cbm_retrans_cntr_clr_1 <= reset_i;
+ cbm_retrans_error_cntr_clr_1 <= reset_i;
+ cbm_crc_error_cntr_clr_2 <= reset_i;
+ cbm_retrans_cntr_clr_2 <= reset_i;
+ cbm_retrans_error_cntr_clr_2 <= reset_i;
+ cbm_crc_error_cntr_clr_3 <= reset_i;
+ cbm_retrans_cntr_clr_3 <= reset_i;
+ cbm_retrans_error_cntr_clr_3 <= reset_i;
+
+ THE_DLM_REFLECT: dlm_reflect port map (
+ clk => rclk_125_i, -- in std_logic;
+ res_n => cbm_res_n, -- in std_logic;
+ dlm_rec_in => cbm_dlm_rec_type, -- in std_logic_vector(3 downto 0);
+ dlm_rec_va_in => cbm_dlm_rec_va, -- in std_logic;
+ dlm_rec_out => open, -- out std_logic_vector(3 downto 0);
+ dlm_rec_va_out => open, -- out std_logic;
+ dlm2send_va => cbm_dlm2send_va, -- out std_logic;
+ dlm2send => cbm_dlm2send -- out std_logic_vector(3 downto 0)
+ );
+
+
+ PROC_DATA_SEND: process begin
+ wait until rising_edge(rclk_125_i);
+
+ cbm_data2send <= (others => '0');
+ cbm_data2send_start <= "0";
+ cbm_data2send_end <= "0";
+
+ if reset_i = '1' or send_enabled_i = '0' then
+ send_fsm_i <= START;
+ send_num_pack_counter_i <= (others => '0');
+
+ else
+ case(send_fsm_i) is
+ when START =>
+ if cbm_link_active='1' and cbm_data2send_stop = "0" then
+ send_fsm_i <= SEND_HEADER;
+ send_num_pack_counter_i <= send_num_pack_counter_i + 1;
+ send_length_i <= "0" & send_num_pack_counter_i(3 downto 0);
+ end if;
+
+ when SEND_HEADER =>
+ cbm_data2send <= x"f123";
+ cbm_data2send_start <= "1";
+ send_fsm_i <= SEND_PACK_NUM;
+
+ when SEND_PACK_NUM =>
+ cbm_data2send <= send_num_pack_counter_i;
+ send_fsm_i <= SEND_LENGTH;
+
+ when SEND_LENGTH =>
+ cbm_data2send(send_length_i'range) <= send_length_i;
+ send_fsm_i <= SEND_DATA;
+
+ when SEND_DATA =>
+ send_length_i <= send_length_i - 1;
+ cbm_data2send(15 downto 8) <= "0" & std_logic_vector(send_length_i(2 downto 0)) & std_logic_vector(send_length_i(3 downto 0));
+ cbm_data2send(send_length_i'high + 0 downto 0) <= send_length_i;
+
+ if send_length_i = TO_UNSIGNED(1, send_length_i'length) then
+ send_fsm_i <= SEND_FOOTER;
+ end if;
+
+ when SEND_FOOTER =>
+ cbm_data2send <= x"f321";
+ cbm_data2send_end <= "1";
+
+ send_wait_counter_i <= (others => '0');
+ send_fsm_i <= AFTER_SEND_WAIT;
+
+ when AFTER_SEND_WAIT =>
+ send_wait_counter_i <= STD_LOGIC_VECTOR( UNSIGNED(send_wait_counter_i) + 1 );
+ if send_wait_counter_i >= send_wait_threshold_i then
+ send_fsm_i <= START;
+ end if;
+
+ when others =>
+ send_fsm_i <= START;
+
+ end case;
+ end if;
+ end process;
+
+ PROC_DLM_COUNTER: process is
+ variable dlm_type_v : integer range 15 downto 0;
+ begin
+ wait until rising_edge(rclk_125_i);
+
+ if reset_i = '1' then
+ dlm_counter_i <= (others => '0');
+ dlm_glob_counter_i <= (others => '0');
+ elsif cbm_dlm_rec_va = '1' then
+ dlm_glob_counter_i <= dlm_glob_counter_i + TO_UNSIGNED(1,1);
+
+ dlm_type_v := to_integer(unsigned(cbm_dlm_rec_type));
+ for i in 0 to 15 loop
+ if dlm_type_v = i then
+ dlm_counter_i(1+i*2 downto i*2) <= dlm_counter_i(1+i*2 downto i*2) + TO_UNSIGNED(1,1);
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ phy_debug_i_buf <= phy_debug_i when rising_edge(clk_100_i);
+
+
+ PROC_REGIO_DEBUG: process is
+ variable address : integer range 0 to 255;
+ begin
+ wait until rising_edge(clk_100_i);
+ address := to_integer(unsigned(debug_addr));
+
+ debug_data_out <= x"00000000";
+
+ debug_ack <= debug_read_en or debug_write_en;
+ case address is
+ when 16#0# => debug_data_out <= x"0000" & phy_stat_op;
+ when 16#1# => debug_data_out <= x"0000" & phy_ctrl_op;
+ when 16#2# => debug_data_out <= phy_stat_debug(31 downto 0);
+ when 16#3# => debug_data_out <= phy_stat_debug(63 downto 32);
+ when 16#4# => debug_data_out <= phy_ctrl_debug(31 downto 0);
+ when 16#5# => debug_data_out <= phy_ctrl_debug(63 downto 32);
+ when 16#6# => debug_data_out <= STD_LOGIC_VECTOR(TO_UNSIGNED(CBM_FEE_MODE, 32));
+
+ when 16#20# => debug_data_out <= phy_debug_i_buf(31+32*0 downto 32*0);
+ when 16#21# => debug_data_out <= phy_debug_i_buf(31+32*1 downto 32*1);
+ when 16#22# => debug_data_out <= phy_debug_i_buf(31+32*2 downto 32*2);
+ when 16#23# => debug_data_out <= phy_debug_i_buf(31+32*3 downto 32*3);
+ when 16#24# => debug_data_out <= phy_debug_i_buf(31+32*4 downto 32*4);
+ when 16#25# => debug_data_out <= phy_debug_i_buf(31+32*5 downto 32*5);
+ when 16#26# => debug_data_out <= phy_debug_i_buf(31+32*6 downto 32*6);
+ when 16#27# => debug_data_out <= phy_debug_i_buf(31+32*7 downto 32*7);
+ when 16#28# => debug_data_out <= phy_debug_i_buf(31+32*8 downto 32*8);
+ when 16#29# => debug_data_out <= phy_debug_i_buf(31+32*9 downto 32*9);
+ when 16#2a# => debug_data_out <= phy_debug_i_buf(31+32*10 downto 32*10);
+ when 16#2b# => debug_data_out <= phy_debug_i_buf(31+32*11 downto 32*11);
+ when 16#2c# => debug_data_out <= phy_debug_i_buf(31+32*12 downto 32*12);
+ when 16#2d# => debug_data_out <= phy_debug_i_buf(31+32*13 downto 32*13);
+ when 16#2e# => debug_data_out <= phy_debug_i_buf(31+32*14 downto 32*14);
+ when 16#2f# => debug_data_out <= phy_debug_i_buf(31+32*15 downto 32*15);
+
+
+ when 16#10# => debug_data_out <= send_wait_threshold_i;
+ when 16#11# => debug_data_out(20 downto 0) <= "000" & cbm_data_from_link;
+
+ when 16#12# => debug_data_out <= STD_LOGIC_VECTOR(dlm_counter_i);
+ when 16#13# => debug_data_out <= STD_LOGIC_VECTOR(dlm_glob_counter_i);
+ when 16#14# =>
+ debug_data_out(21 downto 20) <= cbm_debug_overrides_i;
+ debug_data_out(19 downto 16) <= "0" & send_enabled_i & cbm_data2send_stop & cbm_link_active;
+ debug_data_out(15 downto 0) <= STD_LOGIC_VECTOR(send_num_pack_counter_i);
+
+
+ when 16#15# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_0;
+ when 16#16# => debug_data_out <= cbm_retrans_error_cntr_0 & cbm_retrans_cntr_0;
+ when 16#17# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_1;
+ when 16#18# => debug_data_out <= cbm_retrans_error_cntr_1 & cbm_retrans_cntr_1;
+ when 16#19# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_2;
+ when 16#1a# => debug_data_out <= cbm_retrans_error_cntr_2 & cbm_retrans_cntr_2;
+ when 16#1b# => debug_data_out(15 downto 0) <= cbm_crc_error_cntr_3;
+ when 16#1c# => debug_data_out <= cbm_retrans_error_cntr_3 & cbm_retrans_cntr_3;
+
+ when others => debug_ack <= '0';
+ end case;
+
+ if debug_write_en = '1' then
+ case (address) is
+ when 16#1# => phy_ctrl_op <= debug_data_in(15 downto 0);
+ when 16#4# => phy_ctrl_debug(31 downto 0) <= debug_data_in;
+ when 16#5# => phy_ctrl_debug(63 downto 32) <= debug_data_in;
+ when 16#10# => send_wait_threshold_i <= debug_data_in;
+ when 16#14# =>
+ send_enabled_i <= debug_data_in(18);
+ cbm_debug_overrides_i <= debug_data_in(21 downto 20);
+
+
+ when others => debug_ack <= '0';
+ end case;
+ end if;
+ end process;
+
+
+
+
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+ GSR_N <= pll_lock;
+
+ THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+ THE_MAIN_PLL : pll_in200_out100
+ port map(
+ CLK => CLK_GPLL_RIGHT,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
+ CLKOS => open,
+ LOCK => pll_lock1
+ );
+
+ pll_lock <= pll_lock1; -- and pll_lock2;
+
+-- GEN_TRBNET: if INCLUDE_TRBNET = c_YES generate
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+ generic map(
+ SERDES_NUM => 1, --number of serdes in quad
+ EXT_CLOCK => c_NO, --use internal clock
+ USE_200_MHZ => c_YES, --run on 200 MHz clock
+ USE_125_MHZ => c_NO,
+ USE_CTC => c_NO
+ )
+ port map(
+ CLK => clk_200_i,
+ SYSCLK => clk_100_i,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ CLK_EN => '1',
+ --Internal Connection
+ MED_DATA_IN => med_data_out,
+ MED_PACKET_NUM_IN => med_packet_num_out,
+ MED_DATAREADY_IN => med_dataready_out,
+ MED_READ_OUT => med_read_in,
+ MED_DATA_OUT => med_data_in,
+ MED_PACKET_NUM_OUT => med_packet_num_in,
+ MED_DATAREADY_OUT => med_dataready_in,
+ MED_READ_IN => med_read_out,
+ REFCLK2CORE_OUT => open,
+ --SFP Connection
+ SD_RXD_P_IN => SERDES_INT_RX(2),
+ SD_RXD_N_IN => SERDES_INT_RX(3),
+ SD_TXD_P_OUT => SERDES_INT_TX(2),
+ SD_TXD_N_OUT => SERDES_INT_TX(3),
+ SD_REFCLK_P_IN => open,
+ SD_REFCLK_N_IN => open,
+ SD_PRSNT_N_IN => FPGA5_COMM(0),
+ SD_LOS_IN => FPGA5_COMM(0),
+ SD_TXDIS_OUT => FPGA5_COMM(2),
+ -- Status and control port
+ STAT_OP => med_stat_op,
+ CTRL_OP => med_ctrl_op,
+ STAT_DEBUG => med_stat_debug,
+ CTRL_DEBUG => (others => '0'),
+
+ sci_ack => open,
+ clk_rx_full_out => open,
+ clk_rx_half_out => open
+ );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ generic map(
+ REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ BROADCAST_SPECIAL_ADDR => x"45",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"91000001",
+ REGIO_INIT_ADDRESS => x"f301",
+ REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**9-16
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_out, -- open, --
+ MED_DATA_OUT => med_data_out, -- open, --
+ MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
+ MED_READ_IN => med_read_in,
+ MED_DATAREADY_IN => med_dataready_in,
+ MED_DATA_IN => med_data_in,
+ MED_PACKET_NUM_IN => med_packet_num_in,
+ MED_READ_OUT => med_read_out, -- open, --
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_OUT => trg_invalid_i,
+
+ LVL1_TRG_TYPE_OUT => trg_type_i,
+ LVL1_TRG_NUMBER_OUT => trg_number_i,
+ LVL1_TRG_CODE_OUT => trg_code_i,
+ LVL1_TRG_INFORMATION_OUT => trg_information_i,
+ LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
+ TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+ TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
+ TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
+ TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+
+ --Response from FEE
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
+ FEE_DATA_IN => fee_data_i,
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i,
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+ REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+ REGIO_STAT_REG_IN => stat_reg, --start 0x80
+ REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
+ REGIO_STAT_STROBE_OUT => stat_reg_strobe,
+ REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+ BUS_ADDR_OUT => regio_addr_out,
+ BUS_READ_ENABLE_OUT => regio_read_enable_out,
+ BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+ BUS_DATA_OUT => regio_data_out,
+ BUS_DATA_IN => regio_data_in,
+ BUS_DATAREADY_IN => regio_dataready_in,
+ BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
+ BUS_WRITE_ACK_IN => regio_write_ack_in,
+ BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
+ BUS_TIMEOUT_OUT => regio_timeout_out,
+ ONEWIRE_INOUT => TEMPSENS,
+ ONEWIRE_MONITOR_OUT => open,
+
+ TIME_GLOBAL_OUT => global_time,
+ TIME_LOCAL_OUT => local_time,
+ TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+ TIME_TICKS_OUT => timer_ticks,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ STAT_DEBUG_DATA_HANDLER_OUT => open,
+ STAT_DEBUG_IPU_HANDLER_OUT => open,
+ STAT_TRIGGER_OUT => open,
+ CTRL_MPLEX => (others => '0'),
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"a000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 6, others => 0)
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ DAT_ADDR_IN => regio_addr_out,
+ DAT_DATA_IN => regio_data_out,
+ DAT_DATA_OUT => regio_data_in,
+ DAT_READ_ENABLE_IN => regio_read_enable_out,
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,
+ DAT_TIMEOUT_IN => regio_timeout_out,
+ DAT_DATAREADY_OUT => regio_dataready_in,
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(2) => debug_read_en,
+ BUS_WRITE_ENABLE_OUT(2) => debug_write_en,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => debug_data_in,
+ BUS_ADDR_OUT(2*16+5 downto 2*16) => debug_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+6) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(2*32+31 downto 2*32) => debug_data_out,
+ BUS_DATAREADY_IN(2) => debug_ack,
+ BUS_WRITE_ACK_IN(2) => debug_ack,
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+
+
+ STAT_DEBUG => open
+ );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => FLASH_CS,
+ SPI_SDI_IN => FLASH_DOUT,
+ SPI_SDO_OUT => FLASH_DIN,
+ SPI_SCK_OUT => FLASH_CLK,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+ port map(
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+ THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+ DO_REBOOT => common_ctrl_reg(15),
+ PROGRAMN => PROGRAMN
+ );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ LED_GREEN <= not med_stat_op(9);
+ LED_ORANGE <= not med_stat_op(10);
+ LED_RED <= not time_counter(26);
+ LED_YELLOW <= not med_stat_op(11);
+
+-- end generate;
+
+
end architecture;
\ No newline at end of file
jspc29 / trb3.git / commitdiff