User: Mainz A2: setup script changes for ADC CFD firmware

diff --git a/users/mainz_kph_a2/setup.sh b/users/mainz_kph_a2/setup.sh
index 8b106fd797661995386b086897a3cc1cfcf47081..c28fb4202a6cab8a9fddec1ca414c96a3ea422a5 100755 (executable)
--- a/users/mainz_kph_a2/setup.sh
+++ b/users/mainz_kph_a2/setup.sh
@@ -80,7 +80,7 @@ FPGA="0x0200"
 trbcmd w $FPGA 0xa010 0xff        #Buffer depth
 trbcmd w $FPGA 0xa011 8           #Samples after trigger
 trbcmd w $FPGA 0xa012 1           #Process blocks
-trbcmd w $FPGA 0xa013 40          #Trigger offset
+trbcmd w $FPGA 0xa013 0x10028     #Trigger offset, invert
 trbcmd w $FPGA 0xa014 40          #Readout offset
 trbcmd w $FPGA 0xa015 0           #Downsampling
 trbcmd w $FPGA 0xa016 8           #Baseline
@@ -88,6 +88,8 @@ trbcmd w $FPGA 0xa017 0           #Trigger Enable ch31-00
 trbcmd w $FPGA 0xa018 0           #Trigger Enable ch47-32
 trbcmd w $FPGA 0xa01a 0xfffffffe  #Channel disable ch31-00, all channels except ch0
 trbcmd w $FPGA 0xa01b 0xffff      #Channel disable ch47-32
+trbcmd w $FPGA 0xa01c 0           #Processing mode 0=BlockMode, 1=PSA, 2=CFD
+trbcmd w $FPGA 0xa01d 0x340       #CFD delay is 3, CFD window 64=0x40
 
 trbcmd w $FPGA 0xa020 1           #Sum values
 trbcmd w $FPGA 0xa021 1           #Sum values
@@ -103,7 +105,7 @@ trbcmd w $FPGA 0xa000 0x100       #Reset Baseline
 
 #####  CTS  #######
 trbcmd w 0x8000 0xa150 0x05f5e100  #set CTS pulser to 1Hz
-trbcmd setbit 0x8000 0xa101 0x2 #enable pulser channel 0
-#trbcmd setbit 0x8000 0xa101 0x1 # enable external trigger module
+#trbcmd setbit 0x8000 0xa101 0x2 #enable pulser channel 0
+trbcmd setbit 0x8000 0xa101 0x1 # enable external trigger module
 
 echo "Successfully setup TRB network"