.run_manager.ini
reportview.xml
.kateproject.d
+cts/project*
------------------------------------------------------------------------------
--include TDC for all four trigger input lines
- constant INCLUDE_TDC : integer range c_NO to c_YES := c_YES;
+ constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
--use all four SFP (1-4) as downlink to other boards.
constant USE_4_SFP : integer range c_NO to c_YES := c_NO;
+
+--Ports:
+-- LVL1/IPU SCtrl
+-- 0 FPGA 1 FPGA 1
+-- 1 FPGA 2 FPGA 2
+-- 2 FPGA 3 FPGA 3
+-- 3 FPGA 4 FPGA 4
+-- 4 opt. link opt. link
+-- 5-7 SFP 2-4
+-- 5(8) CTS read-out internal 0 1 - X X O --downlink only
+-- 6(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only
+
use work.config.all;
-- The description of hub ports is also there!
-
---Ports:
--- LVL1/IPU SCtrl
--- 0 FPGA 1 FPGA 1
--- 1 FPGA 2 FPGA 2
--- 2 FPGA 3 FPGA 3
--- 3 FPGA 4 FPGA 4
--- 4 opt. link opt. link
--- 5-7 SFP 2-4
--- 5(8) CTS read-out internal 0 1 - X X O --downlink only
--- 6(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only
-
--Slow Control
-- 0 - 7 Readout endpoint common status
###################################################################################
#Settings for this project
my $TOPNAME = "trb3_central"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
+#my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64';
# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
execute($c);
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
execute($c);
# IOR IO Timing Report
use ieee.numeric_std.all;
use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
package config is
--Hub configuration
------------------------------------------------------------------------------
type hub_mii_t is array(0 to 1) of integer;
- type hub_ct is array(0 to 16) of integer;
- type hub_cfg_t is array(0 to 1) of hub_ct;
+-- type hub_ct is array(0 to 16) of integer;
+ type hub_cfg_t is array(0 to 1) of hub_mii_config_t;
type hw_info_t is array(0 to 7) of std_logic_vector(31 downto 0);
- type hub_ch_t is array(0 to 3) of integer;
- type hub_chn_t is array(0 to 1) of hub_ch_t;
+-- type hub_ch_t is array(0 to 3) of integer;
+ type hub_chn_t is array(0 to 1) of hub_channel_config_t;
--this is used to select the proper configuration in the main code
constant CFG_MODE : integer;
--declare constants, filled in body
constant INTERNAL_NUM : integer;
constant INTERFACE_NUM : integer;
- constant IS_UPLINK : hub_ct;
- constant IS_DOWNLINK : hub_ct;
- constant IS_UPLINK_ONLY : hub_ct;
- constant INTERNAL_CHANNELS : hub_ct;
+ constant IS_UPLINK : hub_mii_config_t;
+ constant IS_DOWNLINK : hub_mii_config_t;
+ constant IS_UPLINK_ONLY : hub_mii_config_t;
+ constant INTERNAL_CHANNELS : hub_mii_config_t;
constant HARDWARE_INFO : std_logic_vector(31 downto 0);
- constant USED_CHANNELS : hub_ch_t;
+ constant USED_CHANNELS : hub_channel_config_t;
constant CLOCK_FREQUENCY : integer;
constant MEDIA_FREQUENCY : integer;
constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE);
constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
- constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
- constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
- constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
- constant INTERNAL_CHANNELS : hub_ct := INTERNAL_CHANNEL_ARR(CFG_MODE);
+ constant IS_UPLINK : hub_mii_config_t := IS_UPLINK_ARR(CFG_MODE);
+ constant IS_DOWNLINK : hub_mii_config_t := IS_DOWNLINK_ARR(CFG_MODE);
+ constant IS_UPLINK_ONLY : hub_mii_config_t := IS_UPLINK_ONLY_ARR(CFG_MODE);
+ constant INTERNAL_CHANNELS : hub_mii_config_t := INTERNAL_CHANNEL_ARR(CFG_MODE);
constant HARDWARE_INFO : std_logic_vector(31 downto 0) := HARDWARE_INFO_ARR(HW_INFO_MODE);
- constant USED_CHANNELS : hub_ch_t := USED_CHANNELS_ARR(USE_SCTRL_ONLY);
+ constant USED_CHANNELS : hub_channel_config_t := USED_CHANNELS_ARR(USE_SCTRL_ONLY);
constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
<BaliProject version="2.0" title="trb3_gbe" device="LFE3-150EA-8FN1156C" default_implementation="trb3_gbe">
<Options/>
<Implementation title="trb3_gbe" dir="trb3_gbe" description="trb3_gbe" default_strategy="Strategy1">
- <Options top="trb3_central"/>
+ <Options def_top="pll_in200_out100" top="trb3_central"/>
<Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Options/>
</Source>
<Source name="../trb3_central.vhd" type="VHDL" type_short="VHDL">
- <Options/>
+ <Options top_module="trb3_central"/>
</Source>
<Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
<Options/>
-w
-i 15
-l 5
--n 2
+-n 1
-y
-s 12
-t 15
--- /dev/null
+-rem
+-distrce
+-log "trb3_gbe_trb3_gbe.log"
+-o "trb3_gbe_trb3_gbe.csv"
+-pr "trb3_gbe_trb3_gbe.prf"
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "config.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
add_file -vhdl -lib work "../base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
--- /dev/null
+-v
+10
+
+
+
+
+-gt
+-sethld
+-sp 8
+-sphld m
attribute syn_preserve of GSR_N : signal is true;
--FPGA Test
- signal time_counter, time_counter2 : unsigned(31 downto 0);
signal rx_clock : std_logic;
signal rx_clock_half : std_logic;
signal rx_clock_full : std_logic;
);
-
---
--- THE_SPI_MASTER: spi_master
--- port map(
--- CLK_IN => clk_sys_i,
--- RESET_IN => reset_i,
--- -- Slave bus
--- BUS_READ_IN => spictrl_read_en,
--- BUS_WRITE_IN => spictrl_write_en,
--- BUS_BUSY_OUT => spictrl_busy,
--- BUS_ACK_OUT => spictrl_ack,
--- BUS_ADDR_IN(0) => spictrl_addr,
--- BUS_DATA_IN => spictrl_data_in,
--- BUS_DATA_OUT => spictrl_data_out,
--- -- SPI connections
--- SPI_CS_OUT => FLASH_CS,
--- SPI_SDI_IN => FLASH_DOUT,
--- SPI_SDO_OUT => FLASH_DIN,
--- SPI_SCK_OUT => FLASH_CLK,
--- -- BRAM for read/write data
--- BRAM_A_OUT => spi_bram_addr,
--- BRAM_WR_D_IN => spi_bram_wr_d,
--- BRAM_RD_D_OUT => spi_bram_rd_d,
--- BRAM_WE_OUT => spi_bram_we,
--- -- Status lines
--- STAT => open
--- );
---
--- -- data memory for SPI accesses
--- THE_SPI_MEMORY: spi_databus_memory
--- port map(
--- CLK_IN => clk_sys_i,
--- RESET_IN => reset_i,
--- -- Slave bus
--- BUS_ADDR_IN => spimem_addr,
--- BUS_READ_IN => spimem_read_en,
--- BUS_WRITE_IN => spimem_write_en,
--- BUS_ACK_OUT => spimem_ack,
--- BUS_DATA_IN => spimem_data_in,
--- BUS_DATA_OUT => spimem_data_out,
--- -- state machine connections
--- BRAM_ADDR_IN => spi_bram_addr,
--- BRAM_WR_D_OUT => spi_bram_wr_d,
--- BRAM_RD_D_IN => spi_bram_rd_d,
--- BRAM_WE_IN => spi_bram_we,
--- -- Status lines
--- STAT => open
--- );
---
--- ---------------------------------------------------------------------------
--- -- Reboot FPGA
--- ---------------------------------------------------------------------------
--- THE_FPGA_REBOOT : fpga_reboot
--- port map(
--- CLK => clk_sys_i,
--- RESET => reset_i,
--- DO_REBOOT => common_ctrl_regs(15),
--- PROGRAMN => PROGRAMN
--- );
-
-
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- FPGA communication
---------------------------------------------------------------------------
--- FPGA1_COMM <= (others => 'Z');
--- FPGA2_COMM <= (others => 'Z');
--- FPGA3_COMM <= (others => 'Z');
--- FPGA4_COMM <= (others => 'Z');
FPGA1_TTL <= (others => 'Z');
FPGA2_TTL <= (others => 'Z');
---------------------------------------------------------------------------
LED_CLOCK_GREEN <= '0';
LED_CLOCK_RED <= '1';
--- LED_GREEN <= not med_stat_op(9);
--- LED_YELLOW <= not med_stat_op(10);
--- LED_ORANGE <= not med_stat_op(11);
--- LED_RED <= '1';
LED_TRIGGER_GREEN <= not med_stat_op(4*16+9);
LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10));
-
---LED_GREEN <= time_counter(27);
---LED_ORANGE <= time_counter2(27);
---LED_RED <= debug(2);
---LED_YELLOW <= debug(3);
-
-LED_GREEN <= debug(0);
-LED_ORANGE <= debug(1);
-LED_RED <= debug(2);
-LED_YELLOW <= link_ok; --debug(3);
+ LED_GREEN <= debug(0);
+ LED_ORANGE <= debug(1);
+ LED_RED <= debug(2);
+ LED_YELLOW <= link_ok; --debug(3);
---------------------------------------------------------------------------
CLK_TEST_OUT <= clk_med_i & '0' & clk_sys_i;
-
--- FPGA1_CONNECTOR(0) <= '0';
- FPGA2_CONNECTOR(0) <= '0';
--- FPGA3_CONNECTOR(0) <= '0';
--- FPGA4_CONNECTOR(0) <= '0';
-
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_sys_internal);
- time_counter <= time_counter + 1;
- end process;
+
end architecture;