preparation of threshold FPGA for DiRICH4; still compatible with old one if set in...

diff --git a/pinout/thresholds_dirich4.lpf b/pinout/thresholds_dirich4.lpf
new file mode 100644 (file)
index 0000000..121a4c8
--- /dev/null
+++ b/pinout/thresholds_dirich4.lpf
@@ -0,0 +1,55 @@
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+SYSCONFIG MCCLK_FREQ=33.25 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE I2C_PORT=ENABLE ;
+
+LOCATE COMP "MISO_OUT"                       SITE "E1";    #DAC1_CTRL0
+LOCATE COMP "MOSI_IN"                        SITE "F1";    #DAC1_CTRL1
+LOCATE COMP "SCLK_IN"                        SITE "D9";    #DAC1_CTRL2
+LOCATE COMP "CS_IN"                          SITE "G9";    #DAC1_CTRL3
+IOBUF PORT "MISO_OUT" IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "MOSI_IN"  IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "SCLK_IN"  IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "CS_IN"    IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+LOCATE COMP "OUTPUT[1]"         SITE "C1";
+LOCATE COMP "OUTPUT[2]"         SITE "J3";
+LOCATE COMP "OUTPUT[3]"         SITE "J7";
+LOCATE COMP "OUTPUT[4]"         SITE "B1";
+LOCATE COMP "OUTPUT[5]"         SITE "A2";
+LOCATE COMP "OUTPUT[6]"         SITE "A8";
+LOCATE COMP "OUTPUT[7]"         SITE "A3";
+LOCATE COMP "OUTPUT[8]"         SITE "H9";
+LOCATE COMP "OUTPUT[9]"         SITE "B4";
+LOCATE COMP "OUTPUT[10]"        SITE "A6";
+LOCATE COMP "OUTPUT[11]"        SITE "B9";
+LOCATE COMP "OUTPUT[12]"        SITE "J8";
+LOCATE COMP "OUTPUT[13]"        SITE "J6";
+LOCATE COMP "OUTPUT[14]"        SITE "J5";
+LOCATE COMP "OUTPUT[15]"        SITE "J2";
+LOCATE COMP "OUTPUT[16]"        SITE "H1";
+DEFINE PORT GROUP "OUTPUT_group" "OUTPUT*" ;
+IOBUF GROUP  "OUTPUT_group" IO_TYPE=LVCMOS25  DRIVE=4 SLEWRATE=SLOW BANK_VCCIO=2.5 ;
+
+###
+LOCATE COMP "DAC_FLAG"                       SITE "G1";
+IOBUF PORT "DAC_FLAG" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+# LOCATE COMP "PWM_IN17" 1                      SITE "A6";
+# LOCATE COMP "PWM_IN18" 2                      SITE "A5";
+# LOCATE COMP "PWM_IN19" 3                      SITE "A3";
+# LOCATE COMP "PWM_IN20" 4                      SITE "A8";
+# LOCATE COMP "PWM_IN21" 5                      SITE "B1";
+# LOCATE COMP "PWM_IN22" 6                      SITE "H9";
+# LOCATE COMP "PWM_IN23" 7                      SITE "B9";
+# LOCATE COMP "PWM_IN24" 8                      SITE "J7";
+# LOCATE COMP "PWM_IN25" 9                      SITE "J8";
+# LOCATE COMP "PWM_IN26" 10                      SITE "J2";
+# LOCATE COMP "PWM_IN27" 11                      SITE "H1";
+# LOCATE COMP "PWM_IN28" 12                      SITE "J5";
+# LOCATE COMP "PWM_IN29" 13                      SITE "J3";
+# LOCATE COMP "PWM_IN30" 14                      SITE "J6";
+# LOCATE COMP "PWM_IN31" 15                      SITE "C1";
+# LOCATE COMP "PWM_IN32" 16                      SITE "A2";

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index f99281428024b90b66144c81c14fad281a0e5ff4..983193460972f50767e0dc00f21e1777f7d6ec50 100644 (file)
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -12,8 +12,10 @@ add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash_I2C_Prog.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit_i2cProg.v"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 add_file -vhdl -lib work "thresholds.vhd"

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index f4df69ac8065e37f7c7c0adbf9e4619bc60a2d09..4b68b9682b53059762c32217d2d217ec55464295 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -16,7 +16,9 @@ entity thresholds is
     MISO_OUT : out std_logic;\r
     MOSI_IN  : in  std_logic;\r
     SCLK_IN  : in  std_logic;\r
-    CS_IN    : in  std_logic--;\r
+    CS_IN    : in  std_logic;\r
+    SCL      : inout std_logic;\r
+    SDA      : inout std_logic--;\r
     --LED           : out std_logic_vector(7 downto 0);\r
     --DIPSW    : in std_logic_vector(3 downto 0)\r
     );\r
@@ -90,7 +92,6 @@ THE_PLL : entity work.pll_in133_out33_133_66
      CLKOS2=> clk_66  --66\r
   );  \r
 \r
-\r
 ---------------------------------------------------------------------------\r
 -- SPI\r
 ---------------------------------------------------------------------------\r
@@ -121,6 +122,9 @@ THE_SPI : entity work.spi_slave
   );\r
 \r
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
+  generic map (\r
+    USE_I2C_PROG => c_YES              -- DiRICH1,2,3: c_YES ; DiRICH4: c_NO\r
+  )\r
   port map(\r
 \r
     CLK_f => clk_33,\r
@@ -141,8 +145,10 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     LOC_WRITE_OUT => bus_write,\r
     LOC_READ_OUT  => bus_read,\r
     LOC_READY_IN  => bus_ready,\r
-    LOC_BUSY_OUT  => bus_busy\r
-                      \r
+    LOC_BUSY_OUT  => bus_busy,\r
+    \r
+    SCL           => SCL,\r
+    SDA           => SDA\r
   );  \r
 \r
 PROC_REGS : process begin\r