correcting changes in lpf files

diff --git a/base/trb3_central_cts.lpf b/base/trb3_central_cts.lpf
index 00a56f45e584a53ef368569b3f5bc6d8e62dba61..ef0c7105d616568d252bb288a4dd13053b69b55b 100644 (file)
--- a/base/trb3_central_cts.lpf
+++ b/base/trb3_central_cts.lpf
@@ -69,6 +69,13 @@ LOCATE COMP  "CLK_TEST_OUT_0"   SITE "U9";
 IOBUF  PORT  "CLK_TEST_OUT_0"  IO_TYPE=LVDS25 ; 
 
 
+LOCATE COMP  "CLKRJ_0"   SITE "U9"; 
+LOCATE COMP  "CLKRJ_1"   SITE "U8"; 
+LOCATE COMP  "CLKRJ_2"   SITE "Y34";
+LOCATE COMP  "CLKRJ_3"   SITE "Y33"; 
+DEFINE PORT GROUP "CLKRJ_group" "CLKRJ*" ;
+IOBUF GROUP  "CLKRJ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;
+
 #################################################################
 # Clock and Trigger Select
 #################################################################

diff --git a/base/trb3_periph_mvdjtag.lpf b/base/trb3_periph_mvdjtag.lpf
index 2ede859df0ba15601701cf32abcb6a7ea912f878..5ffbe7b3f8c033115dd00db7691a6eba8e92af03 100644 (file)
--- a/base/trb3_periph_mvdjtag.lpf
+++ b/base/trb3_periph_mvdjtag.lpf
@@ -107,12 +107,6 @@ LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
 DEFINE PORT GROUP "CLK_group" "CLK*" ;
 IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 ;
 
-LOCATE COMP  "CLKRJ_0"   SITE "U9"; 
-LOCATE COMP  "CLKRJ_1"   SITE "U8"; 
-LOCATE COMP  "CLKRJ_2"   SITE "Y34";
-LOCATE COMP  "CLKRJ_3"   SITE "Y33"; 
-DEFINE PORT GROUP "CLKRJ_group" "CLKRJ*" ;
-IOBUF GROUP  "CLKRJ_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;
 
 #################################################################
 # Trigger I/O