add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
SYSCONFIG MCCLK_FREQ = 20;
-FREQUENCY PORT CLK_CORE_PCLK 240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz;
-FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz;
+FREQUENCY PORT CLK_CORE_PCLK 200 MHz;
+FREQUENCY PORT CLK_CORE_PLL_LEFT 200 MHz;
+FREQUENCY PORT CLK_CORE_PLL_RIGHT 200 MHz;
FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz;
FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz;
# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-#main serdes is PCSB for stand-along or PCSA for crate operation
+#main serdes is PCSB for stand-alone or PCSA for crate operation
LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ;
#REGION "MEDIA_UPLINK" "R96C107D" 19 24;
--- /dev/null
+// nodes file for parallel place&route
+
+[jspc29]
+SYSTEM = linux
+CORENUM = 3
+ENV = /d/jspc29/lattice/36_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb3sc/adcaddon/workdir
+
+[jspc57]
+SYSTEM = linux
+CORENUM = 7
+ENV = /d/jspc29/lattice/36_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb3sc/adcaddon/workdir
lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
synplify_path => '/d/jspc29/lattice/synplify/N-2017.09-1/',
nodelist_file => 'nodes_frankfurt.txt',
-# synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/tdctemplate/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3sc_tdctemplate.prj\" #",
#Include only necessary lpf files
#pinout_file => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME
pinout_file => 'trb3sc_padiwa', #name of pin-out file, if not equal TOPNAME
add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
#Basic Infrastructure
add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
-add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200_200oscillator.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"