--set to 0 for backplane serdes, set to 3 for front SFP serdes
constant SERDES_NUM : integer := 3;
- constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_UART : integer := c_NO;
constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_ADC : integer := c_YES;
constant INCLUDE_I2C : integer := c_NO;
- constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
--input monitor and trigger generation logic
constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
TOPNAME => "trb3sc_basic",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
-synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/',
+lattice_path => '/d/jspc29/lattice/diamond/3.12',
+synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/',
#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+#add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
#SlowControl files
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"