file cleanup, DLM ping works now

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index e2ffcc2d45959dc0e1a3c06b61036d51b616a9a9..e271d832a4fa461e9b96291e2589e82530a371fd 100644 (file)
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -51,8 +51,6 @@ impl -active "workdir"
 
 ####################
 
-
-
 #Packages
 add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "config.vhd"
@@ -136,8 +134,6 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
@@ -189,7 +185,6 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
 
 add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd"
 
-
 #GbE
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
@@ -243,7 +238,6 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd"
 
-
 add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index f3b9cdf2370930d1907464d3a49d79542cb52380..6402070a05173fe265131ff2445b6be69681243c 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -62,10 +62,10 @@ entity trb3sc_cts is
     ADC_DIN              : out   std_logic;
     ADC_DOUT             : in    std_logic;
     --SPI
-    DAC_OUT_SDO      : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
-    DAC_OUT_SCK      : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
-    DAC_OUT_CS       : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
-    DAC_IN_SDI       : in  std_logic_vector(6 downto 5+2*USE_RJADAPT);
+    DAC_OUT_SDO          : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+    DAC_OUT_SCK          : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+    DAC_OUT_CS           : out std_logic_vector(6 downto 5+2*USE_RJADAPT);
+    DAC_IN_SDI           : in  std_logic_vector(6 downto 5+2*USE_RJADAPT);
     --Flash, 1-wire, Reload
     FLASH_CLK            : out   std_logic;
     FLASH_CS             : out   std_logic;
@@ -396,7 +396,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
   )
   port map (
     CLEAR                => '0',
-    LOCALCLK             => clk_full_osc,
+    CLK_REF              => clk_full_osc,
     TX_PLL_LOL_QD_A_IN   => '0',
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
     TX_PLL_LOL_QD_C_IN   => '0',

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 3bfb02981d53252d3303f62c79e1c76c407fd789..fa77b4a7e7650e4a53ed5fbd1ff35421496ddfcc 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -100,8 +100,6 @@ impl -active "workdir"
 
 ####################
 
-
-
 #Packages
 add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "config.vhd"
@@ -123,8 +121,6 @@ add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
 
-
-
 #Fifos
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
@@ -152,7 +148,6 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dual
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
 
-
 #Flash & Reload, Tools
 add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
@@ -184,10 +179,11 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_lsm_RS.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_rsl.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd"

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index ed22588ce3d9f714b4c8f1149d22da5484a6da62..29ecb05ff8b8d775025430f067d6be2283f0baf7 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -291,7 +291,7 @@ end generate;
   )
   port map (
     CLEAR                => '0',
-    LOCALCLK             => clk_full_osc,
+    CLK_REF              => clk_full_osc,
     TX_PLL_LOL_QD_A_IN   => '0',
     TX_PLL_LOL_QD_B_IN   => tx_pll_lol_qd_b_i,
     TX_PLL_LOL_QD_C_IN   => '0',
@@ -449,7 +449,9 @@ end generate;
 
 --  RJ_IO(1 downto 0) <= trig_gen_out_i(3 downto 2);
   RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);
-
+  RJ_IO(1)          <= debug_i(1);
+  RJ_IO(0)          <= debug_i(0);
+  
   BACK_GPIO(1 downto 0)  <= (others => 'Z');
   BACK_GPIO(3 downto 2)  <= trig_gen_out_i(3 downto 2);