Add dqsinput_4x5 file to project

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index b90c68dab44dbd4fd9583b3acb6c53327360ff69..ae59479a7afd0563b93e0bc50093f9f3e963eb77 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -151,6 +151,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_80.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput_4x5.vhd"
 add_file -vhdl -lib "work" "sim/dqsinput_dummy.vhd"
 add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
 add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
@@ -207,4 +208,4 @@ if {$INCLUDE_TDC == 1} {
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
    add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
-}
\ No newline at end of file
+}