--- /dev/null
+Date=01/04/2016
+Time=13:41:19
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=fifo_18x2k_oreg
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:41:19
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=18
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_18x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill
--- /dev/null
+<!DOCTYPE fifo_18x2k_oreg>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO</spirit:name>
+ <spirit:version>5.1</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_18x2k_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_18x2k_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:41:22 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:41:22 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">fifo_18x2k_oreg</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:41:19</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2048</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnFWFT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n fifo_18x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>fifo_18x2k_oreg</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.1
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.fdc
+
+-- Mon Jan 4 13:41:22 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_18x2k_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(10 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(11 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x2k_oreg;
+
+architecture Structure of fifo_18x2k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal rptr_11: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal co4_3: std_logic;
+ signal wcount_11: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co5_2: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal wcount_0: std_logic;
+ signal cnt_con: std_logic;
+ signal precin: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal co5_3: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_18x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_18x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_5: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_4: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_3: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_2: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb);
+
+ INV_0: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ pdp_ram_0_0_1: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8,
+ ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4,
+ ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo,
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9,
+ ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5,
+ ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1,
+ ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open,
+ DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open,
+ DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>Q(8), DOB7=>Q(7),
+ DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2),
+ DOB1=>Q(1), DOB0=>Q(0));
+
+ pdp_ram_0_1_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(17), DIA7=>Data(16), DIA6=>Data(15),
+ DIA5=>Data(14), DIA4=>Data(13), DIA3=>Data(12),
+ DIA2=>Data(11), DIA1=>Data(10), DIA0=>Data(9),
+ ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, ADA10=>wptr_7,
+ ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, ADA6=>wptr_3,
+ ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, ADA2=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA0=>scuba_vlo, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA2=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7,
+ ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3,
+ ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i,
+ OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo,
+ RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open,
+ DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open,
+ DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open,
+ DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open,
+ DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open,
+ DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open,
+ DOB10=>open, DOB9=>open, DOB8=>Q(17), DOB7=>Q(16),
+ DOB6=>Q(15), DOB5=>Q(14), DOB4=>Q(13), DOB3=>Q(12),
+ DOB2=>Q(11), DOB1=>Q(10), DOB0=>Q(9));
+
+ FF_74: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_73: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_72: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_71: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_70: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_69: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_68: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_67: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_66: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_65: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_64: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_63: FD1P3DX
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_62: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_61: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_60: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_59: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_58: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_57: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_56: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_55: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_54: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_53: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_52: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_51: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_50: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_49: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_48: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_47: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_46: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_45: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_44: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_43: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_42: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_41: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_40: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_39: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_38: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_37: FD1P3DX
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_36: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_35: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_34: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_33: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_32: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_31: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_30: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_29: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_28: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_27: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_26: FD1P3DX
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_25: FD1P3DX
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_24: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_23: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_22: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_21: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_20: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_19: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_18: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_17: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_16: FD1P3DX
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_15: FD1P3DX
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_14: FD1P3DX
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_13: FD1P3DX
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_12: FD1S3DX
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_11: FD1S3DX
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_10: FD1S3DX
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_9: FD1S3DX
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_8: FD1S3DX
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_7: FD1S3DX
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_6: FD1S3DX
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_5: FD1S3DX
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_4: FD1S3DX
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_3: FD1S3DX
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_2: FD1S3DX
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_1: FD1S3DX
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+ bdcnt_bctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+ bdcnt_bctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+ bdcnt_bctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+ bdcnt_bctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+ bdcnt_bctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+ bdcnt_bctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+ e_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ e_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+ e_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2,
+ B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+ e_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4,
+ B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+ e_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6,
+ B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+ e_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8,
+ B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+ e_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10,
+ B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open,
+ COUT=>cmp_le_1_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open,
+ COUT=>open);
+
+ g_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ g_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+ g_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ g_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+ g_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+ g_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+ g_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i,
+ B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open,
+ COUT=>cmp_ge_d1_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open,
+ COUT=>open);
+
+ w_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+ w_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0_3);
+
+ w_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1_3);
+
+ w_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2_3);
+
+ w_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7,
+ COUT=>co3_3);
+
+ w_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9,
+ COUT=>co4_3);
+
+ w_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11,
+ COUT=>co5_1);
+
+ r_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+ r_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_4);
+
+ r_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_4);
+
+ r_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_4);
+
+ r_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7,
+ COUT=>co3_4);
+
+ r_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9,
+ COUT=>co4_4);
+
+ r_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11,
+ COUT=>co5_2);
+
+ precin_inst245: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000",
+ INIT0=> X"0000")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+ wcnt_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+ wcnt_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+ wcnt_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+ wcnt_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+ wcnt_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8, COUT=>co4_5);
+
+ wcnt_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10, COUT=>co5_3);
+
+ wcnt_6: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co5_3, S0=>wcnt_sub_11, S1=>open,
+ COUT=>open);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_6);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open,
+ COUT=>co1_6);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open,
+ COUT=>co2_6);
+
+ af_set_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open,
+ COUT=>co3_6);
+
+ af_set_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open,
+ COUT=>co4_6);
+
+ af_set_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:48:58
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=fifo_36x256_oreg
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:48:58
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=256
+Width=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+Reset1=Sync
+RDataCount=1
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_36x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 36 -regout -no_enable -pe -1 -pf 0 -sync_reset -fill
--- /dev/null
+<!DOCTYPE fifo_36x256_oreg>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO</spirit:name>
+ <spirit:version>5.1</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_36x256_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_36x256_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:48:59 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:48:59 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">fifo_36x256_oreg</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:48:58</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">256</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnFWFT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">36</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n fifo_36x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 36 -regout -no_enable -pe -1 -pf 0 -sync_reset -fill</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>fifo_36x256_oreg</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.1
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 36 -regout -no_enable -pe -1 -pf 0 -sync_reset -fill -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.fdc
+
+-- Mon Jan 4 13:48:59 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_36x256_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x256_oreg;
+
+architecture Structure of fifo_36x256_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal rptr_8: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal co4_1: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal co4_2: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal wcount_0: std_logic;
+ signal cnt_con: std_logic;
+ signal precin: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal rptr_7: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal co4_3d: std_logic;
+ signal co4_3: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x256_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_5: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_4: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_3: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_2: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_8, B=>rptr_8, Z=>wcnt_sub_msb);
+
+ INV_0: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ pdp_ram_0_0_0: PDPW16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED",
+ RESETMODE=> "SYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ port map (DI35=>Data(35), DI34=>Data(34), DI33=>Data(33),
+ DI32=>Data(32), DI31=>Data(31), DI30=>Data(30),
+ DI29=>Data(29), DI28=>Data(28), DI27=>Data(27),
+ DI26=>Data(26), DI25=>Data(25), DI24=>Data(24),
+ DI23=>Data(23), DI22=>Data(22), DI21=>Data(21),
+ DI20=>Data(20), DI19=>Data(19), DI18=>Data(18),
+ DI17=>Data(17), DI16=>Data(16), DI15=>Data(15),
+ DI14=>Data(14), DI13=>Data(13), DI12=>Data(12),
+ DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8),
+ DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4),
+ DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0),
+ ADW8=>scuba_vlo, ADW7=>wptr_7, ADW6=>wptr_6, ADW5=>wptr_5,
+ ADW4=>wptr_4, ADW3=>wptr_3, ADW2=>wptr_2, ADW1=>wptr_1,
+ ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, BE1=>scuba_vhi,
+ BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW2=>scuba_vlo,
+ CSW1=>scuba_vlo, CSW0=>scuba_vhi, ADR13=>scuba_vlo,
+ ADR12=>rptr_7, ADR11=>rptr_6, ADR10=>rptr_5, ADR9=>rptr_4,
+ ADR8=>rptr_3, ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0,
+ ADR4=>scuba_vlo, ADR3=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR0=>scuba_vlo, CER=>scuba_vhi,
+ OCER=>scuba_vhi, CLKR=>Clock, CSR2=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR0=>rden_i, RST=>Reset, DO35=>Q(17),
+ DO34=>Q(16), DO33=>Q(15), DO32=>Q(14), DO31=>Q(13),
+ DO30=>Q(12), DO29=>Q(11), DO28=>Q(10), DO27=>Q(9),
+ DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), DO23=>Q(5), DO22=>Q(4),
+ DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), DO18=>Q(0), DO17=>Q(35),
+ DO16=>Q(34), DO15=>Q(33), DO14=>Q(32), DO13=>Q(31),
+ DO12=>Q(30), DO11=>Q(29), DO10=>Q(28), DO9=>Q(27),
+ DO8=>Q(26), DO7=>Q(25), DO6=>Q(24), DO5=>Q(23), DO4=>Q(22),
+ DO3=>Q(21), DO2=>Q(20), DO1=>Q(19), DO0=>Q(18));
+
+ FF_56: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_55: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_54: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_53: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_52: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_51: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_50: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_49: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_48: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_47: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_46: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_45: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_44: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_43: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_42: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_41: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_40: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_39: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_38: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_37: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_36: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_35: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_34: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_33: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_32: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_31: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_30: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_29: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_28: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_27: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_26: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_25: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_24: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_23: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_22: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_21: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_20: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_19: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_18: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_17: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_16: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_15: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_14: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_13: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_12: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_11: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_10: FD1P3DX
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_9: FD1S3DX
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_8: FD1S3DX
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_7: FD1S3DX
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_6: FD1S3DX
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_5: FD1S3DX
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_4: FD1S3DX
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_3: FD1S3DX
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_2: FD1S3DX
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_1: FD1S3DX
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+ bdcnt_bctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+ bdcnt_bctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+ bdcnt_bctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+ bdcnt_bctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+ bdcnt_bctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3, S0=>ifcount_8, S1=>open, COUT=>co4);
+
+ e_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ e_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+ e_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2,
+ B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+ e_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4,
+ B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+ e_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6,
+ B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+ e_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open,
+ COUT=>cmp_le_1_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open,
+ COUT=>open);
+
+ g_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ g_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+ g_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ g_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+ g_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+ g_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_2, S0=>open, S1=>open,
+ COUT=>cmp_ge_d1_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open,
+ COUT=>open);
+
+ w_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+ w_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0_3);
+
+ w_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1_3);
+
+ w_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2_3);
+
+ w_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7,
+ COUT=>co3_3);
+
+ w_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_8, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>open,
+ COUT=>co4_1);
+
+ r_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+ r_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_4);
+
+ r_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_4);
+
+ r_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_4);
+
+ r_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7,
+ COUT=>co3_4);
+
+ r_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_8, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>open,
+ COUT=>co4_2);
+
+ precin_inst261: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000",
+ INIT0=> X"0000")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin);
+
+ wcnt_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5);
+
+ wcnt_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5);
+
+ wcnt_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, COUT=>co2_5);
+
+ wcnt_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6, COUT=>co3_5);
+
+ wcnt_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_7, A1=>wcnt_sub_msb, B0=>rptr_7,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8,
+ COUT=>co4_3);
+
+ wcntd: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_3, S0=>co4_3d, S1=>open, COUT=>open);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_6);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open,
+ COUT=>co1_6);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open,
+ COUT=>co2_6);
+
+ af_set_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open,
+ COUT=>co3_6);
+
+ af_set_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcnt_reg_8, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:39:56
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=5.1
+ModuleName=fifo_9x2k_oreg
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:39:56
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=9
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+Reset1=Sync
+RDataCount=0
+EnECC=0
+EnFWFT=0
+
+[Command]
+cmd_line= -w -n fifo_9x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 9 -regout -no_enable -pe -1 -pf -1 -sync_reset
--- /dev/null
+<!DOCTYPE fifo_9x2k_oreg>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO</spirit:name>
+ <spirit:version>5.1</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_9x2k_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./fifo_9x2k_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:39:59 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:39:59 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">fifo_9x2k_oreg</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:39:56</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2048</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnFWFT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">508</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">9</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n fifo_9x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 9 -regout -no_enable -pe -1 -pf -1 -sync_reset</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>fifo_9x2k_oreg</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.1
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n fifo_9x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 9 -regout -no_enable -pe -1 -pf -1 -sync_reset -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.fdc
+
+-- Mon Jan 4 13:39:59 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity fifo_9x2k_oreg is
+ port (
+ Data: in std_logic_vector(8 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_9x2k_oreg;
+
+architecture Structure of fifo_9x2k_oreg is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co5: std_logic;
+ signal cnt_con: std_logic;
+ signal co4: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal co4_3: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co5_2: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_9x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"3232")
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>wcount_10, ADA12=>wcount_9,
+ ADA11=>wcount_8, ADA10=>wcount_7, ADA9=>wcount_6,
+ ADA8=>wcount_5, ADA7=>wcount_4, ADA6=>wcount_3,
+ ADA5=>wcount_2, ADA4=>wcount_1, ADA3=>wcount_0,
+ ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo,
+ CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo,
+ RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB0=>scuba_vlo, ADB13=>rcount_10, ADB12=>rcount_9,
+ ADB11=>rcount_8, ADB10=>rcount_7, ADB9=>rcount_6,
+ ADB8=>rcount_5, ADB7=>rcount_4, ADB6=>rcount_3,
+ ADB5=>rcount_2, ADB4=>rcount_1, ADB3=>rcount_0,
+ ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo,
+ CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo,
+ RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open,
+ DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open,
+ DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open,
+ DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open,
+ DOA0=>open, DOB17=>open, DOB16=>open, DOB15=>open,
+ DOB14=>open, DOB13=>open, DOB12=>open, DOB11=>open,
+ DOB10=>open, DOB9=>open, DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6),
+ DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1),
+ DOB0=>Q(0));
+
+ FF_37: FD1P3DX
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_36: FD1P3DX
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_35: FD1P3DX
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_34: FD1P3DX
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_33: FD1P3DX
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_32: FD1P3DX
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_31: FD1P3DX
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_30: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_29: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_28: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_27: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_26: FD1P3DX
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_25: FD1S3BX
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_24: FD1S3DX
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_23: FD1P3DX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_22: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_21: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_20: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_19: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_18: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_17: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_16: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_15: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_14: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_13: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_12: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_11: FD1P3DX
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_10: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_9: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_8: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_7: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_6: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_5: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_4: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_3: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_2: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_1: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_0: FD1P3DX
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ bdcnt_bctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci);
+
+ bdcnt_bctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0);
+
+ bdcnt_bctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1);
+
+ bdcnt_bctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2);
+
+ bdcnt_bctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3);
+
+ bdcnt_bctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4);
+
+ bdcnt_bctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>cnt_con, B1=>cnt_con,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co4, S0=>ifcount_10, S1=>ifcount_11, COUT=>co5);
+
+ e_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ e_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1);
+
+ e_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2,
+ B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1);
+
+ e_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4,
+ B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1);
+
+ e_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6,
+ B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1);
+
+ e_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8,
+ B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1);
+
+ e_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10,
+ B1=>fcount_11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open,
+ COUT=>cmp_le_1_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open,
+ COUT=>open);
+
+ g_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ g_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2);
+
+ g_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ g_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2);
+
+ g_cmp_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2);
+
+ g_cmp_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2);
+
+ g_cmp_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i,
+ B1=>wren_i_inv, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open,
+ COUT=>cmp_ge_d1_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open,
+ COUT=>open);
+
+ w_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci);
+
+ w_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0_3);
+
+ w_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1_3);
+
+ w_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2_3);
+
+ w_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7,
+ COUT=>co3_3);
+
+ w_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9,
+ COUT=>co4_3);
+
+ w_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>iwcount_11,
+ COUT=>co5_1);
+
+ r_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci);
+
+ r_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_4);
+
+ r_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_4);
+
+ r_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_4);
+
+ r_ctr_3: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7,
+ COUT=>co3_4);
+
+ r_ctr_4: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9,
+ COUT=>co4_4);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ r_ctr_5: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>ircount_11,
+ COUT=>co5_2);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:56:09
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=lattice_ecp5_fifo_16bit_dualport
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:56:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=32
+Width=18
+RDepth=32
+RWidth=18
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=16
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n lattice_ecp5_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32 -width 18 -rwidth 18 -reset_rel SYNC -pe -1 -pf 16
--- /dev/null
+<!DOCTYPE lattice_ecp5_fifo_16bit_dualport>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO_DC</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_16bit_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_16bit_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:56:10 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:56:10 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">lattice_ecp5_fifo_16bit_dualport</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:56:09</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClockEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">32</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDepth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">32</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RWidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>WDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp5_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32 -width 18 -rwidth 18 -reset_rel SYNC -pe -1 -pf 16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>lattice_ecp5_fifo_16bit_dualport</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32 -width 18 -rwidth 18 -reset_rel SYNC -pe -1 -pf 16 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.fdc
+
+-- Mon Jan 4 13:56:10 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity lattice_ecp5_fifo_16bit_dualport is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_ecp5_fifo_16bit_dualport;
+
+architecture Structure of lattice_ecp5_fifo_16bit_dualport is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co2: std_logic;
+ signal co1: std_logic;
+ signal wcount_5: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co2_1: std_logic;
+ signal co1_1: std_logic;
+ signal rcount_5: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_4: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_4: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal iaf_setcount_0: std_logic;
+ signal iaf_setcount_1: std_logic;
+ signal af_set_ctr_ci: std_logic;
+ signal iaf_setcount_2: std_logic;
+ signal iaf_setcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal iaf_setcount_4: std_logic;
+ signal iaf_setcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal co1_4: std_logic;
+ signal af_setcount_5: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal af_setcount_0: std_logic;
+ signal af_setcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w3: std_logic;
+ signal af_setcount_2: std_logic;
+ signal af_setcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal rcount_w4: std_logic;
+ signal af_set_cmp_clr: std_logic;
+ signal af_setcount_4: std_logic;
+ signal af_set_cmp_set: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp5_fifo_16bit_dualport.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t12: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t11: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t10: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ LUT4_15: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w4);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_5, AD2=>rcount_5, AD1=>w_gcount_r25,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"4c32")
+ port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>wptr_5, DO0=>af_set_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"8001")
+ port map (AD3=>af_setcount_5, AD2=>wcount_5, AD1=>r_gcount_w25,
+ AD0=>wptr_5, DO0=>af_set_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15),
+ DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12),
+ DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9),
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo,
+ ADA11=>scuba_vlo, ADA10=>scuba_vlo, ADA9=>scuba_vlo,
+ ADA8=>wptr_4, ADA7=>wptr_3, ADA6=>wptr_2, ADA5=>wptr_1,
+ ADA4=>wptr_0, ADA3=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>WrClock, WEA=>scuba_vhi, CSA2=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>scuba_vlo, ADB12=>scuba_vlo, ADB11=>scuba_vlo,
+ ADB10=>scuba_vlo, ADB9=>scuba_vlo, ADB8=>rptr_4,
+ ADB7=>rptr_3, ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0,
+ ADB3=>scuba_vlo, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>Q(17), DOB16=>Q(16),
+ DOB15=>Q(15), DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12),
+ DOB11=>Q(11), DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8),
+ DOB7=>Q(7), DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3),
+ DOB2=>Q(2), DOB1=>Q(1), DOB0=>Q(0));
+
+ FF_68: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_67: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_66: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_65: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_64: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_63: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_62: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_61: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_60: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_59: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_58: FD1P3DX
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_57: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_56: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_55: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_54: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_53: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_52: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_51: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_50: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_49: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_48: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_47: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_46: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_45: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_44: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_43: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_42: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_41: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_40: FD1P3DX
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_39: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_38: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_37: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_36: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_35: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_34: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_33: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_32: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_31: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_30: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_29: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_28: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_26: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_25: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_24: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_23: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_20: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_19: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_18: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_14: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_13: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_11: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_8: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_7: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_6: FD1P3BX
+ port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_0);
+
+ FF_5: FD1P3DX
+ port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_1);
+
+ FF_4: FD1P3DX
+ port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_2);
+
+ FF_3: FD1P3DX
+ port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_3);
+
+ FF_2: FD1P3BX
+ port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_4);
+
+ FF_1: FD1P3DX
+ port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_5);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci);
+
+ w_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0);
+
+ w_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1);
+
+ w_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>iwcount_5,
+ COUT=>co2);
+
+ r_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci);
+
+ r_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_1);
+
+ r_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_1);
+
+ r_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>ircount_5,
+ COUT=>co2_1);
+
+ empty_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ empty_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_2);
+
+ empty_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ empty_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_4, A1=>empty_cmp_set, B0=>wcount_r4,
+ B1=>empty_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open,
+ COUT=>empty_d_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open,
+ COUT=>open);
+
+ full_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ full_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, S1=>open,
+ COUT=>co0_3);
+
+ full_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3);
+
+ full_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_4, A1=>full_cmp_set, B0=>rcount_w4,
+ B1=>full_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open,
+ COUT=>full_d_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open,
+ COUT=>open);
+
+ af_set_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open,
+ COUT=>af_set_ctr_ci);
+
+ af_set_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_ctr_ci, S0=>iaf_setcount_0,
+ S1=>iaf_setcount_1, COUT=>co0_4);
+
+ af_set_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>iaf_setcount_2,
+ S1=>iaf_setcount_3, COUT=>co1_4);
+
+ af_set_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>iaf_setcount_4,
+ S1=>iaf_setcount_5, COUT=>co2_2);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open,
+ COUT=>co0_5);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3,
+ B0=>r_g2b_xor_cluster_0, B1=>rcount_w3, C0=>scuba_vhi,
+ C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_5,
+ S0=>open, S1=>open, COUT=>co1_5);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_4, A1=>af_set_cmp_set, B0=>rcount_w4,
+ B1=>af_set_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:37:11
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=lattice_ecp5_fifo_16x16_dualport
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:37:11
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+Depth=16
+Width=16
+RDepth=16
+RWidth=16
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=7
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n lattice_ecp5_fifo_16x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 16 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7
--- /dev/null
+<!DOCTYPE lattice_ecp5_fifo_16x16_dualport>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO_DC</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_16x16_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_16x16_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:37:13 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:37:13 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">lattice_ecp5_fifo_16x16_dualport</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:37:11</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClockEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LUT Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDepth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RWidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>WDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp5_fifo_16x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 16 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>lattice_ecp5_fifo_16x16_dualport</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_16x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 16 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.fdc
+
+-- Mon Jan 4 13:37:13 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity lattice_ecp5_fifo_16x16_dualport is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_ecp5_fifo_16x16_dualport;
+
+architecture Structure of lattice_ecp5_fifo_16x16_dualport is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal wptr_4: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal rptr_4: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2: std_logic;
+ signal co1: std_logic;
+ signal wcount_4: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_1: std_logic;
+ signal co1_1: std_logic;
+ signal rcount_4: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal iaf_setcount_0: std_logic;
+ signal iaf_setcount_1: std_logic;
+ signal af_set_ctr_ci: std_logic;
+ signal iaf_setcount_2: std_logic;
+ signal iaf_setcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal iaf_setcount_4: std_logic;
+ signal co2_2: std_logic;
+ signal co1_4: std_logic;
+ signal af_setcount_4: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcount_w0: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal af_setcount_0: std_logic;
+ signal af_setcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal af_setcount_2: std_logic;
+ signal af_setcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal af_set_cmp_clr: std_logic;
+ signal af_set_cmp_set: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_0: std_logic;
+
+ attribute GSR : string;
+ attribute MEM_INIT_FILE : string;
+ attribute MEM_LPC_FILE : string;
+ attribute COMP : string;
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "lattice_ecp5_fifo_16x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
+ attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "lattice_ecp5_fifo_16x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
+ attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "lattice_ecp5_fifo_16x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2";
+ attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "lattice_ecp5_fifo_16x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t10: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t9: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t8: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t4: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"4c32")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"8001")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_clr);
+
+ FF_73: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_72: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_71: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_70: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_69: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_68: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_67: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_66: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_65: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_64: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_63: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_62: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_61: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_60: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_59: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_58: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_57: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_56: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_55: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_54: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_53: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_52: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_51: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_50: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_49: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_48: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_47: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_46: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_45: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_44: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_43: FD1P3DX
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_42: FD1P3DX
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_41: FD1P3DX
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_40: FD1P3DX
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_39: FD1P3DX
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_38: FD1P3DX
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_37: FD1P3DX
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_36: FD1P3DX
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_35: FD1P3DX
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_34: FD1P3DX
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_33: FD1P3DX
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_32: FD1P3DX
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_31: FD1P3DX
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_30: FD1P3DX
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_29: FD1P3DX
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_28: FD1P3DX
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_24: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_23: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_14: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_13: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_11: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_8: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_7: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_6: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_5: FD1P3DX
+ port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_0);
+
+ FF_4: FD1P3BX
+ port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_1);
+
+ FF_3: FD1P3DX
+ port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_2);
+
+ FF_2: FD1P3BX
+ port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_3);
+
+ FF_1: FD1P3DX
+ port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_4);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci);
+
+ w_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0);
+
+ w_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1);
+
+ w_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>open, COUT=>co2);
+
+ r_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci);
+
+ r_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_1);
+
+ r_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_1);
+
+ r_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>open,
+ COUT=>co2_1);
+
+ empty_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ empty_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci, S0=>open,
+ S1=>open, COUT=>co0_2);
+
+ empty_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ empty_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open,
+ COUT=>empty_d_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open,
+ COUT=>open);
+
+ full_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ full_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open,
+ S1=>open, COUT=>co0_3);
+
+ full_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3);
+
+ full_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open,
+ COUT=>full_d_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open,
+ COUT=>open);
+
+ af_set_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open,
+ COUT=>af_set_ctr_ci);
+
+ af_set_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_ctr_ci, S0=>iaf_setcount_0,
+ S1=>iaf_setcount_1, COUT=>co0_4);
+
+ af_set_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>iaf_setcount_2,
+ S1=>iaf_setcount_3, COUT=>co1_4);
+
+ af_set_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>iaf_setcount_4, S1=>open,
+ COUT=>co2_2);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_5);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ fifo_pfu_0_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12,
+ DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15);
+
+ fifo_pfu_0_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8,
+ DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11);
+
+ fifo_pfu_0_2: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5,
+ DO2=>rdataout6, DO3=>rdataout7);
+
+ fifo_pfu_0_3: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1,
+ DO2=>rdataout2, DO3=>rdataout3);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:33:24
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=lattice_ecp5_fifo_18x16_dualport
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:33:24
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+Depth=16
+Width=18
+RDepth=16
+RWidth=18
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=7
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n lattice_ecp5_fifo_18x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7
--- /dev/null
+<!DOCTYPE lattice_ecp5_fifo_18x16_dualport>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO_DC</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_18x16_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_18x16_dualport.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:33:29 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:33:29 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">lattice_ecp5_fifo_18x16_dualport</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:33:24</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClockEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LUT Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDepth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RWidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>WDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp5_fifo_18x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>lattice_ecp5_fifo_18x16_dualport</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x16_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -pfu_fifo -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.fdc
+
+-- Mon Jan 4 13:33:29 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity lattice_ecp5_fifo_18x16_dualport is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_ecp5_fifo_18x16_dualport;
+
+architecture Structure of lattice_ecp5_fifo_18x16_dualport is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal wptr_4: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal rptr_4: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2: std_logic;
+ signal co1: std_logic;
+ signal wcount_4: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_1: std_logic;
+ signal co1_1: std_logic;
+ signal rcount_4: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal iaf_setcount_0: std_logic;
+ signal iaf_setcount_1: std_logic;
+ signal af_set_ctr_ci: std_logic;
+ signal iaf_setcount_2: std_logic;
+ signal iaf_setcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal iaf_setcount_4: std_logic;
+ signal co2_2: std_logic;
+ signal co1_4: std_logic;
+ signal af_setcount_4: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcount_w0: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal af_setcount_0: std_logic;
+ signal af_setcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal af_setcount_2: std_logic;
+ signal af_setcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal af_set_cmp_clr: std_logic;
+ signal af_set_cmp_set: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+ signal rdataout17: std_logic;
+ signal rdataout16: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rdataout15: std_logic;
+ signal rdataout14: std_logic;
+ signal rdataout13: std_logic;
+ signal rdataout12: std_logic;
+ signal rdataout11: std_logic;
+ signal rdataout10: std_logic;
+ signal rdataout9: std_logic;
+ signal rdataout8: std_logic;
+ signal rdataout7: std_logic;
+ signal rdataout6: std_logic;
+ signal rdataout5: std_logic;
+ signal rdataout4: std_logic;
+ signal rdataout3: std_logic;
+ signal rdataout2: std_logic;
+ signal rdataout1: std_logic;
+ signal rdataout0: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_0: std_logic;
+ signal dec0_wre3: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_0: std_logic;
+
+ attribute GSR : string;
+ attribute MEM_INIT_FILE : string;
+ attribute MEM_LPC_FILE : string;
+ attribute COMP : string;
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "lattice_ecp5_fifo_18x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
+ attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "lattice_ecp5_fifo_18x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
+ attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "lattice_ecp5_fifo_18x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2";
+ attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "lattice_ecp5_fifo_18x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3";
+ attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(16-17)";
+ attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "lattice_ecp5_fifo_18x16_dualport.lpc";
+ attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t10: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t9: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t8: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t4: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"8000")
+ port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi,
+ AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"4c32")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"8001")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_clr);
+
+ FF_75: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_74: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_73: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_72: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_71: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_70: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_69: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_68: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_67: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_66: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_65: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_64: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_63: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_62: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_61: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_60: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_59: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_58: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_57: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_56: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_55: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_54: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_53: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_52: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_51: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_50: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_49: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_48: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_47: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_46: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_45: FD1P3DX
+ port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(0));
+
+ FF_44: FD1P3DX
+ port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(1));
+
+ FF_43: FD1P3DX
+ port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(2));
+
+ FF_42: FD1P3DX
+ port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(3));
+
+ FF_41: FD1P3DX
+ port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(4));
+
+ FF_40: FD1P3DX
+ port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(5));
+
+ FF_39: FD1P3DX
+ port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(6));
+
+ FF_38: FD1P3DX
+ port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(7));
+
+ FF_37: FD1P3DX
+ port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(8));
+
+ FF_36: FD1P3DX
+ port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(9));
+
+ FF_35: FD1P3DX
+ port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(10));
+
+ FF_34: FD1P3DX
+ port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(11));
+
+ FF_33: FD1P3DX
+ port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(12));
+
+ FF_32: FD1P3DX
+ port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(13));
+
+ FF_31: FD1P3DX
+ port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(14));
+
+ FF_30: FD1P3DX
+ port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(15));
+
+ FF_29: FD1P3DX
+ port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(16));
+
+ FF_28: FD1P3DX
+ port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>Q(17));
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_24: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_23: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_14: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_13: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_11: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_8: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_7: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_6: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_5: FD1P3DX
+ port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_0);
+
+ FF_4: FD1P3BX
+ port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_1);
+
+ FF_3: FD1P3DX
+ port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_2);
+
+ FF_2: FD1P3BX
+ port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_3);
+
+ FF_1: FD1P3DX
+ port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_4);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci);
+
+ w_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0);
+
+ w_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1);
+
+ w_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>open, COUT=>co2);
+
+ r_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci);
+
+ r_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_1);
+
+ r_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_1);
+
+ r_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>open,
+ COUT=>co2_1);
+
+ empty_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ empty_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci, S0=>open,
+ S1=>open, COUT=>co0_2);
+
+ empty_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ empty_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open,
+ COUT=>empty_d_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open,
+ COUT=>open);
+
+ full_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ full_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open,
+ S1=>open, COUT=>co0_3);
+
+ full_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3);
+
+ full_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open,
+ COUT=>full_d_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open,
+ COUT=>open);
+
+ af_set_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open,
+ COUT=>af_set_ctr_ci);
+
+ af_set_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_ctr_ci, S0=>iaf_setcount_0,
+ S1=>iaf_setcount_1, COUT=>co0_4);
+
+ af_set_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>iaf_setcount_2,
+ S1=>iaf_setcount_3, COUT=>co1_4);
+
+ af_set_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>iaf_setcount_4, S1=>open,
+ COUT=>co2_2);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_5);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ fifo_pfu_0_0: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(16), DI1=>Data(17), DI2=>scuba_vhi,
+ DI3=>scuba_vhi, WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16,
+ DO1=>rdataout17, DO2=>open, DO3=>open);
+
+ fifo_pfu_0_1: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14),
+ DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12,
+ DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15);
+
+ fifo_pfu_0_2: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10),
+ DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0,
+ RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0,
+ WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8,
+ DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11);
+
+ fifo_pfu_0_3: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5,
+ DO2=>rdataout6, DO3=>rdataout7);
+
+ fifo_pfu_0_4: DPR16X4C
+ generic map (initval=> "0x0000000000000000")
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1,
+ RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1,
+ WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1,
+ DO2=>rdataout2, DO3=>rdataout3);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+Date=01/04/2016
+Time=13:35:37
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=lattice_ecp5_fifo_18x16_dualport_oreg
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=01/04/2016
+Time=13:35:37
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=16
+Width=18
+RDepth=16
+RWidth=18
+regout=1
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=7
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7
--- /dev/null
+<!DOCTYPE lattice_ecp5_fifo_18x16_dualport_oreg>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>FIFO_DC</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_18x16_dualport_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./lattice_ecp5_fifo_18x16_dualport_oreg.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.01:35:39 PM</lattice:date>
+ <lattice:modified>2016-01-04.01:35:39 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">FIFO_DC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">lattice_ecp5_fifo_18x16_dualport_oreg</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">13:35:37</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClockEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CtrlByRdEn</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Depth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EmpFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FIFOImp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">EBR Based</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FullFlg</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PeMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Dual Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfAssert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfDeassert</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">506</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PfMode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Static - Single Threshold</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RDepth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RWidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Async</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reset1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Sync</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>WDataCount</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>regout</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>lattice_ecp5_fifo_18x16_dualport_oreg</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc
+
+-- Mon Jan 4 13:35:39 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity lattice_ecp5_fifo_18x16_dualport_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end lattice_ecp5_fifo_18x16_dualport_oreg;
+
+architecture Structure of lattice_ecp5_fifo_18x16_dualport_oreg is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal co2: std_logic;
+ signal co1: std_logic;
+ signal wcount_4: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal co2_1: std_logic;
+ signal co1_1: std_logic;
+ signal rcount_4: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal iaf_setcount_0: std_logic;
+ signal iaf_setcount_1: std_logic;
+ signal af_set_ctr_ci: std_logic;
+ signal iaf_setcount_2: std_logic;
+ signal iaf_setcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal iaf_setcount_4: std_logic;
+ signal co2_2: std_logic;
+ signal co1_4: std_logic;
+ signal af_setcount_4: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcount_w0: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal af_setcount_0: std_logic;
+ signal af_setcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal af_setcount_2: std_logic;
+ signal af_setcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal af_set_cmp_clr: std_logic;
+ signal af_set_cmp_set: std_logic;
+ signal af_set: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+ signal af_set_c: std_logic;
+
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp5_fifo_18x16_dualport_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t10: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t9: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t8: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t5: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t4: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_gcount_w24,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"4c32")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"8001")
+ port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24,
+ AD0=>wptr_4, DO0=>af_set_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KD
+ generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
+ CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15),
+ DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12),
+ DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9),
+ DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5),
+ DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1),
+ DIA0=>Data(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo,
+ ADA11=>scuba_vlo, ADA10=>scuba_vlo, ADA9=>scuba_vlo,
+ ADA8=>scuba_vlo, ADA7=>wptr_3, ADA6=>wptr_2, ADA5=>wptr_1,
+ ADA4=>wptr_0, ADA3=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>wren_i, OCEA=>wren_i,
+ CLKA=>WrClock, WEA=>scuba_vhi, CSA2=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
+ DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
+ ADB13=>scuba_vlo, ADB12=>scuba_vlo, ADB11=>scuba_vlo,
+ ADB10=>scuba_vlo, ADB9=>scuba_vlo, ADB8=>scuba_vlo,
+ ADB7=>rptr_3, ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0,
+ ADB3=>scuba_vlo, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>scuba_vhi, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB0=>scuba_vlo, RSTB=>Reset, DOA17=>open, DOA16=>open,
+ DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open,
+ DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open,
+ DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open,
+ DOA1=>open, DOA0=>open, DOB17=>Q(17), DOB16=>Q(16),
+ DOB15=>Q(15), DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12),
+ DOB11=>Q(11), DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8),
+ DOB7=>Q(7), DOB6=>Q(6), DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3),
+ DOB2=>Q(2), DOB1=>Q(1), DOB0=>Q(0));
+
+ FF_57: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_56: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_55: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_54: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_53: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_52: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_51: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_50: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_49: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_48: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_47: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_46: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_45: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_44: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_43: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_42: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_41: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_40: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_39: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_38: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_37: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_36: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_35: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_34: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_33: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_32: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_31: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_30: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_29: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_28: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_24: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_23: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_14: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_13: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_11: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_10: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_8: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_7: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_6: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_5: FD1P3DX
+ port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_0);
+
+ FF_4: FD1P3BX
+ port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_1);
+
+ FF_3: FD1P3DX
+ port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_2);
+
+ FF_2: FD1P3BX
+ port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_3);
+
+ FF_1: FD1P3DX
+ port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_4);
+
+ FF_0: FD1S3DX
+ port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci);
+
+ w_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1,
+ COUT=>co0);
+
+ w_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3,
+ COUT=>co1);
+
+ w_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>open, COUT=>co2);
+
+ r_gctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci);
+
+ r_gctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1,
+ COUT=>co0_1);
+
+ r_gctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3,
+ COUT=>co1_1);
+
+ r_gctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>open,
+ COUT=>co2_1);
+
+ empty_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci);
+
+ empty_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci, S0=>open,
+ S1=>open, COUT=>co0_2);
+
+ empty_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2);
+
+ empty_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open,
+ COUT=>empty_d_c);
+
+ a0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open,
+ COUT=>open);
+
+ full_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1);
+
+ full_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open,
+ S1=>open, COUT=>co0_3);
+
+ full_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3);
+
+ full_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open,
+ COUT=>full_d_c);
+
+ a1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open,
+ COUT=>open);
+
+ af_set_ctr_cia: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open,
+ COUT=>af_set_ctr_ci);
+
+ af_set_ctr_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_ctr_ci, S0=>iaf_setcount_0,
+ S1=>iaf_setcount_1, COUT=>co0_4);
+
+ af_set_ctr_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_4, S0=>iaf_setcount_2,
+ S1=>iaf_setcount_3, COUT=>co1_4);
+
+ af_set_ctr_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>af_setcount_4, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_4, S0=>iaf_setcount_4, S1=>open,
+ COUT=>co2_2);
+
+ af_set_cmp_ci_a: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi,
+ CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2);
+
+ af_set_cmp_0: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
+ B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi,
+ D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open,
+ S1=>open, COUT=>co0_5);
+
+ af_set_cmp_1: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5);
+
+ af_set_cmp_2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA",
+ INIT0=> X"99AA")
+ port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open,
+ COUT=>af_set_c);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: CCU2C
+ generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA",
+ INIT0=> X"66AA")
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi,
+ D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open,
+ COUT=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+ generic(
+ USE_STATUS_FLAGS : integer := c_YES
+ );
+ port (
+ read_clock_in: IN std_logic;
+ write_clock_in: IN std_logic;
+ read_enable_in: IN std_logic;
+ write_enable_in: IN std_logic;
+ fifo_gsr_in: IN std_logic;
+ write_data_in: IN std_logic_vector(17 downto 0);
+ read_data_out: OUT std_logic_vector(17 downto 0);
+ full_out: OUT std_logic;
+ empty_out: OUT std_logic;
+ fifostatus_out: OUT std_logic_vector(3 downto 0);
+ valid_read_out: OUT std_logic;
+ almost_empty_out:OUT std_logic;
+ almost_full_out :OUT std_logic
+ );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+ component lattice_ecp3_fifo_16bit_dualport
+ port (Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic; RdClock: in std_logic;
+ WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic;
+ RPReset: in std_logic; Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic; Full: out std_logic; AlmostFull: out std_logic);
+ end component;
+
+ signal buf_empty_out, buf_full_out : std_logic;
+
+BEGIN
+ FIFO_DP_BRAM : lattice_ecp5_fifo_16bit_dualport
+ port map (
+ Data => write_data_in,
+ WrClock => write_clock_in,
+ RdClock => read_clock_in,
+ WrEn => write_enable_in,
+ RdEn => read_enable_in,
+ Reset => fifo_gsr_in,
+ RPReset => '0',
+ Q => read_data_out,
+ Empty => buf_empty_out,
+ Full => buf_full_out,
+ AlmostFull => almost_full_out
+ );
+empty_out <= buf_empty_out;
+full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
+fifostatus_out <= (others => '0');
+valid_read_out <= '0';
+end architecture trb_net_fifo_16bit_bram_dualport_arch;
\ No newline at end of file
--- /dev/null
+Date=01/04/2016
+Time=14:14:21
+
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM-85F-8BG381C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=01/04/2016
+ModuleName=serdes_sync_0
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=14:14:21
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=2
+CDR_MULT=10X
+CDR_REF_RATE=200.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=200.0000
+RSTSEQSEL=Disabled
+RX8B10B=Enabled
+RXCOMMAA=1100000100
+RXCOMMAB=0011111000
+RXCOMMAM=1111111100
+RXCOUPLING=DC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=200.0000
+RX_LINE_RATE=2.0000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=200.0000
+TX_LINE_RATE=2.0000
+TX_MAX_RATE=2
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_0.pp=pp
+serdes_sync_0.sym=sym
+serdes_sync_0.tft=tft
+serdes_sync_0.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH0
--- /dev/null
+<!DOCTYPE serdes_sync_0>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>PCS</spirit:name>
+ <spirit:version>8.2</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./serdes_sync_0_softlogic.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>./serdes_sync_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./serdes_sync_0_softlogic.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>./serdes_sync_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2016-01-04.02:14:28 PM</lattice:date>
+ <lattice:modified>2016-01-04.02:14:28 PM</lattice:modified>
+ <lattice:diamond>3.6.0.83.4</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements>
+ <lattice:element>
+ <lattice:name>Lane0</lattice:name>
+ <lattice:type>DCUCHANNEL</lattice:type>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+ <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+ <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+ </lattice:attributes>
+ </lattice:element>
+ </lattice:elements>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA381</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG381C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">serdes_sync_0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">14:14:21</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>;ACHARA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>;ACHARB</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>;ACHARM</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CDR_MULT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CH_MODE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO_TYPE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>LEQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>LOOPBACK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>LOSPORT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>NUM_CHS</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PROTOCOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RCSRC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RX8B10B</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1100000100</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0011111000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1111111100</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">M4-S4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXINVPOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXLDR</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXLSM</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXSC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">K28P157</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RXWA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SCIPORT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SOFTLOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX8B10B</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">800</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXDEPOST</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXDEPRE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXINVPOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXLDR</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="FilesGenerated"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>serdes_sync_0.pp</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>serdes_sync_0.sym</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>serdes_sync_0.tft</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>serdes_sync_0.txt</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups>
+ <lattice:group>
+ <lattice:name>DCUCHANNEL</lattice:name>
+ <lattice:category>1</lattice:category>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+ <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+ <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elementref>Lane0</lattice:elementref>
+ </lattice:group>
+ </lattice:groups>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>serdes_sync_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_0sll_core
+--
+
+-- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_0
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity serdes_sync_0 is
+ port (hdoutp: out std_logic;
+ hdoutn: out std_logic;
+ hdinp: in std_logic;
+ hdinn: in std_logic;
+ rxrefclk: in std_logic;
+ rx_pclk: out std_logic;
+ tx_pclk: out std_logic;
+ txdata: in std_logic_vector(7 downto 0);
+ tx_k: in std_logic_vector(0 downto 0);
+ tx_force_disp: in std_logic_vector(0 downto 0);
+ tx_disp_sel: in std_logic_vector(0 downto 0);
+ rxdata: out std_logic_vector(7 downto 0);
+ rx_k: out std_logic_vector(0 downto 0);
+ rx_disp_err: out std_logic_vector(0 downto 0);
+ rx_cv_err: out std_logic_vector(0 downto 0);
+ tx_idle_c: in std_logic;
+ signal_detect_c: in std_logic;
+ rx_los_low_s: out std_logic;
+ lsm_status_s: out std_logic;
+ rx_cdr_lol_s: out std_logic;
+ tx_pcs_rst_c: in std_logic;
+ rx_pcs_rst_c: in std_logic;
+ rx_serdes_rst_c: in std_logic;
+ tx_pwrup_c: in std_logic;
+ rx_pwrup_c: in std_logic;
+ sci_wrdata: in std_logic_vector(7 downto 0);
+ sci_addr: in std_logic_vector(5 downto 0);
+ sci_rddata: out std_logic_vector(7 downto 0);
+ sci_en_dual: in std_logic;
+ sci_sel_dual: in std_logic;
+ sci_en: in std_logic;
+ sci_sel: in std_logic;
+ sci_rd: in std_logic;
+ sci_wrn: in std_logic;
+ sci_int: out std_logic;
+ cyawstn: in std_logic;
+ rst_dual_c: in std_logic;
+ serdes_rst_dual_c: in std_logic;
+ serdes_pdb: in std_logic;
+ tx_serdes_rst_c: in std_logic;
+ pll_refclki: in std_logic;
+ sli_rst: in std_logic;
+ pll_lol: out std_logic
+ );
+
+end entity serdes_sync_0;
+
+architecture v1 of serdes_sync_0 is
+ component serdes_sync_0sll_core is
+ generic (PPROTOCOL: string := "G8B10B";
+ PLOL_SETTING: integer := 1;
+ PDYN_RATE_CTRL: string := "DISABLED";
+ PDIFF_VAL_LOCK: integer := 19;
+ PDIFF_VAL_UNLOCK: integer := 131;
+ PPCLK_TC: integer := 65536;
+ PDIFF_DIV11_VAL_LOCK: integer := 0;
+ PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+ PPCLK_DIV11_TC: integer := 0);
+ port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(73)
+ sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(74)
+ sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(75)
+ sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(76)
+ sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(77)
+ sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(78)
+ slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(81)
+ );
+
+ end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(57)
+ signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
+ n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,
+ n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
+ n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51,
+ n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
+ n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
+ n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
+ n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,\_Z\,n108,
+ n107,gnd,pwr : std_logic;
+ attribute LOC : string;
+ attribute LOC of DCU0_inst : label is "DCU0";
+ attribute CHAN : string;
+ attribute CHAN of DCU0_inst : label is "CH0";
+begin
+ rx_pclk <= rx_pclk_c;
+ tx_pclk <= tx_pclk_c;
+ DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+ D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+ D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+ D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+ D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
+ CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
+ CH0_GE_AN_ENABLE=>"0b0",CH0_PRBS_LOCK=>"0b0",CH0_PRBS_ENABLE=>"0b0",
+ CH0_ENABLE_CG_ALIGN=>"0b1",CH0_TX_GEAR_MODE=>"0b0",CH0_RX_GEAR_MODE=>"0b0",
+ CH0_PCS_DET_TIME_SEL=>"0b00",CH0_PCIE_EI_EN=>"0b0",CH0_TX_GEAR_BYPASS=>"0b0",
+ CH0_ENC_BYPASS=>"0b0",CH0_SB_BYPASS=>"0b0",CH0_RX_SB_BYPASS=>"0b0",
+ CH0_WA_BYPASS=>"0b0",CH0_DEC_BYPASS=>"0b0",CH0_CTC_BYPASS=>"0b1",
+ CH0_RX_GEAR_BYPASS=>"0b0",CH0_LSM_DISABLE=>"0b0",CH0_MATCH_2_ENABLE=>"0b0",
+ CH0_MATCH_4_ENABLE=>"0b1",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x1BC",
+ CH0_CC_MATCH_2=>"0x11C",CH0_CC_MATCH_3=>"0x11C",CH0_CC_MATCH_4=>"0x11C",
+ CH0_UDF_COMMA_MASK=>"0x0ff",CH0_UDF_COMMA_A=>"0x083",CH0_UDF_COMMA_B=>"0x07C",
+ CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b1",CH0_TPWDNB=>"0b1",
+ CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
+ CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b00",CH0_TDRV_SLICE1_SEL=>"0b00",
+ CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",
+ CH0_TDRV_SLICE5_SEL=>"0b00",CH0_TDRV_SLICE0_CUR=>"0b000",CH0_TDRV_SLICE1_CUR=>"0b000",
+ CH0_TDRV_SLICE2_CUR=>"0b11",CH0_TDRV_SLICE3_CUR=>"0b11",CH0_TDRV_SLICE4_CUR=>"0b01",
+ CH0_TDRV_SLICE5_CUR=>"0b00",CH0_TDRV_DAT_SEL=>"0b00",CH0_TX_DIV11_SEL=>"0b0",
+ CH0_RPWDNB=>"0b1",CH0_RATE_MODE_RX=>"0b0",CH0_RX_DIV11_SEL=>"0b0",
+ CH0_SEL_SD_RX_CLK=>"0b1",CH0_FF_RX_H_CLK_EN=>"0b0",CH0_FF_RX_F_CLK_DIS=>"0b0",
+ CH0_FF_TX_H_CLK_EN=>"0b0",CH0_FF_TX_F_CLK_DIS=>"0b0",CH0_TDRV_POST_EN=>"0b0",
+ CH0_TX_POST_SIGN=>"0b0",CH0_TX_PRE_SIGN=>"0b0",CH0_REQ_LVL_SET=>"0b00",
+ CH0_REQ_EN=>"0b1",CH0_RTERM_RX=>"0d22",CH0_RXTERM_CM=>"0b11",CH0_PDEN_SEL=>"0b0",
+ CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
+ CH0_RLOS_SEL=>"0b0",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
+ CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
+ CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2",
+ CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
+ CH0_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01",
+ D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001",
+ D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH0_CDR_CNT4SEL=>"0b00",
+ CH0_CDR_CNT8SEL=>"0b00",CH0_DCOATDCFG=>"0b00",CH0_DCOATDDLY=>"0b00",
+ CH0_DCOBYPSATD=>"0b1",CH0_DCOCALDIV=>"0b000",CH0_DCOCTLGI=>"0b011",
+ CH0_DCODISBDAVOID=>"0b0",CH0_DCOFLTDAC=>"0b00",CH0_DCOFTNRG=>"0b001",
+ CH0_DCOIOSTUNE=>"0b010",CH0_DCOITUNE=>"0b00",CH0_DCOITUNE4LSB=>"0b010",
+ CH0_DCOIUPDNX2=>"0b1",CH0_DCONUOFLSB=>"0b100",CH0_DCOSCALEI=>"0b01",
+ CH0_DCOSTARTVAL=>"0b010",CH0_DCOSTEP=>"0b11",CH0_BAND_THRESHOLD=>"0d0",
+ CH0_AUTO_FACQ_EN=>"0b1",CH0_AUTO_CALIB_EN=>"0b1",CH0_CALIB_CK_MODE=>"0b0",
+ CH0_REG_BAND_OFFSET=>"0d0",CH0_REG_BAND_SEL=>"0d0",CH0_REG_IDAC_SEL=>"0d0",
+ CH0_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+ D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+ D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+ D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10",
+ D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01",
+ D_RG_EN=>"0b1",D_RG_SET=>"0b00")
+ port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106,
+ D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
+ CH0_RX_REFCLK=>rxrefclk,CH1_RX_REFCLK=>n106,CH0_FF_RXI_CLK=>rx_pclk_c,
+ CH1_FF_RXI_CLK=>n105,CH0_FF_TXI_CLK=>tx_pclk_c,CH1_FF_TXI_CLK=>n105,CH0_FF_EBRD_CLK=>n48,
+ CH1_FF_EBRD_CLK=>n105,CH0_FF_TX_D_0=>txdata(0),CH1_FF_TX_D_0=>n106,CH0_FF_TX_D_1=>txdata(1),
+ CH1_FF_TX_D_1=>n106,CH0_FF_TX_D_2=>txdata(2),CH1_FF_TX_D_2=>n106,CH0_FF_TX_D_3=>txdata(3),
+ CH1_FF_TX_D_3=>n106,CH0_FF_TX_D_4=>txdata(4),CH1_FF_TX_D_4=>n106,CH0_FF_TX_D_5=>txdata(5),
+ CH1_FF_TX_D_5=>n106,CH0_FF_TX_D_6=>txdata(6),CH1_FF_TX_D_6=>n106,CH0_FF_TX_D_7=>txdata(7),
+ CH1_FF_TX_D_7=>n106,CH0_FF_TX_D_8=>tx_k(0),CH1_FF_TX_D_8=>n106,CH0_FF_TX_D_9=>tx_force_disp(0),
+ CH1_FF_TX_D_9=>n106,CH0_FF_TX_D_10=>tx_disp_sel(0),CH1_FF_TX_D_10=>n106,
+ CH0_FF_TX_D_11=>n47,CH1_FF_TX_D_11=>n106,CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,
+ CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,
+ CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,
+ CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,
+ CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,
+ CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,
+ CH0_FF_TX_D_23=>n47,CH1_FF_TX_D_23=>n106,CH0_FFC_EI_EN=>tx_idle_c,CH1_FFC_EI_EN=>n106,
+ CH0_FFC_PCIE_DET_EN=>n47,CH1_FFC_PCIE_DET_EN=>n106,CH0_FFC_PCIE_CT=>n47,
+ CH1_FFC_PCIE_CT=>n106,CH0_FFC_SB_INV_RX=>n106,CH1_FFC_SB_INV_RX=>n106,
+ CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,CH0_FFC_SIGNAL_DETECT=>signal_detect_c,
+ CH1_FFC_SIGNAL_DETECT=>n106,CH0_FFC_FB_LOOPBACK=>n47,CH1_FFC_FB_LOOPBACK=>n106,
+ CH0_FFC_SB_PFIFO_LP=>n47,CH1_FFC_SB_PFIFO_LP=>n106,CH0_FFC_PFIFO_CLR=>n47,
+ CH1_FFC_PFIFO_CLR=>n106,CH0_FFC_RATE_MODE_RX=>n106,CH1_FFC_RATE_MODE_RX=>n106,
+ CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,CH0_FFC_DIV11_MODE_RX=>n47,
+ CH1_FFC_DIV11_MODE_RX=>n106,CH0_FFC_DIV11_MODE_TX=>n47,CH1_FFC_DIV11_MODE_TX=>n106,
+ CH0_FFC_RX_GEAR_MODE=>n47,CH1_FFC_RX_GEAR_MODE=>n106,CH0_FFC_TX_GEAR_MODE=>n47,
+ CH1_FFC_TX_GEAR_MODE=>n106,CH0_FFC_LDR_CORE2TX_EN=>n106,CH1_FFC_LDR_CORE2TX_EN=>n106,
+ CH0_FFC_LANE_TX_RST=>tx_pcs_rst_c,CH1_FFC_LANE_TX_RST=>n106,CH0_FFC_LANE_RX_RST=>rx_pcs_rst_c,
+ CH1_FFC_LANE_RX_RST=>n106,CH0_FFC_RRST=>rx_serdes_rst_c,CH1_FFC_RRST=>n106,
+ CH0_FFC_TXPWDNB=>tx_pwrup_c,CH1_FFC_TXPWDNB=>n106,CH0_FFC_RXPWDNB=>rx_pwrup_c,
+ CH1_FFC_RXPWDNB=>n106,CH0_LDR_CORE2TX=>n106,CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),
+ D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),
+ D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),
+ D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),
+ D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),
+ D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,
+ CH0_SCIEN=>sci_en,CH1_SCIEN=>n106,CH0_SCISEL=>sci_sel,CH1_SCISEL=>n106,
+ D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,
+ D_FFC_DUAL_RST=>rst_dual_c,D_FFC_MACRO_RST=>serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,
+ D_FFC_TRST=>tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n47,CH1_FFC_CDR_EN_BITSLIP=>n106,
+ D_SCAN_ENABLE=>n47,D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,
+ D_SCAN_IN_3=>n47,D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,
+ D_SCAN_IN_7=>n47,D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,
+ D_CIN2=>n47,D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,
+ D_CIN8=>n47,D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>hdoutp,
+ CH1_HDOUTP=>n50,CH0_HDOUTN=>hdoutn,CH1_HDOUTN=>n51,D_TXBIT_CLKP_TO_ND=>n1,
+ D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n5,
+ CH1_FF_RX_F_CLK=>n52,CH0_FF_RX_H_CLK=>n6,CH1_FF_RX_H_CLK=>n53,CH0_FF_TX_F_CLK=>n7,
+ CH1_FF_TX_F_CLK=>n54,CH0_FF_TX_H_CLK=>n8,CH1_FF_TX_H_CLK=>n55,CH0_FF_RX_PCLK=>rx_pclk_c,
+ CH1_FF_RX_PCLK=>n56,CH0_FF_TX_PCLK=>tx_pclk_c,CH1_FF_TX_PCLK=>n57,CH0_FF_RX_D_0=>rxdata(0),
+ CH1_FF_RX_D_0=>n58,CH0_FF_RX_D_1=>rxdata(1),CH1_FF_RX_D_1=>n59,CH0_FF_RX_D_2=>rxdata(2),
+ CH1_FF_RX_D_2=>n60,CH0_FF_RX_D_3=>rxdata(3),CH1_FF_RX_D_3=>n61,CH0_FF_RX_D_4=>rxdata(4),
+ CH1_FF_RX_D_4=>n62,CH0_FF_RX_D_5=>rxdata(5),CH1_FF_RX_D_5=>n63,CH0_FF_RX_D_6=>rxdata(6),
+ CH1_FF_RX_D_6=>n64,CH0_FF_RX_D_7=>rxdata(7),CH1_FF_RX_D_7=>n65,CH0_FF_RX_D_8=>rx_k(0),
+ CH1_FF_RX_D_8=>n66,CH0_FF_RX_D_9=>rx_disp_err(0),CH1_FF_RX_D_9=>n67,CH0_FF_RX_D_10=>rx_cv_err(0),
+ CH1_FF_RX_D_10=>n68,CH0_FF_RX_D_11=>n9,CH1_FF_RX_D_11=>n69,CH0_FF_RX_D_12=>n70,
+ CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,
+ CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,
+ CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,
+ CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,
+ CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,
+ CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n10,CH1_FF_RX_D_23=>n92,CH0_FFS_PCIE_DONE=>n11,
+ CH1_FFS_PCIE_DONE=>n93,CH0_FFS_PCIE_CON=>n12,CH1_FFS_PCIE_CON=>n94,CH0_FFS_RLOS=>rx_los_low_s,
+ CH1_FFS_RLOS=>n95,CH0_FFS_LS_SYNC_STATUS=>lsm_status_s,CH1_FFS_LS_SYNC_STATUS=>n96,
+ CH0_FFS_CC_UNDERRUN=>n13,CH1_FFS_CC_UNDERRUN=>n97,CH0_FFS_CC_OVERRUN=>n14,
+ CH1_FFS_CC_OVERRUN=>n98,CH0_FFS_RXFBFIFO_ERROR=>n15,CH1_FFS_RXFBFIFO_ERROR=>n99,
+ CH0_FFS_TXFBFIFO_ERROR=>n16,CH1_FFS_TXFBFIFO_ERROR=>n100,CH0_FFS_RLOL=>rx_cdr_lol_s,
+ CH1_FFS_RLOL=>n101,CH0_FFS_SKP_ADDED=>n17,CH1_FFS_SKP_ADDED=>n102,CH0_FFS_SKP_DELETED=>n18,
+ CH1_FFS_SKP_DELETED=>n103,CH0_LDR_RX2CORE=>n104,CH1_LDR_RX2CORE=>\_Z\,
+ D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),
+ D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),
+ D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,
+ D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,D_SCAN_OUT_3=>n22,
+ D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,D_SCAN_OUT_7=>n26,
+ D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,D_COUT4=>n31,D_COUT5=>n32,
+ D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,D_COUT10=>n37,D_COUT11=>n38,
+ D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,D_COUT15=>n42,D_COUT16=>n43,
+ D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
+ n48 <= '1' ;
+ n47 <= '0' ;
+ n1 <= 'Z' ;
+ n2 <= 'Z' ;
+ n3 <= 'Z' ;
+ n4 <= 'Z' ;
+ n5 <= 'Z' ;
+ n6 <= 'Z' ;
+ n7 <= 'Z' ;
+ n8 <= 'Z' ;
+ n9 <= 'Z' ;
+ n10 <= 'Z' ;
+ n11 <= 'Z' ;
+ n12 <= 'Z' ;
+ n13 <= 'Z' ;
+ n14 <= 'Z' ;
+ n15 <= 'Z' ;
+ n16 <= 'Z' ;
+ n17 <= 'Z' ;
+ n18 <= 'Z' ;
+ n19 <= 'Z' ;
+ n20 <= 'Z' ;
+ n21 <= 'Z' ;
+ n22 <= 'Z' ;
+ n23 <= 'Z' ;
+ n24 <= 'Z' ;
+ n25 <= 'Z' ;
+ n26 <= 'Z' ;
+ n27 <= 'Z' ;
+ n28 <= 'Z' ;
+ n29 <= 'Z' ;
+ n30 <= 'Z' ;
+ n31 <= 'Z' ;
+ n32 <= 'Z' ;
+ n33 <= 'Z' ;
+ n34 <= 'Z' ;
+ n35 <= 'Z' ;
+ n36 <= 'Z' ;
+ n37 <= 'Z' ;
+ n38 <= 'Z' ;
+ n39 <= 'Z' ;
+ n40 <= 'Z' ;
+ n41 <= 'Z' ;
+ n42 <= 'Z' ;
+ n43 <= 'Z' ;
+ n44 <= 'Z' ;
+ n45 <= 'Z' ;
+ n46 <= 'Z' ;
+ n49 <= 'Z' ;
+ n106 <= '0' ;
+ n105 <= '1' ;
+ n50 <= 'Z' ;
+ n51 <= 'Z' ;
+ n52 <= 'Z' ;
+ n53 <= 'Z' ;
+ n54 <= 'Z' ;
+ n55 <= 'Z' ;
+ n56 <= 'Z' ;
+ n57 <= 'Z' ;
+ n58 <= 'Z' ;
+ n59 <= 'Z' ;
+ n60 <= 'Z' ;
+ n61 <= 'Z' ;
+ n62 <= 'Z' ;
+ n63 <= 'Z' ;
+ n64 <= 'Z' ;
+ n65 <= 'Z' ;
+ n66 <= 'Z' ;
+ n67 <= 'Z' ;
+ n68 <= 'Z' ;
+ n69 <= 'Z' ;
+ n70 <= 'Z' ;
+ n71 <= 'Z' ;
+ n72 <= 'Z' ;
+ n73 <= 'Z' ;
+ n74 <= 'Z' ;
+ n75 <= 'Z' ;
+ n76 <= 'Z' ;
+ n77 <= 'Z' ;
+ n78 <= 'Z' ;
+ n79 <= 'Z' ;
+ n80 <= 'Z' ;
+ n81 <= 'Z' ;
+ n82 <= 'Z' ;
+ n83 <= 'Z' ;
+ n84 <= 'Z' ;
+ n85 <= 'Z' ;
+ n86 <= 'Z' ;
+ n87 <= 'Z' ;
+ n88 <= 'Z' ;
+ n89 <= 'Z' ;
+ n90 <= 'Z' ;
+ n91 <= 'Z' ;
+ n92 <= 'Z' ;
+ n93 <= 'Z' ;
+ n94 <= 'Z' ;
+ n95 <= 'Z' ;
+ n96 <= 'Z' ;
+ n97 <= 'Z' ;
+ n98 <= 'Z' ;
+ n99 <= 'Z' ;
+ n100 <= 'Z' ;
+ n101 <= 'Z' ;
+ n102 <= 'Z' ;
+ n103 <= 'Z' ;
+ n104 <= 'Z' ;
+ \_Z\ <= 'Z' ;
+ sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+ sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+ slo_plol=>pll_lol);
+ n108 <= '1' ;
+ n107 <= '0' ;
+ gnd <= '0' ;
+ pwr <= '1' ;
+
+end architecture v1;
+
--- /dev/null
+
+// ===========================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+// ---------------------------------------------------------------------------
+// Copyright (c) 2015 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// Permission:
+//
+// Lattice SG Pte. Ltd. grants permission to use this code
+// pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+// Disclaimer:
+//
+// This VHDL or Verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Lattice provides no warranty
+// regarding the use or functionality of this code.
+//
+// ---------------------------------------------------------------------------
+//
+// Lattice SG Pte. Ltd.
+// 101 Thomson Road, United Square #07-02
+// Singapore 307591
+//
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// +65-6631-2000 (Singapore)
+// +1-503-268-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// ---------------------------------------------------------------------------
+//
+// =============================================================================
+// FILE DETAILS
+// Project : SLL - Soft Loss Of Lock(LOL) Logic
+// File : sll_core.v
+// Title : Top-level file for SLL
+// Dependencies : 1.
+// : 2.
+// Description :
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.0
+// Author(s) : AV
+// Mod. Date : March 2, 2015
+// Changes Made : Initial Creation
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.1
+// Author(s) : AV
+// Mod. Date : June 8, 2015
+// Changes Made : Following updates were made
+// 1. Changed all the PLOL status logic and FSM to run
+// on sli_refclk.
+// 2. Added the HB logic for presence of tx_pclk
+// 3. Changed the lparam assignment scheme for
+// simulation purposes.
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.2
+// Author(s) : AV
+// Mod. Date : June 24, 2015
+// Changes Made : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+
+
+`timescale 1ns/10ps
+
+module serdes_sync_0sll_core (
+ //Reset and Clock inputs
+ sli_rst, //Active high asynchronous reset input
+ sli_refclk, //Refclk input to the Tx PLL
+ sli_pclk, //Tx pclk output from the PCS
+
+ //Control inputs
+ sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate
+ sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+ sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+
+ //LOL Output
+ slo_plol //Tx PLL Loss of Lock output to the user logic
+ );
+
+// Inputs
+input sli_rst;
+input sli_refclk;
+input sli_pclk;
+input sli_div2_rate;
+input sli_div11_rate;
+input sli_gear_mode;
+
+// Outputs
+output slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL = "PCIE"; //Protocol selected by the User
+parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control
+parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock
+parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state
+localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state
+localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state
+localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state
+localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk
+localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse
+
+// Input and Output reg and wire declarations
+wire sli_rst;
+wire sli_refclk;
+wire sli_pclk;
+wire sli_div2_rate;
+wire sli_div11_rate;
+wire sli_gear_mode;
+wire slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg [15:0] rcount; //16-bit Counter
+reg rtc_pul; //Terminal count pulse
+reg rtc_pul_p1; //Terminal count pulse pipeline
+reg rtc_ctrl; //Terminal count pulse control
+
+
+reg [7:0] rhb_wait_cnt; //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+reg rhb_sync;
+reg rhb_sync_p2;
+reg rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+reg rgear_p1;
+reg rdiv2_p1;
+reg rdiv11_p1;
+
+reg rstat_pclk; //Pclk presence/absence status
+
+reg [21:0] rcount_tc; //Tx_pclk terminal count register
+reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock
+reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+reg [1:0] sll_state; //Current-state register for LOL FSM
+
+reg pll_lock; //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+reg ppul_sync;
+reg ppul_sync_p1;
+reg ppul_sync_p2;
+reg ppul_sync_p3;
+
+reg [21:0] pcount; //22-bit counter
+reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg [2:0] phb_cnt;
+reg phb;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount <= 16'd0;
+ rtc_pul <= 1'b0;
+ rtc_ctrl <= 1'b0;
+ rtc_pul_p1 <= 1'b0;
+ end
+ else begin
+ //Counter logic
+ if (rcount != LRCLK_TC_w) begin
+ rcount <= rcount + 1;
+ end
+ else begin
+ rcount <= 16'd0;
+ end
+
+ //Pulse control logic
+ if (rcount == LRCLK_TC_w - 1) begin
+ rtc_ctrl <= 1'b1;
+ end
+
+ //Pulse Generation logic
+ if (rtc_ctrl == 1'b1) begin
+ if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+ rtc_pul <= 1'b1;
+ end
+ else begin
+ rtc_pul <= 1'b0;
+ end
+ end
+
+ rtc_pul_p1 <= rtc_pul;
+ end
+end
+
+
+// =============================================================================
+// Heartbeat synchronization and monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rhb_sync <= 1'b0;
+ rhb_sync_p1 <= 1'b0;
+ rhb_sync_p2 <= 1'b0;
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b0;
+ rgear_p1 <= 1'b0;
+ rdiv2_p1 <= 1'b0;
+ rdiv11_p1 <= 1'b0;
+ end
+ else begin
+ //Synchronization logic
+ rhb_sync <= phb;
+ rhb_sync_p1 <= rhb_sync;
+ rhb_sync_p2 <= rhb_sync_p1;
+
+ //Pipeline stages of the Dynamic rate control signals
+ rgear_p1 <= sli_gear_mode;
+ rdiv2_p1 <= sli_div2_rate;
+ rdiv11_p1 <= sli_div11_rate;
+
+ //Heartbeat wait counter and monitor logic
+ if (rtc_ctrl == 1'b1) begin
+ if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b1;
+ end
+ else if (rhb_wait_cnt == 8'd255) begin
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b0;
+ end
+ else begin
+ rhb_wait_cnt <= rhb_wait_cnt + 1;
+ end
+ end
+ end
+end
+
+
+// =============================================================================
+// Synchronizing terminal count pulse to sli_pclk domain
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ ppul_sync <= 1'b0;
+ ppul_sync_p1 <= 1'b0;
+ ppul_sync_p2 <= 1'b0;
+ ppul_sync_p3 <= 1'b0;
+ end
+ else begin
+ ppul_sync <= rtc_pul;
+ ppul_sync_p1 <= ppul_sync;
+ ppul_sync_p2 <= ppul_sync_p1;
+ ppul_sync_p3 <= ppul_sync_p2;
+ end
+end
+
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ //Div by 11 is enabled
+ if (sli_div11_rate == 1'b1) begin
+ //Gear mode is 16/20
+ if (sli_gear_mode == 1'b1) begin
+ rcount_tc <= PPCLK_DIV11_TC;
+ rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+ end
+ else begin
+ rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0};
+ rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+ rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+ end
+ end
+ //Div by 2 is enabled
+ else if (sli_div2_rate == 1'b1) begin
+ //Gear mode is 16/20
+ if (sli_gear_mode == 1'b1) begin
+ rcount_tc <= {1'b0,PPCLK_TC[21:1]};
+ rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+ rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+ end
+ else begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ end
+ //Both div by 11 and div by 2 are disabled
+ else begin
+ //Gear mode is 16/20
+ if (sli_gear_mode == 1'b1) begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ else begin
+ rcount_tc <= {PPCLK_TC[20:0],1'b0};
+ rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0};
+ rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+ end
+ end
+ end
+end
+end
+endgenerate
+
+//For CPRI or G8B10B protocols with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "CPRI" || PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ //Div by 2 is enabled
+ if (sli_div2_rate == 1'b1) begin
+ rcount_tc <= {1'b0,PPCLK_TC[21:1]};
+ rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+ rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+ end
+ else begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ end
+end
+end
+endgenerate
+
+
+//For all protocols where Dynamic rate control is disabled
+generate
+if (PDYN_RATE_CTRL == "DISABLED") begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ pcount <= 22'd0;
+ pcount_diff <= 22'd65535;
+ phb_cnt <= 3'd0;
+ phb <= 1'b0;
+ end
+ else begin
+ //Counter logic
+ if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+ pcount <= 22'd0;
+ end
+ else begin
+ pcount <= pcount + 1;
+ end
+
+ //Heartbeat logic
+ phb_cnt <= phb_cnt + 1;
+
+ if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+ phb <= 1'b1;
+ end
+ else begin
+ phb <= 1'b0;
+ end
+
+ //Differential value logic
+ if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+ pcount_diff <= rcount_tc + ~(pcount) + 1;
+ end
+ else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+ if (pcount_diff[21] == 1'b1) begin
+ pcount_diff <= ~(pcount_diff) + 1;
+ end
+ end
+ end
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ if ((rstat_pclk == 1'b0) || (rgear_p1^sli_gear_mode == 1'b1) || (rdiv2_p1^sli_div2_rate == 1'b1) || (rdiv11_p1^sli_div11_rate == 1'b1)) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ case(sll_state)
+ LPLL_LOSS_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (pcount_diff[15:0] > rdiff_comp_unlock) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else if (pcount_diff[15:0] <= rdiff_comp_lock) begin
+ if (PLOL_SETTING == 2'd0) begin
+ sll_state <= LPLL_PRELOCK_ST;
+ end
+ else begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ end
+ end
+ end
+
+
+ LPLL_LOCK_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (pcount_diff[15:0] <= rdiff_comp_lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ else begin
+ if (PLOL_SETTING == 2'd0) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ end
+ end
+ end
+
+
+ LPLL_PRELOCK_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (pcount_diff[15:0] <= rdiff_comp_lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ else begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ end
+ end
+
+
+ LPLL_PRELOSS_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (pcount_diff[15:0] > rdiff_comp_unlock) begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ else if (pcount_diff[15:0] <= rdiff_comp_lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ end
+ end
+
+ default: begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ endcase
+ end
+ end
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ pll_lock <= 1'b0;
+ end
+ else begin
+ case(sll_state)
+ LPLL_LOSS_ST : begin
+ pll_lock <= 1'b0;
+ end
+
+ LPLL_LOCK_ST : begin
+ pll_lock <= 1'b1;
+ end
+
+ LPLL_PRELOSS_ST : begin
+ pll_lock <= 1'b0;
+ end
+
+ default: begin
+ pll_lock <= 1'b0;
+ end
+ endcase
+ end
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule
+
-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8);
-- STAT_DEBUG(7) <= '0';
-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0);
-STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
+-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
+STAT_DEBUG(15 downto 0) <= debug_rx_control_i(15 downto 0);
end architecture;
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