register fsm_wr_debug for better timing

diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd
index 3b3a4904c7f52fc74f7b8880a3282dd87f65ea19..0d9858bfa2ee585bb5ab7e5ca3504be332dbed5f 100644 (file)
--- a/releases/tdc_v2.3/Channel_200.vhd
+++ b/releases/tdc_v2.3/Channel_200.vhd
@@ -462,10 +462,12 @@ begin  -- Channel_200
       write_stop_a    <= write_stop_a_fsm;
       write_stop_b    <= write_stop_b_fsm;
       write_data_flag <= write_data_flag_fsm;
-      fsm_wr_debug    <= fsm_wr_debug_fsm;
     end if;
   end process FSM_CLK;
 
+  fsm_wr_debug    <= fsm_wr_debug_fsm when rising_edge(CLK_100);
+
+  
   FSM_PROC : process (FSM_WR_CURRENT, encoder_finished, epoch_cntr_updated, trg_win_end_tdc,
                       trg_win_end_tdc_flag, write_data_flag)
   begin