Starting with a frame generator for soda.

diff --git a/mupix/MupixSoda/compile_GSI.pl b/mupix/MupixSoda/compile_GSI.pl
new file mode 100755 (executable)
index 0000000..19f11cf
--- /dev/null
+++ b/mupix/MupixSoda/compile_GSI.pl
@@ -0,0 +1,260 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+use FileHandle;
+use Getopt::Long;
+use Term::ANSIColor qw(:constants);
+use Cwd;
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
+my $lattice_path                 = '/opt/lattice/diamond/3.6_x64/';
+my $lattice_bin_path             = "$lattice_path/bin/lin64";
+my $synplify_path                = '/opt/synplicity/K-2015.09';
+my $lm_license_file_for_synplify = "27000\@lxcad03.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+my $synplify_locale_workaround   = "C";
+my $cwd                          = getcwd();
+###################################################################################
+
+
+my $all  = 1;
+my $syn  = 0;
+my $map  = 0;
+my $timing = 0;
+my $bitgen = 0;
+my $pargen = 0;
+my $help = "";
+my $result = GetOptions ("h|help"       => \$help,
+                        "a|all"        => \$all,
+                        "s|syn"        => \$syn,
+                        "m|map"        => \$map,
+                         "t|tim"        => \$timing,
+                         "b|bit"        => \$bitgen,
+                         "p|par"        => \$pargen);
+
+
+if ($help) {
+  print "Usage: compile_priph_gsi.de <OPTIONS>\n\n";
+  print "-h  --help\tPrints the usage manual.\n";
+  print "-a  --all\tRun all compile script. By default the script is going to run the whole process.\n";
+  print "-s  --syn\tRun synthesis part of the compile script.\n";
+  print "-m  --map\tRun mapping part of the compile script.\n";
+  print "-p  --par\tRun place and route.\n";
+  print "-t  --tim\tCreate timing reports.\n";
+  print "-b  --bit\tCreate bitfile.\n";
+  print "\n";
+  exit;
+}
+
+if ($syn != 0 || $map != 0 || $timing != 0 || $bitgen != 0 || $pargen != 0) {
+    $all=0;
+}
+
+# source the standard lattice environment
+$ENV{bindir}="$lattice_bin_path";
+open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env ; env'|" or
+  die "Can't fork: $!";
+while (<$SOURCE>) {
+  if (/^(.*)=(.*)/) {
+    $ENV{$1} = ${2} ;
+  }
+}
+close $SOURCE;
+
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'LC_ALL'}=$synplify_locale_workaround;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+my $WORKDIR = "workdir";
+unless(-d $WORKDIR) {
+    mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
+}
+system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
+print GREEN, "Compiling $TOPNAME project in $cwd/$WORKDIR...\n\n", RESET;
+
+print GREEN, "Generating constraints file...\n\n", RESET;
+#create full lpf file
+system("cp ../../base/$TOPNAME"."_mupixsoda.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+my $c = "";
+my @a = ();
+
+chdir "workdir";
+if($syn == 1 || $all == 1){
+    print GREEN, "Starting synthesis process...\n\n", RESET;
+    $c="$synplify_path/bin/synplify_premier_dp -batch ../$TOPNAME.prj";
+    $r=execute($c, "do_not_exit" );
+
+
+    $fh = new FileHandle("<$TOPNAME".".srr");
+    @a = <$fh>;
+    $fh -> close;
+
+    foreach (@a){
+        if(/\@E:/){
+            print "\n";
+            $c="cat $TOPNAME.srr | egrep --color \"\@E:\"";
+            system($c);
+            print "\n\n";
+            print RED, "ERROR in the log file $TOPNAME.srr Exiting...\n\n", RESET;
+            exit 129;
+        }
+    }
+}
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+if($map == 1 || $all == 1){
+    print GREEN, "Starting mapping process...\n\n", RESET;
+    
+    $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+    execute($c);
+
+    $c=qq| edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+    execute($c);
+
+    $c=qq| ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+    execute($c);
+
+    my $tpmap = $TOPNAME . "_map" ;
+
+    $c=qq| map  -hier -td_pack -retime EFFORT=6 -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+    execute($c);
+
+    $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|;
+    execute($c);
+
+    $fh = new FileHandle("<$TOPNAME"."_mrp.html");
+    @a = <$fh>;
+    $fh -> close;
+    my $i=1;
+    my $print=0;
+    foreach (@a) {
+       if (/WARNING/|$print) {
+           if ((grep /WARNING - map: There are semantic errors in the preference file/, $_) & ($i == 1)) {
+               last;
+           } 
+           elsif (grep /WARNING - map: There are semantic errors in the preference file/, $_) {
+               print RED, "There are errors in the constraints file. Better have a look...\n\n", RESET;
+               sleep(5);               # ERROR -> sleep is effective before the print
+               last;
+           } 
+           elsif ($i == 1) {
+               print RED,"\n\n", RESET;
+               print RED,"#################################################\n", RESET;
+               print RED,"CONSTRAINTS ERRORS\n", RESET;
+               print RED,"#################################################\n\n", RESET;
+           }
+           $print=1;
+           if (grep /WARNING.*UGROUP/, $_) {
+               print RED, $_, RESET;
+           } elsif (grep /FC|hitBuf|ff_en/, $_) {
+               print YELLOW, $_, RESET;
+           } else {
+               print $_;
+           }
+           $i++;
+       }
+    }
+}
+
+if($pargen == 1 || $all == 1){
+    print GREEN, "Starting placement and route process...\n\n", RESET;
+    system("rm $TOPNAME.ncd");
+
+    # dont forget to create a nodelist.txt for multipar / mpartrce
+    my $tpmap = $TOPNAME . "_map" ;
+    $c=qq|mpartrce -p "../$TOPNAME.p2t" -f "../$TOPNAME.p3t" -tf "$TOPNAME.pt" "$tpmap.ncd" "$TOPNAME.ncd"|;
+    execute($c);
+    #my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd";
+    system($c);
+}
+
+if($timing == 1 || $all == 1){
+    print GREEN, "Running timing analysis \n\n", RESET;
+    
+    # TWR Timing Report
+    $c=qq| trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+    execute($c);
+
+    $c=qq| trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+    execute($c);
+
+    # IOR IO Timing Report
+    $c=qq| iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+    execute($c);
+    
+    $c=qq| ltxt2ptxt $TOPNAME.ncd|;
+    execute($c);
+}
+
+if($bitgen == 1 || $all == 1){
+    print GREEN, "Creating Bit File \n\n", RESET;
+    $c=qq| bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+    execute($c);
+}
+
+$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|;
+execute($c);
+
+chdir "..";
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+       print "$!";
+       if($op ne "do_not_exit") {
+           exit;
+       }
+    }
+
+    return $r;
+
+}

diff --git a/mupix/MupixSoda/config.vhd b/mupix/MupixSoda/config.vhd
new file mode 100644 (file)
index 0000000..1108620
--- /dev/null
+++ b/mupix/MupixSoda/config.vhd
@@ -0,0 +1,91 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+    constant USE_DUMMY_READOUT      : integer := c_NO;  --use slowcontrol for readout, no trigger logic
+    
+--Run wih 125 MHz instead of 100 MHz     
+    constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!  
+    constant USE_EXTERNALCLOCK      : integer := c_NO;  --not implemented yet!  
+    
+--Use sync mode, RX clock for all parts of the FPGA
+    constant USE_RXCLOCK            : integer := c_NO;  --not implemented yet!
+    
+   
+--Address settings   
+    constant INIT_ADDRESS           : std_logic_vector := x"F30a";
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
+   
+--ADC sampling frequency (only 40 MHz supported a.t.m.)
+    constant ADC_SAMPLING_RATE      : integer := 40;
+    
+--These are currently used for the included features table only
+    constant ADC_PROCESSING_TYPE    : integer := 0;
+    constant ADC_BASELINE_LOGIC     : integer := c_YES;
+    constant ADC_TRIGGER_LOGIC      : integer := c_YES;
+    constant ADC_CHANNELS           : integer := 48;
+    
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration 
+------------------------------------------------------------------------------
+    type intlist_t is array(0 to 7) of integer;
+    type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+    constant HW_INFO_BASE            : unsigned(31 downto 0) := x"91009000";
+    
+    constant CLOCK_FREQUENCY_ARR  : intlist_t := (100,125, others => 0);
+    constant MEDIA_FREQUENCY_ARR  : intlist_t := (200,125, others => 0);
+                          
+  --declare constants, filled in body                          
+    constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
+    constant CLOCK_FREQUENCY      : integer;
+    constant MEDIA_FREQUENCY      : integer;
+    constant INCLUDED_FEATURES      : std_logic_vector(63 downto 0);
+    
+    
+end;
+
+package body config is
+--compute correct configuration mode
+  
+  constant HARDWARE_INFO        : std_logic_vector(31 downto 0) := std_logic_vector(
+                                      HW_INFO_BASE );
+  constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
+  constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+
+  
+  
+function generateIncludedFeatures return std_logic_vector is
+  variable t : std_logic_vector(63 downto 0);
+begin
+  t               := (others => '0');
+  t(63 downto 56) := std_logic_vector(to_unsigned(4,8)); --table version 2
+  t(7 downto 0)   := std_logic_vector(to_unsigned(ADC_SAMPLING_RATE,8));
+  t(11 downto 8)  := std_logic_vector(to_unsigned(ADC_PROCESSING_TYPE,4)); --processing type
+  t(14 downto 14) := std_logic_vector(to_unsigned(ADC_BASELINE_LOGIC,1));
+  t(15 downto 15) := std_logic_vector(to_unsigned(ADC_TRIGGER_LOGIC,1));
+  t(23 downto 16) := std_logic_vector(to_unsigned(ADC_CHANNELS,8));
+  t(42 downto 42) := "1"; --std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+  t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+  t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+  t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1));
+  t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+  t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1));
+  return t;
+end function;  
+
+  constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;    
+
+end package body;
\ No newline at end of file

diff --git a/mupix/MupixSoda/sources/FrameGenerator.vhd b/mupix/MupixSoda/sources/FrameGenerator.vhd
new file mode 100644 (file)
index 0000000..935a6dc
--- /dev/null
+++ b/mupix/MupixSoda/sources/FrameGenerator.vhd
@@ -0,0 +1,96 @@
+--FrameGenerator soll Testdatenpakete fuer SODA erzeugen
+--Vordefinierte Beginn und Endsequenz
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity FrameGenerator is
+    port(
+        clk:   in std_logic;           --Taktsignal
+        reset: in std_logic;           --Reset
+        trigger: in std_logic;         --Startsignal zum Senden von Daten (wuerde sonst an MuPix gehen)
+        data_out: out std_logic_vector(31 downto 0); --Datenpaket variabler Laenge, immer 32 Bit lang
+        data_valid:out std_logic      -- 1, wenn relevante Daten gesendet und mitgeschrieben werden sollte
+           );
+end FrameGenerator;
+ 
+architecture dataGeneration of FrameGenerator is
+    component LinearFeedbackShiftRegister
+        Port (
+           lfsr_seed : in STD_LOGIC_VECTOR(3 downto 0);
+           output_number : out STD_LOGIC_VECTOR(3 downto 0);
+           clock : in std_logic;
+           reset : in std_logic;
+           start : in std_logic
+           );
+    end component;
+        
+    type ZUSTAENDE is (waiting, header, data, trailer);
+    signal ZustandJetzt, Folge_Zustand: ZUSTAENDE;
+    signal counter: integer range 0 to 2**4 - 1; -- veraenderliches Datenpaket
+    signal trigger_edge : std_logic_vector(1 downto 0) := "00";
+    signal lfsr_value, lfsr_value_i: std_logic_vector(3 downto 0); -- neuer Wert, der aus dem LinerFeedbackShiftRegister kommt
+    signal start_signal : std_logic := '0';
+    
+begin  
+
+    lfsr1: LinearFeedbackShiftRegister port map ( clock=>clk, reset=>reset,output_number =>lfsr_value, lfsr_seed => "0101", start => start_signal);   
+    
+    trigger_edge_detect : process(clk)
+    begin
+       if  rising_edge(clk) then
+         if reset = '1' then 
+            trigger_edge <= "00";
+         else
+            trigger_edge <= trigger_edge(0) & trigger;--dranhaengen beim vector, 01 ist der uebergang, der den Trigger darstellt
+         end if;
+       end if; 
+    end process trigger_edge_detect;
+
+    Z_Aenderung: process(clk)
+    begin
+        if rising_edge(clk) then
+        case ZustandJetzt is
+            when waiting => data_valid <= '0';
+                            data_out <= (others => '0');
+                            if trigger_edge = "01" then
+                                ZustandJetzt <= header;
+                            else
+                                ZustandJetzt <= waiting;
+                            end if;
+            
+            when header => data_valid <= '1';
+                           data_out <= X"FABEABBA";
+                           ZustandJetzt <= data;
+                           counter <= 0;
+                           lfsr_value_i <= lfsr_value;
+                           
+           when data =>    counter <= counter + 1;
+                           if counter < to_integer(unsigned(lfsr_value_i)) then
+                            data_valid <= '1';
+                            data_out <= std_logic_vector(to_unsigned(counter, 32));
+                            ZustandJetzt <= data;
+                           else
+                            ZustandJetzt <= trailer;                           
+                           end if;                             
+           
+           when trailer => data_valid <= '1';
+                           data_out <= X"BEEFBEEF";
+                           ZustandJetzt <= waiting;
+                            
+        end case;
+        end if;
+    end process Z_Aenderung;
+    
+    lfsr_val: process (clk)
+    begin
+        if (rising_edge(clk)) then
+            if   ZustandJetzt = header then
+                start_signal <= '1';
+            elsif ZustandJetzt = trailer then
+                start_signal <= '0';
+            end if;
+        end if;
+    end process lfsr_val;
+
+end dataGeneration;

diff --git a/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd b/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd
new file mode 100644 (file)
index 0000000..bfdfda7
--- /dev/null
+++ b/mupix/MupixSoda/sources/LinearFeedbackShiftRegister.vhd
@@ -0,0 +1,46 @@
+
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity LinearFeedbackShiftRegister is
+    Port (
+           lfsr_seed : in STD_LOGIC_VECTOR(3 downto 0);
+           output_number : out STD_LOGIC_VECTOR(3 downto 0);
+           clock : in std_logic;
+           reset : in std_logic;
+           start : in std_logic
+           );
+end LinearFeedbackShiftRegister;
+
+architecture Behavioral of LinearFeedbackShiftRegister is
+
+signal lfsr_speicher : std_logic_vector(3 downto 0);
+signal enable : std_logic := '0';
+
+begin
+output_number <= lfsr_speicher;
+
+lfsr_output: process(clock, reset) begin
+    if (reset = '1') then
+        lfsr_speicher <= (others => '1');
+        enable <='0';
+    elsif rising_edge(clock) then
+        if (start ='1' and enable = '0') then
+            lfsr_speicher <= lfsr_seed;
+            enable <= '1';
+        elsif (start = '1' and enable = '1') then
+            lfsr_speicher(3) <= lfsr_speicher(0);
+            lfsr_speicher(2) <= lfsr_speicher(3) xor lfsr_speicher(0);
+            lfsr_speicher(1) <= lfsr_speicher(2);
+            lfsr_speicher(0) <= lfsr_speicher(1);
+        end if;
+    end if;
+end process lfsr_output;
+
+end Behavioral;

diff --git a/mupix/MupixSoda/sources/SodaBoard.vhd b/mupix/MupixSoda/sources/SodaBoard.vhd
new file mode 100644 (file)
index 0000000..52b3bc1
--- /dev/null
+++ b/mupix/MupixSoda/sources/SodaBoard.vhd
@@ -0,0 +1,110 @@
+----------------------------------------------------------
+-- Modul to read out and use a frame generator that generates and sends test data for the soda module
+-- T. Roethemeyer RUB
+----------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sodaBoard is
+       port(
+               clk_in                        : in std_logic ;                    --system clock
+               reset_in                      : in std_logic ;                    -- system reset 
+               -- Slave bus               
+                           SLV_READ_IN           : in  std_logic;                    -- data shall be read
+                       SLV_WRITE_IN          : in  std_logic;                    -- incoming data is meant for writing into some register
+                       SLV_DATA_OUT          : out std_logic_vector(31 downto 0);--
+                       SLV_DATA_IN           : in  std_logic_vector(31 downto 0);--
+                       SLV_ADDR_IN           : in  std_logic_vector(15 downto 0);-- defines the address which shall be read or written
+                       SLV_ACK_OUT           : out std_logic;                    -- high if data is put out
+                       SLV_NO_MORE_DATA_OUT  : out std_logic;                    -- 
+                       SLV_UNKNOWN_ADDR_OUT  : out std_logic                   --
+       );
+end sodaBoard;
+
+architecture Behavioral of sodaBoard is
+       ----------------------------------
+       --component of the frame generator
+       component FrameGenerator is
+       port(
+               clk:   in std_logic;                         -- Taktsignal
+               reset: in std_logic;                         -- Reset
+               trigger: in std_logic;                       -- Startsignal zum Senden von Daten (wuerde sonst an MuPix gehen)
+               data_out: out std_logic_vector(31 downto 0); -- Datenpaket variabler Laenge, immer 32 Bit lang
+               data_valid:out std_logic                     -- 1, wenn relevante Daten gesendet und mitgeschrieben werden sollte
+            );
+       end component FrameGenerator;
+       ----------------------------------
+       --signals
+       signal readpointer, writepointer : integer range 0 to 17 := 0;            -- pointers that tell, which one of the max 18 words shall be read or written  
+       signal memory                    : std_logic_vector (18*32 - 1 downto 0) := (others => '0'); -- vector that can contain up to 18 32-bit words
+       signal single_word               : std_logic_vector (31 downto 0);        -- contains the actual word which is written out from the frame generator
+       signal start_generation          : std_logic := '0';                      -- start signal for the frame generator
+       signal data_valid                : std_logic := '0';                      -- logic that tells whether relevant data is put out from the frame generator
+    signal known_word                : std_logic_vector(31 downto 0) := x"abcdefab";
+       begin
+       -- port map for frame generator
+       framegen1: FrameGenerator port map( clk => clk_in, reset => reset_in, trigger => start_generation, data_out => single_word, data_valid => data_valid);
+
+       -----------------------------------------------------------
+       --TRB SLV-BUS Handler
+       ------------------------------------------------------------
+       --Address Equivalents:
+       --0x0001: gen trigger
+       --0x0002: read word/write readpointer
+       slv_bus_handler: process (clk_in) is
+       begin
+               if rising_edge(clk_in) then
+                       slv_data_out         <= (others => '0');
+                       slv_ack_out          <= '0';
+                       slv_no_more_data_out <= '0';
+                       slv_unknown_addr_out <= '0';
+                 if (slv_write_in = '1') then
+                       case slv_addr_in is
+                               when x"0001" =>                                   -- set trigger/start generation value
+                                       start_generation     <= slv_data_in(0);
+                                       slv_ack_out          <= '1';
+                               when x"0002" =>                                   -- write: readpointers value changing (word that might be read later)
+                                   if (to_integer(unsigned(slv_data_in(4 downto 0))) < 19) then
+                                          readpointer          <= to_integer(unsigned(slv_data_in(4 downto 0)));
+                                          slv_ack_out          <= '1';
+                   else
+                       readpointer <=  0;
+                       slv_ack_out <= '0';
+                   end if;
+                when x"0003" => known_word (7 downto 0) <= slv_data_in(7 downto 0);
+                                slv_ack_out <= '1';
+                               when others  =>                                   -- no useful address put in
+                                       slv_unknown_addr_out <= '1';
+                       end case;
+                 end if;
+               if slv_read_in = '1' then
+                       case slv_addr_in is
+                               when x"0001" =>                                   -- read trigger value
+                                       slv_data_out(0)      <= start_generation;
+                                       slv_ack_out          <= '1';
+                               when x"0002" =>                                   -- read: get x-th word of the memory, value stored in the readpointer
+                                       slv_data_out         <= memory(((readpointer + 1)*32 - 1) downto readpointer*32);
+                                       slv_ack_out          <= '1';
+                when x"0003" => slv_data_out <= known_word;
+                                slv_ack_out <= '1';
+                               when others  =>                                   -- no useful address put in
+                                       slv_unknown_addr_out <= '1';
+                       end case;
+                 end if;
+               end if;
+       end process slv_bus_handler;
+
+       word_generation: process (clk_in) is
+       begin
+               if reset_in = '1' then
+                       writepointer <= 0;
+                       memory <= (others => '0');         --reset clears memory and current value of writepointer
+               elsif rising_edge(clk_in) then
+                       if data_valid = '1' then
+                               memory ( (writepointer +1)*32 -1 downto writepointer*32 ) <= single_word;
+                               writepointer <= writepointer + 1;
+                       end if;
+               end if;
+       end process;    
+end architecture;

diff --git a/mupix/MupixSoda/trb3_periph.p2t b/mupix/MupixSoda/trb3_periph.p2t
new file mode 100644 (file)
index 0000000..995161f
--- /dev/null
+++ b/mupix/MupixSoda/trb3_periph.p2t
@@ -0,0 +1,20 @@
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 11
+-c 1
+-e 2
+-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:

diff --git a/mupix/MupixSoda/trb3_periph.p3t b/mupix/MupixSoda/trb3_periph.p3t
new file mode 100644 (file)
index 0000000..bf0053f
--- /dev/null
+++ b/mupix/MupixSoda/trb3_periph.p3t
@@ -0,0 +1,5 @@
+-rem
+-distrce
+-log "trb3_periph.log"
+-o "trb3_periph.csv"
+-pr "trb3_periph.prf"

diff --git a/mupix/MupixSoda/trb3_periph.prj b/mupix/MupixSoda/trb3_periph.prj
new file mode 100644 (file)
index 0000000..baaaafc
--- /dev/null
+++ b/mupix/MupixSoda/trb3_periph.prj
@@ -0,0 +1,151 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr 
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../../base/trb3_components.vhd"
+
+#trbnet components
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+#ip cores for mupix design
+add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd"
+
+#MuPix Files
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+add_file -vhdl -lib "work" "sources/FrameGenerator.vhd"
+add_file -vhdl -lib "work" "sources/LinearFeedbackShiftRegister.vhd"
+add_file -vhdl -lib "work" "sources/SodaBoard.vhd"

diff --git a/mupix/MupixSoda/trb3_periph.vhd b/mupix/MupixSoda/trb3_periph.vhd
new file mode 100644 (file)
index 0000000..c8ef0d7
--- /dev/null
+++ b/mupix/MupixSoda/trb3_periph.vhd
@@ -0,0 +1,587 @@
+-------------------------------------------------------------------------------
+--trb3_periph for MuPix Version 8
+--Tobias Weber
+--Ruhr Universitaet Bochum
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+library ecp3;
+use ecp3.components.all;
+
+
+entity trb3_periph is
+  port(
+    --Clocks
+    --CLK_GPLL_RIGHT       : in    std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
+    --CLK_GPLL_LEFT        : in    std_logic;  --Clock Manager 1/(2468), 125 MHz
+    --CLK_PCLK_LEFT        : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left!
+    CLK_PCLK_RIGHT       : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+    --Trigger
+    TRIGGER_LEFT         : in    std_logic;  --left side trigger input from fan-out
+    TRIGGER_RIGHT        : in    std_logic;  --right side trigger input from fan-out
+    --Serdes
+    CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
+    CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
+    SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
+    SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
+    --SERDES_ADDON_TX      : out   std_logic_vector(11 downto 0);
+    --SERDES_ADDON_RX      : in    std_logic_vector(11 downto 0);
+    --Inter-FPGA Communication
+    FPGA5_COMM           : inout std_logic_vector(11 downto 0);
+                                        --Bit 0/1 input, serial link RX active
+                                        --Bit 2/3 output, serial link TX active
+
+    
+    --Flash ROM & Reboot
+    FLASH_CLK  : out   std_logic;
+    FLASH_CS   : out   std_logic;
+    FLASH_DIN  : out   std_logic;
+    FLASH_DOUT : in    std_logic;
+    PROGRAMN   : out   std_logic;       --reboot FPGA
+    --Misc
+    TEMPSENS   : inout std_logic;       --Temperature Sensor
+    CODE_LINE  : in    std_logic_vector(1 downto 0);
+    LED_GREEN  : out   std_logic;
+    LED_ORANGE : out   std_logic;
+    LED_RED    : out   std_logic;
+    LED_YELLOW : out   std_logic;
+    --SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
+    --Test Connectors
+    TEST_LINE  : out   std_logic_vector(15 downto 0)
+    );
+
+  attribute syn_useioff                  : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN     : signal is false;
+  attribute syn_useioff of LED_ORANGE    : signal is false;
+  attribute syn_useioff of LED_RED       : signal is false;
+  attribute syn_useioff of LED_YELLOW    : signal is false;
+  attribute syn_useioff of TEMPSENS      : signal is false;
+  attribute syn_useioff of PROGRAMN      : signal is false;
+  attribute syn_useioff of CODE_LINE     : signal is false;
+  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
+  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+  --important signals
+  attribute syn_useioff of FLASH_CLK     : signal is true;
+  attribute syn_useioff of FLASH_CS      : signal is true;
+  attribute syn_useioff of FLASH_DIN     : signal is true;
+  attribute syn_useioff of FLASH_DOUT    : signal is true;
+  attribute syn_useioff of FPGA5_COMM    : signal is true;
+  attribute syn_useioff of TEST_LINE     : signal is true;
+  --attribute syn_useioff of INP           : signal is false;
+  --attribute syn_useioff of DAC_SDO       : signal is true;
+  --attribute syn_useioff of DAC_SDI       : signal is true;
+  --attribute syn_useioff of DAC_SCK       : signal is true;
+  --attribute syn_useioff of DAC_CS        : signal is true;
+
+end entity;
+
+
+architecture trb3_periph_arch of trb3_periph is
+
+       component SodaBoard is
+        port (
+               clk_in                        : in std_logic ;                    --system clock
+               reset_in                      : in std_logic ;                    -- system reset 
+               -- Slave bus               
+               SLV_READ_IN           : in  std_logic;                    -- data shall be read
+               SLV_WRITE_IN          : in  std_logic;                    -- incoming data is meant for writing into some register
+               SLV_DATA_OUT          : out std_logic_vector(31 downto 0);--
+               SLV_DATA_IN           : in  std_logic_vector(31 downto 0);--
+               SLV_ADDR_IN           : in  std_logic_vector(15 downto 0);-- defines the address which shall be read or written
+               SLV_ACK_OUT           : out std_logic;                    -- high if data is put out
+               SLV_NO_MORE_DATA_OUT  : out std_logic;                    -- 
+               SLV_UNKNOWN_ADDR_OUT  : out std_logic                   --
+       );
+       end component;
+               
+
+  --Constants
+  constant REGIO_NUM_STAT_REGS : integer := 5;
+  constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+  
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep              : boolean;
+  attribute syn_preserve          : boolean;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i  : std_logic;
+  signal trg_data_valid_i       : std_logic;
+  signal trg_timing_valid_i     : std_logic;
+  signal trg_notiming_valid_i   : std_logic;
+  signal trg_invalid_i          : std_logic;
+  signal trg_type_i             : std_logic_vector(3 downto 0);
+  signal trg_number_i           : std_logic_vector(15 downto 0);
+  signal trg_code_i             : std_logic_vector(7 downto 0);
+  signal trg_information_i      : std_logic_vector(23 downto 0);
+  signal trg_int_number_i       : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i     : std_logic;
+  signal trg_timeout_detected_i : std_logic;
+  signal trg_spurious_trg_i     : std_logic;
+  signal trg_missing_tmg_trg_i  : std_logic;
+  signal trg_spike_detected_i   : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+  signal spidac_read_en   : std_logic;
+  signal spidac_write_en  : std_logic;
+  signal spidac_data_in   : std_logic_vector(31 downto 0);
+  signal spidac_addr      : std_logic_vector(4 downto 0);
+  signal spidac_data_out  : std_logic_vector(31 downto 0);
+  signal spidac_ack       : std_logic;
+  signal spidac_busy      : std_logic;
+
+  signal dac_cs_i  : std_logic_vector(3 downto 0);
+  signal dac_sck_i : std_logic;
+  signal dac_sdi_i : std_logic;
+
+  signal spi_bram_addr : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+  signal spi_bram_we   : std_logic;
+
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
+
+  --common reset signals for mupix frontends
+  signal sodaboard_regio_addr_in_0          : std_logic_vector (15 downto 0) := (others => '0');
+  signal sodaboard_regio_data_in_0          : std_logic_vector (31 downto 0);
+  signal sodaboard_regio_data_out_0         : std_logic_vector (31 downto 0);
+  signal sodaboard_regio_read_enable_in_0   : std_logic;
+  signal sodaboard_regio_write_enable_in_0  : std_logic;
+  signal sodaboard_regio_timeout_in_0       : std_logic;
+  signal sodaboard_regio_ack_out_0          : std_logic;
+  signal sodaboard_regio_no_more_data_out_0 : std_logic;
+  signal sodaboard_regio_unknown_addr_out_0 : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_PCLK_RIGHT,
+      RESET => '0',
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
+      LOCK  => pll_lock
+      );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+    generic map(
+      SERDES_NUM  => 1,                 --number of serdes in quad
+      EXT_CLOCK   => c_NO,              --use internal clock
+      USE_200_MHZ => c_YES,             --run on 200 MHz clock
+      USE_125_MHZ => c_NO,
+      USE_CTC     => c_NO
+      )
+    port map(
+      CLK                => clk_200_i,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_INT_RX(2),
+      SD_RXD_N_IN        => SERDES_INT_RX(3),
+      SD_TXD_P_OUT       => SERDES_INT_TX(2),
+      SD_TXD_N_OUT       => SERDES_INT_TX(3),
+      SD_REFCLK_P_IN     => open,
+      SD_REFCLK_N_IN     => open,
+      SD_PRSNT_N_IN      => FPGA5_COMM(0),
+      SD_LOS_IN          => FPGA5_COMM(0),
+      SD_TXDIS_OUT       => FPGA5_COMM(2),
+      -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+    generic map(
+      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,  --16 stat reg
+      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,  --8 cotrol reg
+      ADDRESS_MASK              => x"FFFF",
+      BROADCAST_BITMASK         => x"FF",
+      BROADCAST_SPECIAL_ADDR    => x"48",
+      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+      REGIO_HARDWARE_VERSION    => x"9100_6000",
+      REGIO_INIT_ADDRESS        => x"1100",
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+      CLOCK_FREQUENCY           => 125,
+      TIMING_TRIGGER_RAW        => c_YES,
+      --Configure data handler
+      DATA_INTERFACE_NUMBER     => 1,       --number of FEE Cards
+      DATA_BUFFER_DEPTH         => 13,                   --13
+      DATA_BUFFER_WIDTH         => 32,
+      DATA_BUFFER_FULL_THRESH   => 2**13-800,            --2**13-1024
+      TRG_RELEASE_AFTER_DATA    => c_YES,
+      HEADER_BUFFER_DEPTH       => 9,
+      HEADER_BUFFER_FULL_THRESH => 2**9-16
+      )
+    port map(
+      CLK                => clk_100_i,
+      RESET              => reset_i,
+      CLK_EN             => '1',
+      MED_DATAREADY_OUT  => med_dataready_out,           -- open,  --
+      MED_DATA_OUT       => med_data_out,                -- open,  --
+      MED_PACKET_NUM_OUT => med_packet_num_out,          -- open,  --
+      MED_READ_IN        => med_read_in,
+      MED_DATAREADY_IN   => med_dataready_in,
+      MED_DATA_IN        => med_data_in,
+      MED_PACKET_NUM_IN  => med_packet_num_in,
+      MED_READ_OUT       => med_read_out,                -- open,  --
+      MED_STAT_OP_IN     => med_stat_op,
+      MED_CTRL_OP_OUT    => med_ctrl_op,
+
+      --Timing trigger in
+      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      --LVL1 trigger to FEE
+      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+      LVL1_TRG_TYPE_OUT        => trg_type_i,
+      LVL1_TRG_NUMBER_OUT      => trg_number_i,
+      LVL1_TRG_CODE_OUT        => trg_code_i,
+      LVL1_TRG_INFORMATION_OUT => trg_information_i,
+      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+
+      --Response from FEE, i.e. MuPix 
+      FEE_TRG_RELEASE_IN(0)                      => open,
+      FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => open,
+      FEE_DATA_IN(0*32+31 downto 0*32)           => open,
+      FEE_DATA_WRITE_IN(0)                       => open,
+      FEE_DATA_FINISHED_IN(0)                    => open,
+      FEE_DATA_ALMOST_FULL_OUT(0)                => open,
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+      REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+      REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+      REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+      REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+      BUS_ADDR_OUT         => regio_addr_out,
+      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+      BUS_DATA_OUT         => regio_data_out,
+      BUS_DATA_IN          => regio_data_in,
+      BUS_DATAREADY_IN     => regio_dataready_in,
+      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+      BUS_WRITE_ACK_IN     => regio_write_ack_in,
+      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+      BUS_TIMEOUT_OUT      => regio_timeout_out,
+      ONEWIRE_INOUT        => TEMPSENS,
+      ONEWIRE_MONITOR_OUT  => open,
+
+      TIME_GLOBAL_OUT         => global_time,
+      TIME_LOCAL_OUT          => local_time,
+      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+      TIME_TICKS_OUT          => timer_ticks,
+
+      STAT_DEBUG_IPU              => open,
+      STAT_DEBUG_1                => open,
+      STAT_DEBUG_2                => open,
+      STAT_DEBUG_DATA_HANDLER_OUT => open,
+      STAT_DEBUG_IPU_HANDLER_OUT  => open,
+      STAT_TRIGGER_OUT            => open,
+      CTRL_MPLEX                  => (others => '0'),
+      IOBUF_CTRL_GEN              => (others => '0'),
+      STAT_ONEWIRE                => open,
+      STAT_ADDR_DEBUG             => open,
+      DEBUG_LVL1_HANDLER_OUT      => open
+      );
+
+  timing_trg_received_i <= TRIGGER_LEFT;
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER               => 3,
+      PORT_ADDRESSES            => (0 => x"d000",  -- spi master
+                         1      => x"d100",        -- spi memory
+                         2      => x"c000",        -- SodaGen
+                         others => x"0000"),
+      PORT_ADDR_MASK            => (0 => 1,
+                         1      => 6,         
+                         2      => 12,
+                         others => 0)
+      )
+    port map(
+      CLK   => clk_100_i,
+      RESET => reset_i,
+
+      DAT_ADDR_IN          => regio_addr_out,
+      DAT_DATA_IN          => regio_data_out,
+      DAT_DATA_OUT         => regio_data_in,
+      DAT_READ_ENABLE_IN   => regio_read_enable_out,
+      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+      DAT_TIMEOUT_IN       => regio_timeout_out,
+      DAT_DATAREADY_OUT    => regio_dataready_in,
+      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+      --Bus Handler (SPI CTRL)
+      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+      BUS_TIMEOUT_OUT(0)                  => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+      BUS_DATAREADY_IN(0)                 => spictrl_ack,
+      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+      BUS_UNKNOWN_ADDR_IN(0)              => '0',
+
+      --Bus Handler (SPI Memory)           
+      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+      BUS_TIMEOUT_OUT(1)                  => open,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(1)                 => spimem_ack,
+      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_NO_MORE_DATA_IN(1)              => '0',
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+
+      --Common Reset
+      BUS_READ_ENABLE_OUT(2)               => sodaboard_regio_read_enable_in_0,
+      BUS_WRITE_ENABLE_OUT(2)              => sodaboard_regio_write_enable_in_0,
+      BUS_DATA_OUT(2*32+31 downto 2*32)    => sodaboard_regio_data_in_0,
+      BUS_ADDR_OUT(2*16+11 downto 2*16)    => sodaboard_regio_addr_in_0(11 downto 0),
+      BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+      BUS_TIMEOUT_OUT(2)                   => open,
+      BUS_DATA_IN(2*32+31 downto 2*32)     => sodaboard_regio_data_out_0,
+      BUS_DATAREADY_IN(2)                  => sodaboard_regio_ack_out_0,
+      BUS_WRITE_ACK_IN(2)                  => sodaboard_regio_ack_out_0,
+      BUS_NO_MORE_DATA_IN(2)               => sodaboard_regio_no_more_data_out_0,
+      BUS_UNKNOWN_ADDR_IN(2)               => sodaboard_regio_unknown_addr_out_0,
+
+      STAT_DEBUG => open
+      );
+
+---------------------------------------------------------------------------
+-- SodaBoard
+---------------------------------------------------------------------------
+       SodaTest:  SodaBoard 
+        port map(
+               clk_in                 => clk_100_i,                    --system clock
+               reset_in               => reset_i,                    -- system reset 
+               -- Slave bus               
+               SLV_READ_IN           =>sodaboard_regio_read_enable_in_0,                    -- data shall be read
+       SLV_WRITE_IN          =>sodaboard_regio_write_enable_in_0,                    -- incoming data is meant for writing into some register
+       SLV_DATA_OUT          =>sodaboard_regio_data_out_0,--
+       SLV_DATA_IN           =>sodaboard_regio_data_in_0,--
+       SLV_ADDR_IN           =>sodaboard_regio_addr_in_0,-- defines the address which shall be read or written
+       SLV_ACK_OUT           =>sodaboard_regio_ack_out_0,-- high if data is put out
+       SLV_NO_MORE_DATA_OUT  =>sodaboard_regio_no_more_data_out_0,                    -- 
+       SLV_UNKNOWN_ADDR_OUT  =>sodaboard_regio_unknown_addr_out_0                  --
+       );      
+      
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+  THE_SPI_MASTER : spi_master
+    port map(
+      CLK_IN         => clk_100_i,
+      RESET_IN       => reset_i,
+      -- Slave bus
+      BUS_READ_IN    => spictrl_read_en,
+      BUS_WRITE_IN   => spictrl_write_en,
+      BUS_BUSY_OUT   => spictrl_busy,
+      BUS_ACK_OUT    => spictrl_ack,
+      BUS_ADDR_IN(0) => spictrl_addr,
+      BUS_DATA_IN    => spictrl_data_in,
+      BUS_DATA_OUT   => spictrl_data_out,
+      -- SPI connections
+      SPI_CS_OUT     => FLASH_CS,
+      SPI_SDI_IN     => FLASH_DOUT,
+      SPI_SDO_OUT    => FLASH_DIN,
+      SPI_SCK_OUT    => FLASH_CLK,
+      -- BRAM for read/write data
+      BRAM_A_OUT     => spi_bram_addr,
+      BRAM_WR_D_IN   => spi_bram_wr_d,
+      BRAM_RD_D_OUT  => spi_bram_rd_d,
+      BRAM_WE_OUT    => spi_bram_we,
+      -- Status lines
+      STAT           => open
+      );
+
+  -- data memory for SPI accesses
+  THE_SPI_MEMORY : spi_databus_memory
+    port map(
+      CLK_IN        => clk_100_i,
+      RESET_IN      => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN   => spimem_addr,
+      BUS_READ_IN   => spimem_read_en,
+      BUS_WRITE_IN  => spimem_write_en,
+      BUS_ACK_OUT   => spimem_ack,
+      BUS_DATA_IN   => spimem_data_in,
+      BUS_DATA_OUT  => spimem_data_out,
+      -- state machine connections
+      BRAM_ADDR_IN  => spi_bram_addr,
+      BRAM_WR_D_OUT => spi_bram_wr_d,
+      BRAM_RD_D_IN  => spi_bram_rd_d,
+      BRAM_WE_IN    => spi_bram_we,
+      -- Status lines
+      STAT          => open
+      );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => PROGRAMN
+      );
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  LED_GREEN  <= not med_stat_op(9);
+  LED_ORANGE <= not med_stat_op(10);
+  LED_RED    <= timing_trg_received_i;
+  LED_YELLOW <= not med_stat_op(11);
+
+
+end architecture;

diff --git a/mupix/MupixSoda/trb3_periph_constraints.lpf b/mupix/MupixSoda/trb3_periph_constraints.lpf
new file mode 100644 (file)
index 0000000..677710b
--- /dev/null
+++ b/mupix/MupixSoda/trb3_periph_constraints.lpf
@@ -0,0 +1,45 @@
+# BLOCK RESETPATHS ;
+# BLOCK ASYNCPATHS ;
+# BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+  SYSCONFIG MCCLK_FREQ = 20;
+
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  #FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+  #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  #FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+  USE PRIMARY NET "CLK_PCLK_RIGHT_c";
+
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";  
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION "MEDIA_UPLINK" "R102C95D" 13 25;
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+
+
+#################################################################
+# Relax some of the timing constraints
+#################################################################
+#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+#MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
+
+
+#################################################################
+# Constraints for MuPix inputs
+#################################################################
+
+# look at .par and .twr.setup file for clocks 
+# and .mrp or errors
+