Revert "Revert to Diamond 2.1 and TDC v1.6.3"

This reverts commit d0971cde640bbcea1e0de28613bb1cc187652e08.

diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl
index d7a00c5cd1237ddccd5d7a94cd6813cdd56bc720..5c0b8c830533bc026c516945c8d54d90009af73c 100755 (executable)
--- a/ADC/compile_constraints.pl
+++ b/ADC/compile_constraints.pl
@@ -70,24 +70,6 @@ close FILE;
 
 $lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g;
 
-
-# make the LPF diamond 2.1 compatible
-# we assume that generate loops are all named with "gen_"
-#$lpf =~ s#(gen_)(\w+?)\.#$1$2_#gi;
-#$lpf =~ s#(gen_)(\w+?)(\d+)\.#$1$2$3_#gi;
-#$lpf =~ s#(gen_)(\w+?)(\*)\.#$1$2$3_#gi;
-#$lpf =~ s#SimAdder##g;
-sub replace_dot {
-  my @m = @_;
-  $m[1] =~ s/\./_/g;
-  return join("", @m);
-}
-$lpf =~ s#(BLKNAME\s+)(.+?)([;\s])#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#(CELL\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#(NET\s+")(.+?)(")#replace_dot($1,$2,$3)#eg;
-$lpf =~ s#ff_array_en#ff_array_en_i#g;
-
-
 open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!";
 print FILE $lpf;
 close FILE;

diff --git a/ADC/compile_periph_gsi.pl b/ADC/compile_periph_gsi.pl
index 05fb11eaea54d275d47fab3b3034d3d7619f6088..80c3d64ccc69c9b6951a4b960664adb60a035bf5 100755 (executable)
--- a/ADC/compile_periph_gsi.pl
+++ b/ADC/compile_periph_gsi.pl
@@ -9,9 +9,9 @@ use FileHandle;
 ###################################################################################
 #Settings for this project
 my $TOPNAME                      = "trb3_periph_adc"; #Name of top-level entity
-my $lattice_path                 = '/opt/lattice/diamond/2.1_x64';
+my $lattice_path                 = '/opt/lattice/diamond/3.4_x64';
 my $lattice_bin_path             = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
-my $synplify_path                = '/opt/synplicity/F-2012.03-SP1';
+my $synplify_path                = '/opt/synplicity/J-2014.09-SP2';
 my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de';
 my $lm_license_file_for_par      = '1702@hadeb05.gsi.de';
 ###################################################################################

diff --git a/ADC/config.vhd b/ADC/config.vhd
index 138db8d8da0e17f538d4e073d16b96739c43b38b..b3db5e169e6a0ac4eefb392fae558b7e5a0699f0 100644 (file)
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -37,7 +37,7 @@ package config is
   constant ADC_TRIGGER_LOGIC  : integer := c_YES;
   -- ADC channels may be 48 or 36, the latter for enabling compilation 
   -- with TDC and lattice diamond version >2.1
-  constant ADC_CHANNELS       : integer := 48;
+  constant ADC_CHANNELS       : integer := 36;
 
   --Include the TDC (only useful for CFD readout mode) 
   constant INCLUDE_TDC : integer := c_YES;
@@ -50,14 +50,10 @@ package config is
   constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0;
   
   --> change names in constraints file
-  --ring buffer size: 32,64,96,128,dyn
-  --for TDC v1.6.3, only 0,1,3 are valid
-  constant RING_BUFFER_SIZE : integer range 0 to 7 := 3; --ring buffer size:  0, 1, 2,  3,  7   
+  --ring buffer size: 32,64,96,128,dyn    
+  constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size:  0, 1, 2,  3,  7   
 
 
-  constant TDC_CONTROL_REG_NR : integer := 6;
-  
-
   ------------------------------------------------------------------------------
   --End of design configuration
   ------------------------------------------------------------------------------

diff --git a/ADC/tdc_release b/ADC/tdc_release
index 3f0371b3bd681ac8224da969a193e997dd2a381a..043eaed755187bdef540148f05e28b03a930503c 120000 (symlink)
--- a/ADC/tdc_release
+++ b/ADC/tdc_release
@@ -1 +1 @@
-../../tdc/releases/tdc_v1.6.3
\ No newline at end of file
+../../tdc/releases/tdc_v2.1.3/
\ No newline at end of file

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index 87cc00921d1eddb086feffefc79ff1250ff33a5b..4d0fd22023d1843f40a39cf403cf755ca6176128 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -182,6 +182,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is
   
   signal tdc_inputs                  : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0);
   
+  constant TDC_CONTROL_REG_NR : integer := 8;
   type tdc_ctrl_reg_arr_t is array (0 to TDC_CONTROL_REG_NR-1) of std_logic_vector(31 downto 0);
   signal tdc_ctrl_reg_arr : tdc_ctrl_reg_arr_t;
   signal tdc_ctrl_reg   : std_logic_vector(TDC_CONTROL_REG_NR*32-1 downto 0);
@@ -592,7 +593,7 @@ LED_YELLOW <= not med_stat_op(11);
         CLK_READOUT           => clk_100_i,  -- Clock for the readout
         REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
         HIT_IN                => tdc_inputs,      -- Channel start signals
-        HIT_CALIBRATION       => osc_int,  --clk_20_i,    -- Hits for calibrating the TDC
+        HIT_CAL_IN            => osc_int,  --clk_20_i,    -- Hits for calibrating the TDC
         TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
         TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
         --