+++ /dev/null
-# Trigger Logic config registers
-
-!Register table
-
-
-#simple or #Trb3sc Pairs: 3,4,1,2. Trb3 pairs: TRG 4,3 - Clk 3,4
-############################################################################################################
- #TrgEnOut1 TrgEnOut1 TrgEnOut2 TrgEnOut2 TrgEnOut3 TrgEnOut3 TrgEnOut4 TrgEnOut4
- #Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63
- 200 0xdf00 0xdf01 0xdf04 0xdf05 0xdf08 0xdf09 0xdf0c 0xdf0d
-
- #Stretch Stretch Invert Invert StretchVal
- #Ch00-31 Ch32-63 Ch00-31 Ch32-63
- 201 0xdf20 0xdf21 0xdf24 0xdf25 0xdf36
-
- #just enables for 32 channels and 2 outputs
- 202 0xdf00 0xdf04
-
-#single multiplicity
-###########################################################################################################
- #Enable0_0 Enable0_1 23..16Lim0 15..8OutSel
- 100 0xdf33 0xdf35 0xdf32 0xdf34
-
-#triple multiplicity
-###########################################################################################################
- #Enable0_0 Enable0_1 Enable1_0 Enable1_1 Enable2_0 Enable2_1
- 110 0xdf33 0xdf35 0xdf38 0xdf39 0xdf3a 0xdf3b
-
- #31..24 Lim2
- #15..8 Lim1 7..0OutSel1
- #23..16 Lim0 15..8OutSel0 15..8OutSel2
- 111 0xdf32 0xdf34 0xdf37
-
-#4 coincidence registers
-###########################################################################################################
- 300 0xdf40 0xdf41 0xdf42 0xdf43
-
-#simple coincidence
-###########################################################################################################
- 400 0xdf28 0xdf2c 0xdf34 #34 overlap with 111 !
-
-
-#Monitoring for 64 channels
-###########################################################################################################
- 900 0xdf80 0xdf85
- 902 0xdf80
- 901 0xdf81 0xdf86 #invert
-
-
-
-
-
-!Value table
-
-#ECAL TDC: mult 3 output
-##################################
- 0xfe71 100 0x00ffffff 0 0x00030000 0x00000400
-
-#ECAL crate master: output half sectors on 2 outputs
-##################################
- 0x8a00 202 0x00000015 0x00000000
- 0x8a01 202 0x00000051 0x00015100
- 0x8a02 202 0x00000000 0x00015400
- 0x8a03 202 0x00000054 0x00000000
- 0x8a04 202 0x00000015 0x00015400
- 0x8a05 202 0x00000000 0x00015100
-
-
-#STS / Veto TDC: or of all channels, in groups of 16 to master
-##################################
- 0xfe4c 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
- 0xfe4c 201 0xffffffff 0xffff 0xffffffff 0xffff 3
- 0x5010 201 0xffffffff 0xffff 0 0 3
- 0x5011 201 0xffffffff 0xffff 0 0 3
-
- 0x6403 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6413 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6423 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6433 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6464 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6465 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x6474 200 0 0 0 0 0 0 0 0
- 0x6475 200 0 0 0 0 0 0 0 0
- 0x6472 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0x0000ffff 0 #output0 to central broken
-
-# 0x6452 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
-# 0x6453 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
-
-
- 0x5010 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x5011 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
- 0x5012 200 0 0 0 0 0 0 0 0
-
-
-#TOF, fRPC, Veto, STS central FPGA: 'or' of all peripherals to output 3 and 4
-##################################
- 0xfe40 200 0 0 0 0 0xffff 0 0xffff 0
- 0xfe40 201 0xffff 0 0 0 3
-
-#STS
- 0x8b14 200 0 0 0 0 0xfeff 0 0xfeff 0
-
-#TOF, fRPC TDC: forward to central FPGA in groups of 16
- 0xfe47 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0xffffffff 0
- 0x6810 100 0xF 0 0x30000 0x400 #mult2 for PMT signals
-
-#fRPC: 1 and 2 or 3 and 4
- 0x8c00 111 0 0x80000 0
- 0x8c00 300 0x80000703 0x80000F0B 0 0
- 0x8c10 111 0 0x80000 0
- 0x8c10 300 0x80000703 0x80000F0B 0 0
- 0x8c10 200 0 0 0 0 4 0 0 0 #PMT signal
-
-#Veto
- 0x8890 200 0 0 0 0 0x088 0 0 0
- 0x5010 400 0xffff 0xffff0000 0x8 #left/right coincidence for bars
- 0x5011 400 0xffff 0xffff0000 0x8
-
-#Wall: all to second output
- 0x6700 200 0 0 0xffffffff 0
- 0x6701 200 0 0 0xffffffff 0
- 0x6702 200 0 0 0xffffffff 0
- 0x6703 200 0 0 0xffffffff 0
- 0x6710 200 0 0 0xffffffff 0
- 0x6711 200 0 0 0xffffffff 0
- 0x6712 200 0 0 0xffffffff 0
- 0x6713 200 0 0 0xffffffff 0
- 0x6720 200 0 0 0xffffffff 0
- 0x6721 200 0 0 0xffffffff 0
- 0x6722 200 0 0 0xffffffff 0
- 0x6723 200 0 0 0xffffffff 0
-
-
-
-#Start: or of all channels, in groups of 16 on Pair 1-3, or on Pair 4
-##################################
- 0x5000 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
- 0x5003 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
- 0x5001 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
- 0x5002 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
-
-
-
-#iTOF: or of all channels, multiplicity in groups of 12/16 on Pair 2,3,4 and or on 1
-##################################
-# 0x5d00 110 0 0 0 0 0 0
- 0x5d01 110 0x00007bde 0 0x7bde0000 0 0 0x00007bde
-# 0x5d02 110 0 0 0 0 0 0
-# 0x5d03 110 0 0 0 0 0 0
- 0x5d04 110 0x00007bde 0 0x7bde0000 0 0 0x00007bde
-# 0x5d05 110 0 0 0 0 0 0
-# 0x5d00 111 0x03030300 0x00000800 0x00000201
- 0x5d01 111 0x03030300 0x00000800 0x00000201
-# 0x5d02 111 0x03030300 0x00000800 0x00000201
-# 0x5d03 111 0x03030300 0x00000800 0x00000201
- 0x5d04 111 0x03030300 0x00000800 0x00000201
-# 0x5d05 111 0x03030300 0x00000800 0x00000201
-
-# 0x5d00 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
- 0x5d01 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
-# 0x5d02 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
-# 0x5d03 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
- 0x5d04 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
-# 0x5d05 200 0 0 0 0 0x7bde7bde 0x7bde 0 0
-
-#Secondary trigger box
-##################################
- #from ECAL: #0..5: output 1, #8..13 output 2, #6 from pulser
- #from STS: STS-1 #16..19, STS-2 #32..37
- #from fRPC: #42,46
-
-##Setup 1: or of all 12 Ecal half sectors on output 1 - needs update
-#Setup 2: or of all Veto channels
-#Setup 3: or of all STS boards on output 3
-#Setup 4: from fRPC (PMT mult2 plus both ends of RPC)
-
- 0x0100 200 0 0x00003e3e 0x40000 0 0x0000003f 0x000f0000 0x00000c00 0
- 0x0100 201 0 0x00003e3e 0 0 0
-
-
-
-
-
-
-#Monitoring Enable
-##################################
- 0xfe60 900 0xffffffff 0xffffffff
- 0xfe61 900 0xffffffff 0xffffffff
- 0xfe71 900 0xffffffff 0xffffffff
- 0xfe73 900 0xffffffff 0xffffffff
- 0xfe47 902 0xffffffff
- 0xfe4c 900 0xffffffff 0xffff
- 0xfe40 902 0x000fffff
- 0x0100 900 0xffffffff 0xffffffff #secondary box
-
- 0x5000 900 0xffff0015 0x000000ff #disable unused channels in Start 0xffff0000
- 0x5001 900 0xffff00ff 0x0000fc00
- 0x5002 900 0xffff00ff 0x0000fc00
- 0x5003 900 0xfffffc00 0x000000ff
-
- 0x5d00 900 0 0 #innerTOF
- 0x5d01 900 0x7fff7fff 0x7fff
- 0x5d02 900 0 0
- 0x5d03 900 0 0
- 0x5d04 900 0x7fff7fff 0x7fff
- 0x5d05 900 0 0
-
- 0xfe4c 901 0xffffffff 0xffff #invert monitor for STS/Veto
--- /dev/null
+register_trigger_am.db
\ No newline at end of file
--- /dev/null
+# Trigger Logic config registers
+
+!Register table
+
+
+#simple or #Trb3sc Pairs: 3,4,1,2. Trb3 pairs: TRG 4,3 - Clk 3,4
+############################################################################################################
+ #TrgEnOut1 TrgEnOut1 TrgEnOut2 TrgEnOut2 TrgEnOut3 TrgEnOut3 TrgEnOut4 TrgEnOut4
+ #Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63
+ 200 0xdf00 0xdf01 0xdf04 0xdf05 0xdf08 0xdf09 0xdf0c 0xdf0d
+
+ #Stretch Stretch Invert Invert StretchVal
+ #Ch00-31 Ch32-63 Ch00-31 Ch32-63
+ 201 0xdf20 0xdf21 0xdf24 0xdf25 0xdf36
+
+ #just enables for 32 channels and 2 outputs
+ 202 0xdf00 0xdf04
+
+#single multiplicity
+###########################################################################################################
+ #Enable0_0 Enable0_1 23..16Lim0 15..8OutSel
+ 100 0xdf33 0xdf35 0xdf32 0xdf34
+
+#triple multiplicity
+###########################################################################################################
+ #Enable0_0 Enable0_1 Enable1_0 Enable1_1 Enable2_0 Enable2_1
+ 110 0xdf33 0xdf35 0xdf38 0xdf39 0xdf3a 0xdf3b
+
+ #31..24 Lim2
+ #15..8 Lim1 7..0OutSel1
+ #23..16 Lim0 15..8OutSel0 15..8OutSel2
+ 111 0xdf32 0xdf34 0xdf37
+
+#4 coincidence registers
+###########################################################################################################
+ 300 0xdf40 0xdf41 0xdf42 0xdf43
+
+#simple coincidence
+###########################################################################################################
+ 400 0xdf28 0xdf2c 0xdf34 #34 overlap with 111 !
+
+
+#Monitoring for 64 channels
+###########################################################################################################
+ 900 0xdf80 0xdf85
+ 902 0xdf80
+ 901 0xdf81 0xdf86 #invert
+
+
+
+
+
+!Value table
+
+#ECAL TDC: mult 3 output
+##################################
+ 0xfe71 100 0x00ffffff 0 0x00030000 0x00000400
+
+#ECAL crate master: output half sectors on 2 outputs
+##################################
+ 0x8a00 202 0x00000015 0x00000000
+ 0x8a01 202 0x00000051 0x00015100
+ 0x8a02 202 0x00000000 0x00015400
+ 0x8a03 202 0x00000054 0x00000000
+ 0x8a04 202 0x00000015 0x00015400
+ 0x8a05 202 0x00000000 0x00015100
+
+
+#STS / Veto TDC: or of all channels, in groups of 16 to master
+##################################
+ 0xfe4c 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+ 0xfe4c 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+ 0x5010 201 0xffffffff 0xffff 0 0 3
+ 0x5011 201 0xffffffff 0xffff 0 0 3
+
+ 0x6403 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6413 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6423 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6433 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6464 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6465 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6474 200 0 0 0 0 0 0 0 0
+ 0x6475 200 0 0 0 0 0 0 0 0
+ 0x6472 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0x0000ffff 0 #output0 to central broken
+
+# 0x6452 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
+# 0x6453 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
+
+
+ 0x5010 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x5011 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x5012 200 0 0 0 0 0 0 0 0
+
+
+#TOF, fRPC, Veto, STS central FPGA: 'or' of all peripherals to output 3 and 4
+##################################
+ 0xfe40 200 0 0 0 0 0xffff 0 0xffff 0
+ 0xfe40 201 0xffff 0 0 0 3
+
+#STS
+ 0x8b14 200 0 0 0 0 0xfeff 0 0xfeff 0
+
+#TOF, fRPC TDC: forward to central FPGA in groups of 16
+ 0xfe47 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0xffffffff 0
+ 0x6810 100 0xF 0 0x30000 0x400 #mult2 for PMT signals
+
+#fRPC: 1 and 2 or 3 and 4
+ 0x8c00 111 0 0x80000 0
+ 0x8c00 300 0x80000703 0x80000F0B 0 0
+ 0x8c10 111 0 0x80000 0
+ 0x8c10 300 0x80000703 0x80000F0B 0 0
+ 0x8c10 200 0 0 0 0 4 0 0 0 #PMT signal
+
+#Veto
+ 0x8890 200 0 0 0 0 0x088 0 0 0
+ 0x5010 400 0xffff 0xffff0000 0x8 #left/right coincidence for bars
+ 0x5011 400 0xffff 0xffff0000 0x8
+
+#Wall: all to second output
+ 0x6700 200 0 0 0xffffffff 0
+ 0x6701 200 0 0 0xffffffff 0
+ 0x6702 200 0 0 0xffffffff 0
+ 0x6703 200 0 0 0xffffffff 0
+ 0x6710 200 0 0 0xffffffff 0
+ 0x6711 200 0 0 0xffffffff 0
+ 0x6712 200 0 0 0xffffffff 0
+ 0x6713 200 0 0 0xffffffff 0
+ 0x6720 200 0 0 0xffffffff 0
+ 0x6721 200 0 0 0xffffffff 0
+ 0x6722 200 0 0 0xffffffff 0
+ 0x6723 200 0 0 0xffffffff 0
+
+
+
+#Start: or of all channels, in groups of 16 on Pair 1-3, or on Pair 4
+##################################
+ 0x5000 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
+ 0x5003 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
+ 0x5001 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
+ 0x5002 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
+
+
+
+#iTOF: or of all channels, multiplicity in groups of 12/16 on Pair 2,3,4 and or on 1
+##################################
+ 0x5d00 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d01 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d02 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d03 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d04 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d05 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+
+ 0x5d00 111 0x03030300 0x00000800 0x00000201
+ 0x5d01 111 0x03030300 0x00000800 0x00000201
+ 0x5d02 111 0x03030300 0x00000800 0x00000201
+ 0x5d03 111 0x03030300 0x00000800 0x00000201
+ 0x5d04 111 0x03030300 0x00000800 0x00000201
+ 0x5d05 111 0x03030300 0x00000800 0x00000201
+
+ 0x5d00 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d01 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d02 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d03 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d04 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d05 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+
+#Secondary trigger box
+##################################
+ #from ECAL: #0..5: output 1, #8..13 output 2, #6 from pulser
+ #from STS: STS-1 #16..19, STS-2 #32..37
+ #from fRPC: #42,46
+
+##Setup 1: or of all 12 Ecal half sectors on output 1 - needs update
+#Setup 2: or of all Veto channels
+#Setup 3: or of all STS boards on output 3
+#Setup 4: from fRPC (PMT mult2 plus both ends of RPC)
+
+ 0x0100 200 0 0x00003e3e 0x40000 0 0x0000003f 0x000f0000 0x00000c00 0
+ 0x0100 201 0 0x00003e3e 0 0 0
+
+
+
+
+
+
+#Monitoring Enable
+##################################
+ 0xfe60 900 0xffffffff 0xffffffff
+ 0xfe61 900 0xffffffff 0xffffffff
+ 0xfe71 900 0xffffffff 0xffffffff
+ 0xfe73 900 0xffffffff 0xffffffff
+ 0xfe47 902 0xffffffff
+ 0xfe4c 900 0xffffffff 0xffff
+ 0xfe40 902 0x000fffff
+ 0x0100 900 0xffffffff 0xffffffff #secondary box
+
+ 0x5000 900 0xffffffff 0x0000ffff #disable unused channels in Start 0xffff0000
+ 0x5001 900 0xffffffff 0x0000ffff
+ 0x5002 900 0xffffffff 0x0000ffff
+ 0x5003 900 0xffffffff 0x0000ffff
+ 0x5004 900 0xffffffff 0x0000ffff
+ 0x5005 900 0xffffffff 0x0000ffff
+ 0x5006 900 0xffffffff 0x0000ffff
+ 0x5007 900 0xffffffff 0x0000ffff
+
+ 0x5d00 900 0x7fff7fff 0x7fff
+ 0x5d01 900 0x7fff7fff 0x7fff
+ 0x5d02 900 0x7fff7fff 0x7fff
+ 0x5d03 900 0x7fff7fff 0x7fff
+ 0x5d04 900 0x7fff7fff 0x7fff
+ 0x5d05 900 0x7fff7fff 0x7fff
+
+ 0xfe4c 901 0xffffffff 0xffff #invert monitor for STS/Veto
--- /dev/null
+# Trigger Logic config registers
+
+!Register table
+
+
+#simple or #Trb3sc Pairs: 3,4,1,2. Trb3 pairs: TRG 4,3 - Clk 3,4
+############################################################################################################
+ #TrgEnOut1 TrgEnOut1 TrgEnOut2 TrgEnOut2 TrgEnOut3 TrgEnOut3 TrgEnOut4 TrgEnOut4
+ #Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63 Ch00-31 Ch32-63
+ 200 0xdf00 0xdf01 0xdf04 0xdf05 0xdf08 0xdf09 0xdf0c 0xdf0d
+
+ #Stretch Stretch Invert Invert StretchVal
+ #Ch00-31 Ch32-63 Ch00-31 Ch32-63
+ 201 0xdf20 0xdf21 0xdf24 0xdf25 0xdf36
+
+ #just enables for 32 channels and 2 outputs
+ 202 0xdf00 0xdf04
+
+#single multiplicity
+###########################################################################################################
+ #Enable0_0 Enable0_1 23..16Lim0 15..8OutSel
+ 100 0xdf33 0xdf35 0xdf32 0xdf34
+
+#triple multiplicity
+###########################################################################################################
+ #Enable0_0 Enable0_1 Enable1_0 Enable1_1 Enable2_0 Enable2_1
+ 110 0xdf33 0xdf35 0xdf38 0xdf39 0xdf3a 0xdf3b
+
+ #31..24 Lim2
+ #15..8 Lim1 7..0OutSel1
+ #23..16 Lim0 15..8OutSel0 15..8OutSel2
+ 111 0xdf32 0xdf34 0xdf37
+
+#4 coincidence registers
+###########################################################################################################
+ 300 0xdf40 0xdf41 0xdf42 0xdf43
+
+#simple coincidence
+###########################################################################################################
+ 400 0xdf28 0xdf2c 0xdf34 #34 overlap with 111 !
+
+
+#Monitoring for 64 channels
+###########################################################################################################
+ 900 0xdf80 0xdf85
+ 902 0xdf80
+ 901 0xdf81 0xdf86 #invert
+
+
+
+
+
+!Value table
+
+#ECAL TDC: mult 3 output
+##################################
+ 0xfe71 100 0x00ffffff 0 0x00030000 0x00000400
+
+#ECAL crate master: output half sectors on 2 outputs
+##################################
+ 0x8a00 202 0x00000045 0x00000000
+ 0x8a01 202 0x00000051 0x00014500
+ 0x8a02 202 0x00000015 0x00015400
+ 0x8a03 202 0x00000054 0x00015400
+ 0x8a04 202 0x00000015 0x00015400
+ 0x8a05 202 0x00000000 0x00015100
+
+
+#STS / Veto TDC: or of all channels, in groups of 16 to master
+##################################
+
+ 0xfe4c 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+ 0xfe4c 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+ 0x5010 201 0xffffffff 0xffff 0 0 3
+ 0x5011 201 0xffffffff 0xffff 0 0 3
+
+ 0x6403 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6413 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6423 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6433 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6464 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6465 200 0x0000ffff 0 0xffff0000 0 0 0 0 0
+ 0x6474 200 0 0 0 0 0 0 0 0
+ 0x6475 200 0 0 0 0 0 0 0 0
+ 0x6472 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0x0000ffff 0 #output0 to central broken
+
+# 0x6452 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
+# 0x6453 200 0 0 0 0 0 0 0 0 #noisy at 23.12.20
+
+
+
+#
+# #0xfe4c 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# #0xfe4c 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x5010 201 0xffffffff 0xffff 0 0 3
+# 0x5011 201 0xffffffff 0xffff 0 0 3
+#
+# 0x6440 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6440 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6441 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6441 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6442 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6442 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6443 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6443 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6444 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6444 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6445 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6445 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+#
+# 0x6400 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6400 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6401 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6401 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6402 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6402 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+# 0x6403 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0 0
+# 0x6403 201 0xffffffff 0xffff 0xffffffff 0xffff 3
+
+
+#TOF, fRPC, Veto, STS central FPGA: 'or' of all peripherals to output 3 and 4
+##################################
+ 0xfe40 200 0 0 0 0 0xffff 0 0xffff 0
+ 0xfe40 201 0xffff 0 0 0 3
+
+#STS
+ 0x8b14 200 0 0 0 0 0xfeff 0 0xfeff 0
+ 0x8b15 200 0 0 0 0 0x00ff 0 0x00ff 0
+
+#TOF, fRPC TDC: forward to central FPGA in groups of 16
+ 0xfe47 200 0x0000ffff 0 0xffff0000 0 0 0x0000ffff 0xffffffff 0
+ 0x6810 100 0xF 0 0x30000 0x400 #mult2 for PMT signals
+
+#fRPC: 1 and 2 or 3 and 4
+ 0x8c00 111 0 0x80000 0
+ 0x8c00 300 0x80000703 0x80000F0B 0 0
+ 0x8c10 111 0 0x80000 0
+ 0x8c10 300 0x80000703 0x80000F0B 0 0
+ 0x8c10 200 0 0 0 0 4 0 0 0 #PMT signal
+
+#Veto
+ 0x8890 200 0 0 0 0 0x088 0 0 0
+ 0x5010 400 0xffff 0xffff0000 0x8 #left/right coincidence for bars
+ 0x5011 400 0xffff 0xffff0000 0x8
+
+#Wall: all to second output
+ 0x6700 200 0 0 0xffffffff 0
+ 0x6701 200 0 0 0xffffffff 0
+ 0x6702 200 0 0 0xffffffff 0
+ 0x6703 200 0 0 0xffffffff 0
+ 0x6710 200 0 0 0xffffffff 0
+ 0x6711 200 0 0 0xffffffff 0
+ 0x6712 200 0 0 0xffffffff 0
+ 0x6713 200 0 0 0xffffffff 0
+ 0x6720 200 0 0 0xffffffff 0
+ 0x6721 200 0 0 0xffffffff 0
+ 0x6722 200 0 0 0xffffffff 0
+ 0x6723 200 0 0 0xffffffff 0
+
+
+
+#Start: or of all channels, in groups of 16 on Pair 1-3, or on Pair 4
+##################################
+ 0x5000 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
+ 0x5003 200 0 0x000000ff 0xfffffc00 0x000000ff 0x0000fc00 0 0xffff0000 0
+ 0x5001 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
+ 0x5002 200 0 0x0000fc00 0xffff00ff 0x0000fc00 0x000000ff 0 0xffff0000 0
+
+
+
+#iTOF: or of all channels, multiplicity in groups of 12/16 on Pair 2,3,4 and or on 1
+##################################
+ 0x5d00 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d01 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d02 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d03 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d04 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+ 0x5d05 110 0x00000fff 0 0x0fff0000 0 0 0x00000fff
+
+ 0x5d00 111 0x03030300 0x00000800 0x00000201
+ 0x5d01 111 0x03030300 0x00000800 0x00000201
+ 0x5d02 111 0x03030300 0x00000800 0x00000201
+ 0x5d03 111 0x03030300 0x00000800 0x00000201
+ 0x5d04 111 0x03030300 0x00000800 0x00000201
+ 0x5d05 111 0x03030300 0x00000800 0x00000201
+
+ 0x5d00 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d01 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d02 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d03 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d04 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+ 0x5d05 200 0 0 0 0 0x0fff0fff 0x0fff 0 0
+
+#Secondary trigger box
+##################################
+ #from ECAL: #0..5: output 1, #8..13 output 2, #6 from pulser
+ #from STS: STS-1 #16..19, STS-2 #32..37
+ #from fRPC: #42,46
+
+##Setup 1: or of all 12 Ecal half sectors on output 1 - needs update
+#Setup 2: or of all Veto channels
+#Setup 3: or of all STS boards on output 3
+#Setup 4: from fRPC (PMT mult2 plus both ends of RPC)
+
+ 0x0100 200 0 0x00003e3e 0x40000 0 0x0000003f 0x000f0000 0x00000c00 0
+ 0x0100 201 0 0x00003e3e 0 0 0
+
+
+
+
+
+
+#Monitoring Enable
+##################################
+ 0xfe60 900 0xffffffff 0xffffffff
+ 0xfe61 900 0xffffffff 0xffffffff
+ 0xfe71 900 0xffffffff 0xffffffff
+ 0xfe73 900 0xffffffff 0xffffffff
+ 0xfe47 902 0xffffffff
+ 0xfe4c 900 0xffffffff 0xffff
+ 0xfe40 902 0x000fffff
+ 0x0100 900 0xffffffff 0xffffffff #secondary box
+
+ 0xfe74 900 0x7fff7fff 0x00007fff
+
+ 0x5000 900 0xffffffff 0x0000ffff #disable unused channels in Start 0xffff0000
+ 0x5001 900 0xffffffff 0x0000ffff
+ 0x5002 900 0xffffffff 0x0000ffff
+ 0x5003 900 0xffffffff 0x0000ffff
+ 0x5004 900 0xffffffff 0x0000ffff
+ 0x5005 900 0xffffffff 0x0000ffff
+ 0x5006 900 0xffffffff 0x0000ffff
+ 0x5007 900 0xffffffff 0x0000ffff
+
+# 0x5d00 900 0x7fff7fff 0x7fff
+# 0x5d01 900 0x7fff7fff 0x7fff
+# 0x5d02 900 0x7fff7fff 0x7fff
+# 0x5d03 900 0x7fff7fff 0x7fff
+# 0x5d04 900 0x7fff7fff 0x7fff
+# 0x5d05 900 0x7fff7fff 0x7fff
+
+ 0xfe4c 901 0xffffffff 0xffff #invert monitor for STS/Veto
-triggerbox_itof.trbcmd
\ No newline at end of file
+P18_b.txt
\ No newline at end of file
jspc29 / hadesdaq.git / commitdiff