correct non-existent mult registers for channels<=32

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 6d4ca786522b4d6e7598c87dfed8aa7d01b56d84..e3e25f453b14f148b5c7da0b511fec5ad8b0096c 100644 (file)
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -50,7 +50,7 @@ signal coin_enable  : std_logic  := '0';
 signal current_multiplicity0, current_multiplicity1 : unsigned(7 downto 0);
 signal current_multiplicity, set_multiplicity       : unsigned(7 downto 0);
 signal multiplicity_trigger : std_logic := '0';
-signal multiplicity_enable  : std_logic_vector(INPUTS-1 downto 0);
+signal multiplicity_enable  : std_logic_vector(register_bits downto 0);
 signal mult_gated           : std_logic_vector(INPUTS-1 downto 0);
 
 signal set_output_coin, set_output_mult, set_output_simplecoin : std_logic_vector(7 downto 0);
@@ -118,7 +118,7 @@ begin
       set_output_mult <= BUS_RX.data(15 downto 8);
       set_output_coin <= BUS_RX.data(23 downto 16);
       edge_enable     <= BUS_RX.data(31 downto 24);
-    elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS >= 32 then
+    elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
       multiplicity_enable(63 downto 32) <= BUS_RX.data;
     else
       BUS_TX.nack <= '1'; 
@@ -183,7 +183,7 @@ begin
       BUS_TX.data                 <= multiplicity_enable(31 downto 0);
     elsif BUS_RX.addr(6 downto 0) = "0110100" then
       BUS_TX.data <= edge_enable & set_output_coin & set_output_mult & set_output_simplecoin;
-    elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS >= 32 then
+    elsif BUS_RX.addr(6 downto 0) = "0110101" and INPUTS > 32 then
       BUS_TX.data                 <= multiplicity_enable(63 downto 32);
     else  
       BUS_TX.nack <= '1';