*** empty log message ***

diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd
index b5eb11f8e209336a9acba0ab7684b7b069f60506..b810473f9aa9ee27744975074c6df29e10919a71 100644 (file)
--- a/trb_net_sbuf5.vhd
+++ b/trb_net_sbuf5.vhd
@@ -49,6 +49,18 @@ port(
 );\r
 end component fifo_19x16_obuf;\r
 \r
+\r
+--component dbg_reg is\r
+--generic(\r
+--     WIDTH      : integer := 1\r
+--);\r
+--port(\r
+--     DEBUG_IN   : in  std_logic_vector(WIDTH-1 downto 0);\r
+--     DEBUG_OUT  : out std_logic_vector(WIDTH-1 downto 0)\r
+--);\r
+--end component dbg_reg;\r
+\r
+\r
 type STATES is (IDLE, RD1, RD2, RD3, RD4, RD5, WT5, WR5, WD5, DEL);\r
 signal CURRENT_STATE, NEXT_STATE: STATES;\r
 signal bsm_x                 : std_logic_vector(3 downto 0);\r
@@ -63,6 +75,7 @@ signal syn_data              : std_logic_vector(18 downto 0);
 \r
 signal p_wait_x              : std_logic;\r
 signal p_avail_x             : std_logic;\r
+signal p_really_x            : std_logic;\r
 \r
 signal fifo_data_i           : std_logic_vector(18 downto 0);\r
 signal fifo_data_o           : std_logic_vector(18 downto 0);\r
@@ -90,8 +103,30 @@ attribute syn_keep of bsm                 : signal is true;
 attribute syn_hier : string;\r
 attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm";\r
 \r
+--attribute syn_noprune : boolean;\r
+--attribute syn_noprune of THE_DBG_REG : label is true;\r
+--signal my_debug                 : std_logic_vector(26 downto 0);\r
+\r
 begin\r
 \r
+\r
+---------------------------------------------------------------------\r
+-- VHDL / Synplify workaround for fixed nodes... creepy.\r
+---------------------------------------------------------------------\r
+--THE_DBG_REG: dbg_reg\r
+--generic map(\r
+--     WIDTH      => 27\r
+--)\r
+--port map(\r
+--     DEBUG_IN   => my_debug,\r
+--     DEBUG_OUT  => open\r
+--);\r
+--\r
+--my_debug(8 downto 4)   <= fifo_wcnt;\r
+--my_debug(3 downto 0)   <= bsm;\r
+---------------------------------------------------------------------\r
+---------------------------------------------------------------------\r
+\r
 ---------------------------------------------------------------------\r
 -- I/O\r
 ---------------------------------------------------------------------\r
@@ -125,10 +160,11 @@ port map(
        AlmostFull     => fifo_almostfull --open\r
 );\r
 \r
-p_wait_x  <= '1' when (unsigned(fifo_wcnt) > x"0") else '0';\r
-p_avail_x <= '1' when ((unsigned(fifo_wcnt) >= x"2") and (COMB_DATAREADY_IN = '1')) or\r
+p_wait_x   <= '1' when (unsigned(fifo_wcnt) > x"0") else '0';\r
+p_avail_x  <= '1' when ((unsigned(fifo_wcnt) >= x"2") and (COMB_DATAREADY_IN = '1')) or\r
                        (unsigned(fifo_wcnt) >= x"3")\r
-                 else '0';\r
+                  else '0';\r
+p_really_x <= '1' when (unsigned(fifo_wcnt) >= x"3") else '0';\r
 \r
 -- was 3 and 4\r
 \r
@@ -154,7 +190,7 @@ begin
 end process STATE_MEM;\r
 \r
 -- state transitions\r
-STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN )\r
+STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, p_really_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN )\r
 begin\r
        NEXT_STATE      <= IDLE; -- avoid latches\r
        fifo_rd_en_x    <= '0';\r
@@ -215,7 +251,7 @@ begin
                                                else\r
                                                        NEXT_STATE      <= RD5;\r
                                                end if;\r
-               when WR5    =>  if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then\r
+               when WR5    =>  if( (SYN_READ_IN = '1') and (p_really_x = '1') ) then\r
                                                        NEXT_STATE      <= RD2;\r
                                                        fifo_rd_en_x    <= '1';\r
                                                        --syn_dataready_x <= '1';\r