if rising_edge(RX_CLK) then
if RESET = '1' then
fifo_data_in <= (others => '0');
- elsif SYNC_CURRENT = NORMAL_OPERATION_2 then
+ elsif SYNC_CURRENT = NORMAL_OPERATION_2 and CV="00" then
fifo_data_in <= '0' & (not RX_K(0)) & RXD;
fifo_wr_en <= not RX_K(0);
- elsif SYNC_CURRENT = NORMAL_OPERATION_1 then
+ elsif SYNC_CURRENT = NORMAL_OPERATION_1 and CV="00" then
fifo_data_in <= '0' & (not RX_K(1)) & RXD(7 downto 0) & rxd_synch_i(15 downto 8);
- fifo_wr_en <= not RX_K(1);
+ fifo_wr_en <= not rx_k_synch_i(1);
else
fifo_data_in <= (others => '0');
fifo_wr_en <= '0';