\hline
Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\
\hline \hline
- \multirow{11}{*}{0xc0} & \multirow{11}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
- & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
- & & 11-5 & reserved.\\
+ \multirow{13}{*}{0xc0} & \multirow{13}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
+ & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
+ & & 7-5 & reserved.\\
+ & & 8 & Resets the internal counters.\\
+ & & 11-9 & reserved.\\
& & 12 & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
& & 31-13 & reserved.\\
\hline